1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target
*target
,
56 uint32_t num
, uint32_t value
);
57 static void cortex_m_dwt_free(struct target
*target
);
59 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
60 uint32_t *value
, int regnum
)
62 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target
->dbg_msg_enabled
) {
69 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
70 if (retval
!= ERROR_OK
)
74 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
75 if (retval
!= ERROR_OK
)
78 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
79 if (retval
!= ERROR_OK
)
82 if (target
->dbg_msg_enabled
) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
92 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
93 uint32_t value
, int regnum
)
95 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target
->dbg_msg_enabled
) {
102 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
103 if (retval
!= ERROR_OK
)
107 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
108 if (retval
!= ERROR_OK
)
111 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
112 if (retval
!= ERROR_OK
)
115 if (target
->dbg_msg_enabled
) {
116 /* restore DCB_DCRDR - this needs to be in a separate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
125 static int cortex_m_write_debug_halt_mask(struct target
*target
,
126 uint32_t mask_on
, uint32_t mask_off
)
128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
131 /* mask off status bits */
132 cortex_m
->dcb_dhcsr
&= ~((0xFFFFul
<< 16) | mask_off
);
133 /* create new register mask */
134 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
136 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
139 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
141 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
142 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
143 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
148 static int cortex_m_set_maskints_for_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 switch (cortex_m
->isrmasking_mode
) {
152 case CORTEX_M_ISRMASK_AUTO
:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target
, false);
156 case CORTEX_M_ISRMASK_OFF
:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target
, false);
160 case CORTEX_M_ISRMASK_ON
:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target
, true);
164 case CORTEX_M_ISRMASK_STEPONLY
:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
172 static int cortex_m_set_maskints_for_run(struct target
*target
)
174 switch (target_to_cm(target
)->isrmasking_mode
) {
175 case CORTEX_M_ISRMASK_AUTO
:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target
, false);
179 case CORTEX_M_ISRMASK_OFF
:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target
, false);
183 case CORTEX_M_ISRMASK_ON
:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target
, true);
187 case CORTEX_M_ISRMASK_STEPONLY
:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target
, false);
194 static int cortex_m_set_maskints_for_step(struct target
*target
)
196 switch (target_to_cm(target
)->isrmasking_mode
) {
197 case CORTEX_M_ISRMASK_AUTO
:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target
, true);
201 case CORTEX_M_ISRMASK_OFF
:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target
, false);
205 case CORTEX_M_ISRMASK_ON
:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target
, true);
209 case CORTEX_M_ISRMASK_STEPONLY
:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target
, true);
216 static int cortex_m_clear_halt(struct target
*target
)
218 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
219 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
225 /* Read Debug Fault Status Register */
226 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
227 if (retval
!= ERROR_OK
)
230 /* Clear Debug Fault Status */
231 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
232 if (retval
!= ERROR_OK
)
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
239 static int cortex_m_single_step_core(struct target
*target
)
241 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
242 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
249 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
250 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
251 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
252 if (retval
!= ERROR_OK
)
255 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
256 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
257 if (retval
!= ERROR_OK
)
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target
);
267 static int cortex_m_enable_fpb(struct target
*target
)
269 int retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 /* check the fpb is actually enabled */
275 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
276 if (retval
!= ERROR_OK
)
285 static int cortex_m_endreset_event(struct target
*target
)
290 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
291 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
292 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
293 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
294 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
298 if (retval
!= ERROR_OK
)
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
302 /* this register is used for emulated dcc channel */
303 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
304 if (retval
!= ERROR_OK
)
307 /* Enable debug requests */
308 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
309 if (retval
!= ERROR_OK
)
311 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
312 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
313 if (retval
!= ERROR_OK
)
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target
);
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
327 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
328 if (retval
!= ERROR_OK
)
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
336 retval
= cortex_m_enable_fpb(target
);
337 if (retval
!= ERROR_OK
) {
338 LOG_ERROR("Failed to enable the FPB");
342 cortex_m
->fpb_enabled
= true;
344 /* Restore FPB registers */
345 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
346 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
347 if (retval
!= ERROR_OK
)
351 /* Restore DWT registers */
352 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
353 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
355 if (retval
!= ERROR_OK
)
357 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
359 if (retval
!= ERROR_OK
)
361 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
362 dwt_list
[i
].function
);
363 if (retval
!= ERROR_OK
)
366 retval
= dap_run(swjdp
);
367 if (retval
!= ERROR_OK
)
370 register_cache_invalidate(armv7m
->arm
.core_cache
);
372 /* make sure we have latest dhcsr flags */
373 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
378 static int cortex_m_examine_debug_reason(struct target
*target
)
380 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
385 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
386 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
387 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
388 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
389 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
390 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
391 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
392 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
393 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
394 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
395 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
396 target
->debug_reason
= DBG_REASON_DBGRQ
;
398 target
->debug_reason
= DBG_REASON_UNDEFINED
;
404 static int cortex_m_examine_exception_reason(struct target
*target
)
406 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
407 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
408 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
411 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
412 if (retval
!= ERROR_OK
)
414 switch (armv7m
->exception_number
) {
417 case 3: /* Hard Fault */
418 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
419 if (retval
!= ERROR_OK
)
421 if (except_sr
& 0x40000000) {
422 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
423 if (retval
!= ERROR_OK
)
427 case 4: /* Memory Management */
428 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
429 if (retval
!= ERROR_OK
)
431 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
432 if (retval
!= ERROR_OK
)
435 case 5: /* Bus Fault */
436 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
437 if (retval
!= ERROR_OK
)
439 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
440 if (retval
!= ERROR_OK
)
443 case 6: /* Usage Fault */
444 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
445 if (retval
!= ERROR_OK
)
448 case 7: /* Secure Fault */
449 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFSR
, &except_sr
);
450 if (retval
!= ERROR_OK
)
452 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFAR
, &except_ar
);
453 if (retval
!= ERROR_OK
)
456 case 11: /* SVCall */
458 case 12: /* Debug Monitor */
459 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
460 if (retval
!= ERROR_OK
)
463 case 14: /* PendSV */
465 case 15: /* SysTick */
471 retval
= dap_run(swjdp
);
472 if (retval
== ERROR_OK
)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
475 armv7m_exception_string(armv7m
->exception_number
),
476 shcsr
, except_sr
, cfsr
, except_ar
);
480 static int cortex_m_debug_entry(struct target
*target
)
485 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
486 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
487 struct arm
*arm
= &armv7m
->arm
;
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target
);
496 cortex_m_clear_halt(target
);
497 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
498 if (retval
!= ERROR_OK
)
501 retval
= armv7m
->examine_debug_reason(target
);
502 if (retval
!= ERROR_OK
)
505 /* Examine target state and mode
506 * First load register accessible through core debug port */
507 int num_regs
= arm
->core_cache
->num_regs
;
509 for (i
= 0; i
< num_regs
; i
++) {
510 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
512 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
516 xPSR
= buf_get_u32(r
->value
, 0, 32);
518 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
521 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
524 /* Are we in an exception handler */
526 armv7m
->exception_number
= (xPSR
& 0x1FF);
528 arm
->core_mode
= ARM_MODE_HANDLER
;
529 arm
->map
= armv7m_msp_reg_map
;
531 unsigned control
= buf_get_u32(arm
->core_cache
532 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
534 /* is this thread privileged? */
535 arm
->core_mode
= control
& 1
536 ? ARM_MODE_USER_THREAD
539 /* which stack is it using? */
541 arm
->map
= armv7m_psp_reg_map
;
543 arm
->map
= armv7m_msp_reg_map
;
545 armv7m
->exception_number
= 0;
548 if (armv7m
->exception_number
)
549 cortex_m_examine_exception_reason(target
);
551 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
552 arm_mode_name(arm
->core_mode
),
553 buf_get_u32(arm
->pc
->value
, 0, 32),
554 target_state_name(target
));
556 if (armv7m
->post_debug_entry
) {
557 retval
= armv7m
->post_debug_entry(target
);
558 if (retval
!= ERROR_OK
)
565 static int cortex_m_poll(struct target
*target
)
567 int detected_failure
= ERROR_OK
;
568 int retval
= ERROR_OK
;
569 enum target_state prev_target_state
= target
->state
;
570 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
571 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
573 /* Read from Debug Halting Control and Status Register */
574 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
575 if (retval
!= ERROR_OK
) {
576 target
->state
= TARGET_UNKNOWN
;
580 /* Recover from lockup. See ARMv7-M architecture spec,
581 * section B1.5.15 "Unrecoverable exception cases".
583 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
584 LOG_ERROR("%s -- clearing lockup after double fault",
585 target_name(target
));
586 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
587 target
->debug_reason
= DBG_REASON_DBGRQ
;
589 /* We have to execute the rest (the "finally" equivalent, but
590 * still throw this exception again).
592 detected_failure
= ERROR_FAIL
;
594 /* refresh status bits */
595 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
596 if (retval
!= ERROR_OK
)
600 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
601 if (target
->state
!= TARGET_RESET
) {
602 target
->state
= TARGET_RESET
;
603 LOG_INFO("%s: external reset detected", target_name(target
));
608 if (target
->state
== TARGET_RESET
) {
609 /* Cannot switch context while running so endreset is
610 * called with target->state == TARGET_RESET
612 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
613 cortex_m
->dcb_dhcsr
);
614 retval
= cortex_m_endreset_event(target
);
615 if (retval
!= ERROR_OK
) {
616 target
->state
= TARGET_UNKNOWN
;
619 target
->state
= TARGET_RUNNING
;
620 prev_target_state
= TARGET_RUNNING
;
623 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
624 target
->state
= TARGET_HALTED
;
626 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
627 retval
= cortex_m_debug_entry(target
);
628 if (retval
!= ERROR_OK
)
631 if (arm_semihosting(target
, &retval
) != 0)
634 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
636 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
638 retval
= cortex_m_debug_entry(target
);
639 if (retval
!= ERROR_OK
)
642 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
646 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
647 * How best to model low power modes?
650 if (target
->state
== TARGET_UNKNOWN
) {
651 /* check if processor is retiring instructions */
652 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
653 target
->state
= TARGET_RUNNING
;
658 /* Check that target is truly halted, since the target could be resumed externally */
659 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
660 /* registers are now invalid */
661 register_cache_invalidate(armv7m
->arm
.core_cache
);
663 target
->state
= TARGET_RUNNING
;
664 LOG_WARNING("%s: external resume detected", target_name(target
));
665 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
669 /* Did we detect a failure condition that we cleared? */
670 if (detected_failure
!= ERROR_OK
)
671 retval
= detected_failure
;
675 static int cortex_m_halt(struct target
*target
)
677 LOG_DEBUG("target->state: %s",
678 target_state_name(target
));
680 if (target
->state
== TARGET_HALTED
) {
681 LOG_DEBUG("target was already halted");
685 if (target
->state
== TARGET_UNKNOWN
)
686 LOG_WARNING("target was in unknown state when halt was requested");
688 if (target
->state
== TARGET_RESET
) {
689 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
690 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
691 return ERROR_TARGET_FAILURE
;
693 /* we came here in a reset_halt or reset_init sequence
694 * debug entry was already prepared in cortex_m3_assert_reset()
696 target
->debug_reason
= DBG_REASON_DBGRQ
;
702 /* Write to Debug Halting Control and Status Register */
703 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
705 /* Do this really early to minimize the window where the MASKINTS erratum
706 * can pile up pending interrupts. */
707 cortex_m_set_maskints_for_halt(target
);
709 target
->debug_reason
= DBG_REASON_DBGRQ
;
714 static int cortex_m_soft_reset_halt(struct target
*target
)
716 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
717 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
718 uint32_t dcb_dhcsr
= 0;
719 int retval
, timeout
= 0;
721 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
722 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
723 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
724 * core, not the peripherals */
725 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
728 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
729 if (retval
!= ERROR_OK
)
732 /* Enter debug state on reset; restore DEMCR in endreset_event() */
733 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
734 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
735 if (retval
!= ERROR_OK
)
738 /* Request a core-only reset */
739 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
740 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
741 if (retval
!= ERROR_OK
)
743 target
->state
= TARGET_RESET
;
745 /* registers are now invalid */
746 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
748 while (timeout
< 100) {
749 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
750 if (retval
== ERROR_OK
) {
751 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
752 &cortex_m
->nvic_dfsr
);
753 if (retval
!= ERROR_OK
)
755 if ((dcb_dhcsr
& S_HALT
)
756 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
757 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
759 (unsigned) dcb_dhcsr
,
760 (unsigned) cortex_m
->nvic_dfsr
);
761 cortex_m_poll(target
);
762 /* FIXME restore user's vector catch config */
765 LOG_DEBUG("waiting for system reset-halt, "
766 "DHCSR 0x%08x, %d ms",
767 (unsigned) dcb_dhcsr
, timeout
);
776 void cortex_m_enable_breakpoints(struct target
*target
)
778 struct breakpoint
*breakpoint
= target
->breakpoints
;
780 /* set any pending breakpoints */
782 if (!breakpoint
->set
)
783 cortex_m_set_breakpoint(target
, breakpoint
);
784 breakpoint
= breakpoint
->next
;
788 static int cortex_m_resume(struct target
*target
, int current
,
789 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
791 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
792 struct breakpoint
*breakpoint
= NULL
;
796 if (target
->state
!= TARGET_HALTED
) {
797 LOG_WARNING("target not halted");
798 return ERROR_TARGET_NOT_HALTED
;
801 if (!debug_execution
) {
802 target_free_all_working_areas(target
);
803 cortex_m_enable_breakpoints(target
);
804 cortex_m_enable_watchpoints(target
);
807 if (debug_execution
) {
808 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
810 /* Disable interrupts */
811 /* We disable interrupts in the PRIMASK register instead of
812 * masking with C_MASKINTS. This is probably the same issue
813 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
814 * in parallel with disabled interrupts can cause local faults
817 * REVISIT this clearly breaks non-debug execution, since the
818 * PRIMASK register state isn't saved/restored... workaround
819 * by never resuming app code after debug execution.
821 buf_set_u32(r
->value
, 0, 1, 1);
825 /* Make sure we are in Thumb mode */
826 r
= armv7m
->arm
.cpsr
;
827 buf_set_u32(r
->value
, 24, 1, 1);
832 /* current = 1: continue on current pc, otherwise continue at <address> */
835 buf_set_u32(r
->value
, 0, 32, address
);
840 /* if we halted last time due to a bkpt instruction
841 * then we have to manually step over it, otherwise
842 * the core will break again */
844 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
846 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
848 resume_pc
= buf_get_u32(r
->value
, 0, 32);
850 armv7m_restore_context(target
);
852 /* the front-end may request us not to handle breakpoints */
853 if (handle_breakpoints
) {
854 /* Single step past breakpoint at current address */
855 breakpoint
= breakpoint_find(target
, resume_pc
);
857 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
859 breakpoint
->unique_id
);
860 cortex_m_unset_breakpoint(target
, breakpoint
);
861 cortex_m_single_step_core(target
);
862 cortex_m_set_breakpoint(target
, breakpoint
);
867 cortex_m_set_maskints_for_run(target
);
868 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
870 target
->debug_reason
= DBG_REASON_NOTHALTED
;
872 /* registers are now invalid */
873 register_cache_invalidate(armv7m
->arm
.core_cache
);
875 if (!debug_execution
) {
876 target
->state
= TARGET_RUNNING
;
877 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
878 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
880 target
->state
= TARGET_DEBUG_RUNNING
;
881 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
882 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
888 /* int irqstepcount = 0; */
889 static int cortex_m_step(struct target
*target
, int current
,
890 target_addr_t address
, int handle_breakpoints
)
892 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
893 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
894 struct breakpoint
*breakpoint
= NULL
;
895 struct reg
*pc
= armv7m
->arm
.pc
;
896 bool bkpt_inst_found
= false;
898 bool isr_timed_out
= false;
900 if (target
->state
!= TARGET_HALTED
) {
901 LOG_WARNING("target not halted");
902 return ERROR_TARGET_NOT_HALTED
;
905 /* current = 1: continue on current pc, otherwise continue at <address> */
907 buf_set_u32(pc
->value
, 0, 32, address
);
909 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
911 /* the front-end may request us not to handle breakpoints */
912 if (handle_breakpoints
) {
913 breakpoint
= breakpoint_find(target
, pc_value
);
915 cortex_m_unset_breakpoint(target
, breakpoint
);
918 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
920 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
922 armv7m_restore_context(target
);
924 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
926 /* if no bkpt instruction is found at pc then we can perform
927 * a normal step, otherwise we have to manually step over the bkpt
928 * instruction - as such simulate a step */
929 if (bkpt_inst_found
== false) {
930 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
931 /* Automatic ISR masking mode off: Just step over the next
932 * instruction, with interrupts on or off as appropriate. */
933 cortex_m_set_maskints_for_step(target
);
934 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
936 /* Process interrupts during stepping in a way they don't interfere
941 * Set a temporary break point at the current pc and let the core run
942 * with interrupts enabled. Pending interrupts get served and we run
943 * into the breakpoint again afterwards. Then we step over the next
944 * instruction with interrupts disabled.
946 * If the pending interrupts don't complete within time, we leave the
947 * core running. This may happen if the interrupts trigger faster
948 * than the core can process them or the handler doesn't return.
950 * If no more breakpoints are available we simply do a step with
951 * interrupts enabled.
957 * If a break point is already set on the lower half word then a break point on
958 * the upper half word will not break again when the core is restarted. So we
959 * just step over the instruction with interrupts disabled.
961 * The documentation has no information about this, it was found by observation
962 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
963 * suffer from this problem.
965 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
966 * address has it always cleared. The former is done to indicate thumb mode
970 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
971 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
972 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
973 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
974 /* Re-enable interrupts if appropriate */
975 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
976 cortex_m_set_maskints_for_halt(target
);
979 /* Set a temporary break point */
981 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
983 enum breakpoint_type type
= BKPT_HARD
;
984 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
985 /* FPB rev.1 cannot handle such addr, try BKPT instr */
988 retval
= breakpoint_add(target
, pc_value
, 2, type
);
991 bool tmp_bp_set
= (retval
== ERROR_OK
);
993 /* No more breakpoints left, just do a step */
995 cortex_m_set_maskints_for_step(target
);
996 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
997 /* Re-enable interrupts if appropriate */
998 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
999 cortex_m_set_maskints_for_halt(target
);
1001 /* Start the core */
1002 LOG_DEBUG("Starting core to serve pending interrupts");
1003 int64_t t_start
= timeval_ms();
1004 cortex_m_set_maskints_for_run(target
);
1005 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
1007 /* Wait for pending handlers to complete or timeout */
1009 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
1011 &cortex_m
->dcb_dhcsr
);
1012 if (retval
!= ERROR_OK
) {
1013 target
->state
= TARGET_UNKNOWN
;
1016 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1017 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1019 /* only remove breakpoint if we created it */
1021 cortex_m_unset_breakpoint(target
, breakpoint
);
1023 /* Remove the temporary breakpoint */
1024 breakpoint_remove(target
, pc_value
);
1027 if (isr_timed_out
) {
1028 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1029 "leaving target running");
1031 /* Step over next instruction with interrupts disabled */
1032 cortex_m_set_maskints_for_step(target
);
1033 cortex_m_write_debug_halt_mask(target
,
1034 C_HALT
| C_MASKINTS
,
1036 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1037 /* Re-enable interrupts if appropriate */
1038 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1039 cortex_m_set_maskints_for_halt(target
);
1046 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1047 if (retval
!= ERROR_OK
)
1050 /* registers are now invalid */
1051 register_cache_invalidate(armv7m
->arm
.core_cache
);
1054 cortex_m_set_breakpoint(target
, breakpoint
);
1056 if (isr_timed_out
) {
1057 /* Leave the core running. The user has to stop execution manually. */
1058 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1059 target
->state
= TARGET_RUNNING
;
1063 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1064 " nvic_icsr = 0x%" PRIx32
,
1065 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1067 retval
= cortex_m_debug_entry(target
);
1068 if (retval
!= ERROR_OK
)
1070 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1072 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1073 " nvic_icsr = 0x%" PRIx32
,
1074 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1079 static int cortex_m_assert_reset(struct target
*target
)
1081 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1082 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1083 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1085 LOG_DEBUG("target->state: %s",
1086 target_state_name(target
));
1088 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1090 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1091 /* allow scripts to override the reset event */
1093 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1094 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1095 target
->state
= TARGET_RESET
;
1100 /* some cores support connecting while srst is asserted
1101 * use that mode is it has been configured */
1103 bool srst_asserted
= false;
1105 if (!target_was_examined(target
)) {
1106 if (jtag_reset_config
& RESET_HAS_SRST
) {
1107 adapter_assert_reset();
1108 if (target
->reset_halt
)
1109 LOG_ERROR("Target not examined, will not halt after reset!");
1112 LOG_ERROR("Target not examined, reset NOT asserted!");
1117 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1118 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1119 adapter_assert_reset();
1120 srst_asserted
= true;
1123 /* Enable debug requests */
1125 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1126 /* Store important errors instead of failing and proceed to reset assert */
1128 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1129 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1131 /* If the processor is sleeping in a WFI or WFE instruction, the
1132 * C_HALT bit must be asserted to regain control */
1133 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1134 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1136 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1137 /* Ignore less important errors */
1139 if (!target
->reset_halt
) {
1140 /* Set/Clear C_MASKINTS in a separate operation */
1141 cortex_m_set_maskints_for_run(target
);
1143 /* clear any debug flags before resuming */
1144 cortex_m_clear_halt(target
);
1146 /* clear C_HALT in dhcsr reg */
1147 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1149 /* Halt in debug on reset; endreset_event() restores DEMCR.
1151 * REVISIT catching BUSERR presumably helps to defend against
1152 * bad vector table entries. Should this include MMERR or
1156 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1157 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1158 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1159 LOG_INFO("AP write error, reset will not halt");
1162 if (jtag_reset_config
& RESET_HAS_SRST
) {
1163 /* default to asserting srst */
1165 adapter_assert_reset();
1167 /* srst is asserted, ignore AP access errors */
1170 /* Use a standard Cortex-M3 software reset mechanism.
1171 * We default to using VECRESET as it is supported on all current cores
1172 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1173 * This has the disadvantage of not resetting the peripherals, so a
1174 * reset-init event handler is needed to perform any peripheral resets.
1176 if (!cortex_m
->vectreset_supported
1177 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1178 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1179 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1180 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1183 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1184 ? "SYSRESETREQ" : "VECTRESET");
1186 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1187 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1188 "handler to reset any peripherals or configure hardware srst support.");
1192 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1193 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1194 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1195 if (retval3
!= ERROR_OK
)
1196 LOG_DEBUG("Ignoring AP write error right after reset");
1198 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1199 if (retval3
!= ERROR_OK
)
1200 LOG_ERROR("DP initialisation failed");
1203 /* I do not know why this is necessary, but it
1204 * fixes strange effects (step/resume cause NMI
1205 * after reset) on LM3S6918 -- Michael Schwingen
1208 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1212 target
->state
= TARGET_RESET
;
1215 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1217 /* now return stored error code if any */
1218 if (retval
!= ERROR_OK
)
1221 if (target
->reset_halt
) {
1222 retval
= target_halt(target
);
1223 if (retval
!= ERROR_OK
)
1230 static int cortex_m_deassert_reset(struct target
*target
)
1232 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1234 LOG_DEBUG("target->state: %s",
1235 target_state_name(target
));
1237 /* deassert reset lines */
1238 adapter_deassert_reset();
1240 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1242 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1243 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1244 target_was_examined(target
)) {
1245 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1246 if (retval
!= ERROR_OK
) {
1247 LOG_ERROR("DP initialisation failed");
1255 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1259 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1260 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1262 if (breakpoint
->set
) {
1263 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1267 if (breakpoint
->type
== BKPT_HARD
) {
1268 uint32_t fpcr_value
;
1269 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1271 if (fp_num
>= cortex_m
->fp_num_code
) {
1272 LOG_ERROR("Can not find free FPB Comparator!");
1273 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1275 breakpoint
->set
= fp_num
+ 1;
1276 fpcr_value
= breakpoint
->address
| 1;
1277 if (cortex_m
->fp_rev
== 0) {
1278 if (breakpoint
->address
> 0x1FFFFFFF) {
1279 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1283 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1284 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1285 } else if (cortex_m
->fp_rev
> 1) {
1286 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1289 comparator_list
[fp_num
].used
= true;
1290 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1291 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1292 comparator_list
[fp_num
].fpcr_value
);
1293 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1295 comparator_list
[fp_num
].fpcr_value
);
1296 if (!cortex_m
->fpb_enabled
) {
1297 LOG_DEBUG("FPB wasn't enabled, do it now");
1298 retval
= cortex_m_enable_fpb(target
);
1299 if (retval
!= ERROR_OK
) {
1300 LOG_ERROR("Failed to enable the FPB");
1304 cortex_m
->fpb_enabled
= true;
1306 } else if (breakpoint
->type
== BKPT_SOFT
) {
1309 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1310 * semihosting; don't use that. Otherwise the BKPT
1311 * parameter is arbitrary.
1313 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1314 retval
= target_read_memory(target
,
1315 breakpoint
->address
& 0xFFFFFFFE,
1316 breakpoint
->length
, 1,
1317 breakpoint
->orig_instr
);
1318 if (retval
!= ERROR_OK
)
1320 retval
= target_write_memory(target
,
1321 breakpoint
->address
& 0xFFFFFFFE,
1322 breakpoint
->length
, 1,
1324 if (retval
!= ERROR_OK
)
1326 breakpoint
->set
= true;
1329 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1330 breakpoint
->unique_id
,
1331 (int)(breakpoint
->type
),
1332 breakpoint
->address
,
1339 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1342 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1343 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1345 if (!breakpoint
->set
) {
1346 LOG_WARNING("breakpoint not set");
1350 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1351 breakpoint
->unique_id
,
1352 (int)(breakpoint
->type
),
1353 breakpoint
->address
,
1357 if (breakpoint
->type
== BKPT_HARD
) {
1358 int fp_num
= breakpoint
->set
- 1;
1359 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1360 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1363 comparator_list
[fp_num
].used
= false;
1364 comparator_list
[fp_num
].fpcr_value
= 0;
1365 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1366 comparator_list
[fp_num
].fpcr_value
);
1368 /* restore original instruction (kept in target endianness) */
1369 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1370 breakpoint
->length
, 1,
1371 breakpoint
->orig_instr
);
1372 if (retval
!= ERROR_OK
)
1375 breakpoint
->set
= false;
1380 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1382 if (breakpoint
->length
== 3) {
1383 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1384 breakpoint
->length
= 2;
1387 if ((breakpoint
->length
!= 2)) {
1388 LOG_INFO("only breakpoints of two bytes length supported");
1389 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1392 return cortex_m_set_breakpoint(target
, breakpoint
);
1395 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1397 if (!breakpoint
->set
)
1400 return cortex_m_unset_breakpoint(target
, breakpoint
);
1403 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1406 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1408 /* REVISIT Don't fully trust these "not used" records ... users
1409 * may set up breakpoints by hand, e.g. dual-address data value
1410 * watchpoint using comparator #1; comparator #0 matching cycle
1411 * count; send data trace info through ITM and TPIU; etc
1413 struct cortex_m_dwt_comparator
*comparator
;
1415 for (comparator
= cortex_m
->dwt_comparator_list
;
1416 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1417 comparator
++, dwt_num
++)
1419 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1420 LOG_ERROR("Can not find free DWT Comparator");
1423 comparator
->used
= true;
1424 watchpoint
->set
= dwt_num
+ 1;
1426 comparator
->comp
= watchpoint
->address
;
1427 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1430 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1431 uint32_t mask
= 0, temp
;
1433 /* watchpoint params were validated earlier */
1434 temp
= watchpoint
->length
;
1441 comparator
->mask
= mask
;
1442 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1445 switch (watchpoint
->rw
) {
1447 comparator
->function
= 5;
1450 comparator
->function
= 6;
1453 comparator
->function
= 7;
1457 uint32_t data_size
= watchpoint
->length
>> 1;
1458 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1460 switch (watchpoint
->rw
) {
1462 comparator
->function
= 4;
1465 comparator
->function
= 5;
1468 comparator
->function
= 6;
1471 comparator
->function
= comparator
->function
| (1 << 4) |
1475 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1476 comparator
->function
);
1478 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1479 watchpoint
->unique_id
, dwt_num
,
1480 (unsigned) comparator
->comp
,
1481 (unsigned) comparator
->mask
,
1482 (unsigned) comparator
->function
);
1486 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1488 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1489 struct cortex_m_dwt_comparator
*comparator
;
1492 if (!watchpoint
->set
) {
1493 LOG_WARNING("watchpoint (wpid: %d) not set",
1494 watchpoint
->unique_id
);
1498 dwt_num
= watchpoint
->set
- 1;
1500 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1501 watchpoint
->unique_id
, dwt_num
,
1502 (unsigned) watchpoint
->address
);
1504 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1505 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1509 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1510 comparator
->used
= false;
1511 comparator
->function
= 0;
1512 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1513 comparator
->function
);
1515 watchpoint
->set
= false;
1520 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1522 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1524 if (cortex_m
->dwt_comp_available
< 1) {
1525 LOG_DEBUG("no comparators?");
1526 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1529 /* hardware doesn't support data value masking */
1530 if (watchpoint
->mask
!= ~(uint32_t)0) {
1531 LOG_DEBUG("watchpoint value masks not supported");
1532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1535 /* hardware allows address masks of up to 32K */
1538 for (mask
= 0; mask
< 16; mask
++) {
1539 if ((1u << mask
) == watchpoint
->length
)
1543 LOG_DEBUG("unsupported watchpoint length");
1544 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1546 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1547 LOG_DEBUG("watchpoint address is unaligned");
1548 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1551 /* Caller doesn't seem to be able to describe watching for data
1552 * values of zero; that flags "no value".
1554 * REVISIT This DWT may well be able to watch for specific data
1555 * values. Requires comparator #1 to set DATAVMATCH and match
1556 * the data, and another comparator (DATAVADDR0) matching addr.
1558 if (watchpoint
->value
) {
1559 LOG_DEBUG("data value watchpoint not YET supported");
1560 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1563 cortex_m
->dwt_comp_available
--;
1564 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1569 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1571 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1573 /* REVISIT why check? DWT can be updated with core running ... */
1574 if (target
->state
!= TARGET_HALTED
) {
1575 LOG_WARNING("target not halted");
1576 return ERROR_TARGET_NOT_HALTED
;
1579 if (watchpoint
->set
)
1580 cortex_m_unset_watchpoint(target
, watchpoint
);
1582 cortex_m
->dwt_comp_available
++;
1583 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1588 void cortex_m_enable_watchpoints(struct target
*target
)
1590 struct watchpoint
*watchpoint
= target
->watchpoints
;
1592 /* set any pending watchpoints */
1593 while (watchpoint
) {
1594 if (!watchpoint
->set
)
1595 cortex_m_set_watchpoint(target
, watchpoint
);
1596 watchpoint
= watchpoint
->next
;
1600 static int cortex_m_load_core_reg_u32(struct target
*target
,
1601 uint32_t num
, uint32_t *value
)
1605 /* NOTE: we "know" here that the register identifiers used
1606 * in the v7m header match the Cortex-M3 Debug Core Register
1607 * Selector values for R0..R15, xPSR, MSP, and PSP.
1611 /* read a normal core register */
1612 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1614 if (retval
!= ERROR_OK
) {
1615 LOG_ERROR("JTAG failure %i", retval
);
1616 return ERROR_JTAG_DEVICE_ERROR
;
1618 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1622 /* Floating-point Status and Registers */
1623 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1624 if (retval
!= ERROR_OK
)
1626 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1627 if (retval
!= ERROR_OK
)
1629 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1632 case ARMV7M_S0
... ARMV7M_S31
:
1633 /* Floating-point Status and Registers */
1634 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1635 if (retval
!= ERROR_OK
)
1637 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1638 if (retval
!= ERROR_OK
)
1640 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1641 (int)(num
- ARMV7M_S0
), *value
);
1644 case ARMV7M_PRIMASK
:
1645 case ARMV7M_BASEPRI
:
1646 case ARMV7M_FAULTMASK
:
1647 case ARMV7M_CONTROL
:
1648 /* Cortex-M3 packages these four registers as bitfields
1649 * in one Debug Core register. So say r0 and r2 docs;
1650 * it was removed from r1 docs, but still works.
1652 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1655 case ARMV7M_PRIMASK
:
1656 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1659 case ARMV7M_BASEPRI
:
1660 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1663 case ARMV7M_FAULTMASK
:
1664 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1667 case ARMV7M_CONTROL
:
1668 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1672 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1676 return ERROR_COMMAND_SYNTAX_ERROR
;
1682 static int cortex_m_store_core_reg_u32(struct target
*target
,
1683 uint32_t num
, uint32_t value
)
1687 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1689 /* NOTE: we "know" here that the register identifiers used
1690 * in the v7m header match the Cortex-M3 Debug Core Register
1691 * Selector values for R0..R15, xPSR, MSP, and PSP.
1695 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1696 if (retval
!= ERROR_OK
) {
1699 LOG_ERROR("JTAG failure");
1700 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1701 r
->dirty
= r
->valid
;
1702 return ERROR_JTAG_DEVICE_ERROR
;
1704 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1708 /* Floating-point Status and Registers */
1709 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1710 if (retval
!= ERROR_OK
)
1712 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1713 if (retval
!= ERROR_OK
)
1715 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1718 case ARMV7M_S0
... ARMV7M_S31
:
1719 /* Floating-point Status and Registers */
1720 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1721 if (retval
!= ERROR_OK
)
1723 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1724 if (retval
!= ERROR_OK
)
1726 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1727 (int)(num
- ARMV7M_S0
), value
);
1730 case ARMV7M_PRIMASK
:
1731 case ARMV7M_BASEPRI
:
1732 case ARMV7M_FAULTMASK
:
1733 case ARMV7M_CONTROL
:
1734 /* Cortex-M3 packages these four registers as bitfields
1735 * in one Debug Core register. So say r0 and r2 docs;
1736 * it was removed from r1 docs, but still works.
1738 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1741 case ARMV7M_PRIMASK
:
1742 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1745 case ARMV7M_BASEPRI
:
1746 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1749 case ARMV7M_FAULTMASK
:
1750 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1753 case ARMV7M_CONTROL
:
1754 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1758 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1760 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1764 return ERROR_COMMAND_SYNTAX_ERROR
;
1770 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1771 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1773 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1775 if (armv7m
->arm
.is_armv6m
) {
1776 /* armv6m does not handle unaligned memory access */
1777 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1778 return ERROR_TARGET_UNALIGNED_ACCESS
;
1781 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1784 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1785 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1787 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1789 if (armv7m
->arm
.is_armv6m
) {
1790 /* armv6m does not handle unaligned memory access */
1791 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1792 return ERROR_TARGET_UNALIGNED_ACCESS
;
1795 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1798 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1799 struct target
*target
)
1801 armv7m_build_reg_cache(target
);
1802 arm_semihosting_init(target
);
1806 void cortex_m_deinit_target(struct target
*target
)
1808 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1810 free(cortex_m
->fp_comparator_list
);
1812 cortex_m_dwt_free(target
);
1813 armv7m_free_reg_cache(target
);
1815 free(target
->private_config
);
1819 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1820 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1822 struct timeval timeout
, now
;
1823 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1825 bool use_pcsr
= false;
1826 int retval
= ERROR_OK
;
1829 gettimeofday(&timeout
, NULL
);
1830 timeval_add_time(&timeout
, seconds
, 0);
1832 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1833 if (retval
!= ERROR_OK
) {
1834 LOG_ERROR("Error while reading PCSR");
1838 if (reg_value
!= 0) {
1840 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1842 LOG_INFO("Starting profiling. Halting and resuming the"
1843 " target as often as we can...");
1844 reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1847 /* Make sure the target is running */
1848 target_poll(target
);
1849 if (target
->state
== TARGET_HALTED
)
1850 retval
= target_resume(target
, 1, 0, 0, 0);
1852 if (retval
!= ERROR_OK
) {
1853 LOG_ERROR("Error while resuming target");
1857 uint32_t sample_count
= 0;
1861 if (armv7m
&& armv7m
->debug_ap
) {
1862 uint32_t read_count
= max_num_samples
- sample_count
;
1863 if (read_count
> 1024)
1866 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1867 (void *)&samples
[sample_count
],
1868 4, read_count
, DWT_PCSR
);
1869 sample_count
+= read_count
;
1871 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1874 target_poll(target
);
1875 if (target
->state
== TARGET_HALTED
) {
1876 reg_value
= buf_get_u32(reg
->value
, 0, 32);
1877 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1878 retval
= target_resume(target
, 1, 0, 0, 0);
1879 samples
[sample_count
++] = reg_value
;
1880 target_poll(target
);
1881 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1882 } else if (target
->state
== TARGET_RUNNING
) {
1883 /* We want to quickly sample the PC. */
1884 retval
= target_halt(target
);
1886 LOG_INFO("Target not halted or running");
1892 if (retval
!= ERROR_OK
) {
1893 LOG_ERROR("Error while reading %s", use_pcsr
? "PCSR" : "target pc");
1898 gettimeofday(&now
, NULL
);
1899 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1900 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1905 *num_samples
= sample_count
;
1910 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1911 * on r/w if the core is not running, and clear on resume or reset ... or
1912 * at least, in a post_restore_context() method.
1915 struct dwt_reg_state
{
1916 struct target
*target
;
1918 uint8_t value
[4]; /* scratch/cache */
1921 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1923 struct dwt_reg_state
*state
= reg
->arch_info
;
1926 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1927 if (retval
!= ERROR_OK
)
1930 buf_set_u32(state
->value
, 0, 32, tmp
);
1934 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1936 struct dwt_reg_state
*state
= reg
->arch_info
;
1938 return target_write_u32(state
->target
, state
->addr
,
1939 buf_get_u32(buf
, 0, reg
->size
));
1948 static const struct dwt_reg dwt_base_regs
[] = {
1949 { DWT_CTRL
, "dwt_ctrl", 32, },
1950 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1951 * increments while the core is asleep.
1953 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1954 /* plus some 8 bit counters, useful for profiling with TPIU */
1957 static const struct dwt_reg dwt_comp
[] = {
1958 #define DWT_COMPARATOR(i) \
1959 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1960 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1961 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1978 #undef DWT_COMPARATOR
1981 static const struct reg_arch_type dwt_reg_type
= {
1982 .get
= cortex_m_dwt_get_reg
,
1983 .set
= cortex_m_dwt_set_reg
,
1986 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1988 struct dwt_reg_state
*state
;
1990 state
= calloc(1, sizeof(*state
));
1993 state
->addr
= d
->addr
;
1998 r
->value
= state
->value
;
1999 r
->arch_info
= state
;
2000 r
->type
= &dwt_reg_type
;
2003 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
2006 struct reg_cache
*cache
;
2007 struct cortex_m_dwt_comparator
*comparator
;
2010 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
2011 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2013 LOG_DEBUG("no DWT");
2017 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2018 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2020 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2021 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2022 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2023 sizeof(struct cortex_m_dwt_comparator
));
2024 if (!cm
->dwt_comparator_list
) {
2026 cm
->dwt_num_comp
= 0;
2027 LOG_ERROR("out of mem");
2031 cache
= calloc(1, sizeof(*cache
));
2034 free(cm
->dwt_comparator_list
);
2037 cache
->name
= "Cortex-M DWT registers";
2038 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2039 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
2040 if (!cache
->reg_list
) {
2045 for (reg
= 0; reg
< 2; reg
++)
2046 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2047 dwt_base_regs
+ reg
);
2049 comparator
= cm
->dwt_comparator_list
;
2050 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2053 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2054 for (j
= 0; j
< 3; j
++, reg
++)
2055 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2056 dwt_comp
+ 3 * i
+ j
);
2058 /* make sure we clear any watchpoints enabled on the target */
2059 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2062 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2063 cm
->dwt_cache
= cache
;
2065 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2066 dwtcr
, cm
->dwt_num_comp
,
2067 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2069 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2070 * implement single-address data value watchpoints ... so we
2071 * won't need to check it later, when asked to set one up.
2075 static void cortex_m_dwt_free(struct target
*target
)
2077 struct cortex_m_common
*cm
= target_to_cm(target
);
2078 struct reg_cache
*cache
= cm
->dwt_cache
;
2080 free(cm
->dwt_comparator_list
);
2081 cm
->dwt_comparator_list
= NULL
;
2082 cm
->dwt_num_comp
= 0;
2085 register_unlink_cache(&target
->reg_cache
, cache
);
2087 if (cache
->reg_list
) {
2088 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2089 free(cache
->reg_list
[i
].arch_info
);
2090 free(cache
->reg_list
);
2094 cm
->dwt_cache
= NULL
;
2097 #define MVFR0 0xe000ef40
2098 #define MVFR1 0xe000ef44
2100 #define MVFR0_DEFAULT_M4 0x10110021
2101 #define MVFR1_DEFAULT_M4 0x11000011
2103 #define MVFR0_DEFAULT_M7_SP 0x10110021
2104 #define MVFR0_DEFAULT_M7_DP 0x10110221
2105 #define MVFR1_DEFAULT_M7_SP 0x11000011
2106 #define MVFR1_DEFAULT_M7_DP 0x12000011
2108 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
2109 struct adiv5_ap
**debug_ap
)
2111 if (dap_find_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
2114 return dap_find_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
2117 int cortex_m_examine(struct target
*target
)
2120 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2122 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2123 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2124 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2126 /* stlink shares the examine handler but does not support
2128 if (!armv7m
->stlink
) {
2129 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2130 /* Search for the MEM-AP */
2131 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
2132 if (retval
!= ERROR_OK
) {
2133 LOG_ERROR("Could not find MEM-AP to control the core");
2137 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
2140 /* Leave (only) generic DAP stuff for debugport_init(); */
2141 armv7m
->debug_ap
->memaccess_tck
= 8;
2143 retval
= mem_ap_init(armv7m
->debug_ap
);
2144 if (retval
!= ERROR_OK
)
2148 if (!target_was_examined(target
)) {
2149 target_set_examined(target
);
2151 /* Read from Device Identification Registers */
2152 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2153 if (retval
!= ERROR_OK
)
2157 i
= (cpuid
>> 4) & 0xf;
2159 switch (cpuid
& ARM_CPUID_PARTNO_MASK
) {
2160 case CORTEX_M23_PARTNO
:
2164 case CORTEX_M33_PARTNO
:
2173 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2174 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2175 cortex_m
->maskints_erratum
= false;
2178 rev
= (cpuid
>> 20) & 0xf;
2179 patch
= (cpuid
>> 0) & 0xf;
2180 if ((rev
== 0) && (patch
< 2)) {
2181 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2182 cortex_m
->maskints_erratum
= true;
2185 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2187 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2188 cortex_m
->vectreset_supported
= i
> 1;
2191 target_read_u32(target
, MVFR0
, &mvfr0
);
2192 target_read_u32(target
, MVFR1
, &mvfr1
);
2194 /* test for floating point feature on Cortex-M4 */
2195 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2196 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2197 armv7m
->fp_feature
= FPv4_SP
;
2199 } else if (i
== 7 || i
== 33) {
2200 target_read_u32(target
, MVFR0
, &mvfr0
);
2201 target_read_u32(target
, MVFR1
, &mvfr1
);
2203 /* test for floating point features on Cortex-M7 */
2204 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2205 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2206 armv7m
->fp_feature
= FPv5_SP
;
2207 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2208 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2209 armv7m
->fp_feature
= FPv5_DP
;
2211 } else if (i
== 0) {
2212 /* Cortex-M0 does not support unaligned memory access */
2213 armv7m
->arm
.is_armv6m
= true;
2216 if (armv7m
->fp_feature
== FP_NONE
&&
2217 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2218 /* free unavailable FPU registers */
2221 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2222 idx
< armv7m
->arm
.core_cache
->num_regs
;
2224 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
2225 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2226 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2228 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2231 if (!armv7m
->stlink
) {
2232 if (i
== 3 || i
== 4)
2233 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2234 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2235 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2237 /* Cortex-M7 has only 1024 bytes autoincrement range */
2238 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2241 /* Enable debug requests */
2242 retval
= target_read_u32(target
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
2243 if (retval
!= ERROR_OK
)
2245 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
2246 uint32_t dhcsr
= (cortex_m
->dcb_dhcsr
| C_DEBUGEN
) & ~(C_HALT
| C_STEP
| C_MASKINTS
);
2248 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| (dhcsr
& 0x0000FFFFUL
));
2249 if (retval
!= ERROR_OK
)
2251 cortex_m
->dcb_dhcsr
= dhcsr
;
2254 /* Configure trace modules */
2255 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2256 if (retval
!= ERROR_OK
)
2259 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2260 armv7m_trace_tpiu_config(target
);
2261 armv7m_trace_itm_config(target
);
2264 /* NOTE: FPB and DWT are both optional. */
2267 target_read_u32(target
, FP_CTRL
, &fpcr
);
2268 /* bits [14:12] and [7:4] */
2269 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2270 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2271 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2272 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2273 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2274 free(cortex_m
->fp_comparator_list
);
2275 cortex_m
->fp_comparator_list
= calloc(
2276 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2277 sizeof(struct cortex_m_fp_comparator
));
2278 cortex_m
->fpb_enabled
= fpcr
& 1;
2279 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2280 cortex_m
->fp_comparator_list
[i
].type
=
2281 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2282 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2284 /* make sure we clear any breakpoints enabled on the target */
2285 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2287 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2289 cortex_m
->fp_num_code
,
2290 cortex_m
->fp_num_lit
);
2293 cortex_m_dwt_free(target
);
2294 cortex_m_dwt_setup(cortex_m
, target
);
2296 /* These hardware breakpoints only work for code in flash! */
2297 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2298 target_name(target
),
2299 cortex_m
->fp_num_code
,
2300 cortex_m
->dwt_num_comp
);
2306 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2308 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2313 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2314 if (retval
!= ERROR_OK
)
2317 dcrdr
= target_buffer_get_u16(target
, buf
);
2318 *ctrl
= (uint8_t)dcrdr
;
2319 *value
= (uint8_t)(dcrdr
>> 8);
2321 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2323 /* write ack back to software dcc register
2324 * signify we have read data */
2325 if (dcrdr
& (1 << 0)) {
2326 target_buffer_set_u16(target
, buf
, 0);
2327 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2328 if (retval
!= ERROR_OK
)
2335 static int cortex_m_target_request_data(struct target
*target
,
2336 uint32_t size
, uint8_t *buffer
)
2342 for (i
= 0; i
< (size
* 4); i
++) {
2343 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2344 if (retval
!= ERROR_OK
)
2352 static int cortex_m_handle_target_request(void *priv
)
2354 struct target
*target
= priv
;
2355 if (!target_was_examined(target
))
2358 if (!target
->dbg_msg_enabled
)
2361 if (target
->state
== TARGET_RUNNING
) {
2366 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2367 if (retval
!= ERROR_OK
)
2370 /* check if we have data */
2371 if (ctrl
& (1 << 0)) {
2374 /* we assume target is quick enough */
2376 for (int i
= 1; i
<= 3; i
++) {
2377 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2378 if (retval
!= ERROR_OK
)
2380 request
|= ((uint32_t)data
<< (i
* 8));
2382 target_request(target
, request
);
2389 static int cortex_m_init_arch_info(struct target
*target
,
2390 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2392 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2394 armv7m_init_arch_info(target
, armv7m
);
2396 /* default reset mode is to use srst if fitted
2397 * if not it will use CORTEX_M3_RESET_VECTRESET */
2398 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2400 armv7m
->arm
.dap
= dap
;
2402 /* register arch-specific functions */
2403 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2405 armv7m
->post_debug_entry
= NULL
;
2407 armv7m
->pre_restore_context
= NULL
;
2409 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2410 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2412 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2413 TARGET_TIMER_TYPE_PERIODIC
, target
);
2418 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2420 struct adiv5_private_config
*pc
;
2422 pc
= (struct adiv5_private_config
*)target
->private_config
;
2423 if (adiv5_verify_config(pc
) != ERROR_OK
)
2426 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2427 if (cortex_m
== NULL
) {
2428 LOG_ERROR("No memory creating target");
2432 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2433 cortex_m
->apsel
= pc
->ap_num
;
2435 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2440 /*--------------------------------------------------------------------------*/
2442 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2443 struct cortex_m_common
*cm
)
2445 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2446 command_print(cmd
, "target is not a Cortex-M");
2447 return ERROR_TARGET_INVALID
;
2453 * Only stuff below this line should need to verify that its target
2454 * is a Cortex-M3. Everything else should have indirected through the
2455 * cortexm3_target structure, which is only used with CM3 targets.
2458 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2460 struct target
*target
= get_current_target(CMD_CTX
);
2461 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2462 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2466 static const struct {
2470 { "hard_err", VC_HARDERR
, },
2471 { "int_err", VC_INTERR
, },
2472 { "bus_err", VC_BUSERR
, },
2473 { "state_err", VC_STATERR
, },
2474 { "chk_err", VC_CHKERR
, },
2475 { "nocp_err", VC_NOCPERR
, },
2476 { "mm_err", VC_MMERR
, },
2477 { "reset", VC_CORERESET
, },
2480 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2481 if (retval
!= ERROR_OK
)
2484 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2485 if (retval
!= ERROR_OK
)
2491 if (CMD_ARGC
== 1) {
2492 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2493 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2494 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2495 | VC_MMERR
| VC_CORERESET
;
2497 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2500 while (CMD_ARGC
-- > 0) {
2502 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2503 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2505 catch |= vec_ids
[i
].mask
;
2508 if (i
== ARRAY_SIZE(vec_ids
)) {
2509 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2510 return ERROR_COMMAND_SYNTAX_ERROR
;
2514 /* For now, armv7m->demcr only stores vector catch flags. */
2515 armv7m
->demcr
= catch;
2520 /* write, but don't assume it stuck (why not??) */
2521 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2522 if (retval
!= ERROR_OK
)
2524 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2525 if (retval
!= ERROR_OK
)
2528 /* FIXME be sure to clear DEMCR on clean server shutdown.
2529 * Otherwise the vector catch hardware could fire when there's
2530 * no debugger hooked up, causing much confusion...
2534 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2535 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2536 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2542 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2544 struct target
*target
= get_current_target(CMD_CTX
);
2545 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2548 static const Jim_Nvp nvp_maskisr_modes
[] = {
2549 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2550 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2551 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2552 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2553 { .name
= NULL
, .value
= -1 },
2558 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2559 if (retval
!= ERROR_OK
)
2562 if (target
->state
!= TARGET_HALTED
) {
2563 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
2568 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2569 if (n
->name
== NULL
)
2570 return ERROR_COMMAND_SYNTAX_ERROR
;
2571 cortex_m
->isrmasking_mode
= n
->value
;
2572 cortex_m_set_maskints_for_halt(target
);
2575 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2576 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2581 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2583 struct target
*target
= get_current_target(CMD_CTX
);
2584 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2588 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2589 if (retval
!= ERROR_OK
)
2593 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2594 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2596 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2597 if (target_was_examined(target
)
2598 && !cortex_m
->vectreset_supported
)
2599 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2601 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2604 return ERROR_COMMAND_SYNTAX_ERROR
;
2607 switch (cortex_m
->soft_reset_config
) {
2608 case CORTEX_M_RESET_SYSRESETREQ
:
2609 reset_config
= "sysresetreq";
2612 case CORTEX_M_RESET_VECTRESET
:
2613 reset_config
= "vectreset";
2617 reset_config
= "unknown";
2621 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
2626 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2629 .handler
= handle_cortex_m_mask_interrupts_command
,
2630 .mode
= COMMAND_EXEC
,
2631 .help
= "mask cortex_m interrupts",
2632 .usage
= "['auto'|'on'|'off'|'steponly']",
2635 .name
= "vector_catch",
2636 .handler
= handle_cortex_m_vector_catch_command
,
2637 .mode
= COMMAND_EXEC
,
2638 .help
= "configure hardware vectors to trigger debug entry",
2639 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2642 .name
= "reset_config",
2643 .handler
= handle_cortex_m_reset_config_command
,
2644 .mode
= COMMAND_ANY
,
2645 .help
= "configure software reset handling",
2646 .usage
= "['sysresetreq'|'vectreset']",
2648 COMMAND_REGISTRATION_DONE
2650 static const struct command_registration cortex_m_command_handlers
[] = {
2652 .chain
= armv7m_command_handlers
,
2655 .chain
= armv7m_trace_command_handlers
,
2659 .mode
= COMMAND_EXEC
,
2660 .help
= "Cortex-M command group",
2662 .chain
= cortex_m_exec_command_handlers
,
2664 COMMAND_REGISTRATION_DONE
2667 struct target_type cortexm_target
= {
2669 .deprecated_name
= "cortex_m3",
2671 .poll
= cortex_m_poll
,
2672 .arch_state
= armv7m_arch_state
,
2674 .target_request_data
= cortex_m_target_request_data
,
2676 .halt
= cortex_m_halt
,
2677 .resume
= cortex_m_resume
,
2678 .step
= cortex_m_step
,
2680 .assert_reset
= cortex_m_assert_reset
,
2681 .deassert_reset
= cortex_m_deassert_reset
,
2682 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2684 .get_gdb_arch
= arm_get_gdb_arch
,
2685 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2687 .read_memory
= cortex_m_read_memory
,
2688 .write_memory
= cortex_m_write_memory
,
2689 .checksum_memory
= armv7m_checksum_memory
,
2690 .blank_check_memory
= armv7m_blank_check_memory
,
2692 .run_algorithm
= armv7m_run_algorithm
,
2693 .start_algorithm
= armv7m_start_algorithm
,
2694 .wait_algorithm
= armv7m_wait_algorithm
,
2696 .add_breakpoint
= cortex_m_add_breakpoint
,
2697 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2698 .add_watchpoint
= cortex_m_add_watchpoint
,
2699 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2701 .commands
= cortex_m_command_handlers
,
2702 .target_create
= cortex_m_target_create
,
2703 .target_jim_configure
= adiv5_jim_configure
,
2704 .init_target
= cortex_m_init_target
,
2705 .examine
= cortex_m_examine
,
2706 .deinit_target
= cortex_m_deinit_target
,
2708 .profiling
= cortex_m_profiling
,
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