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helper/jim-nvp: comply with coding style [2/2]
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42 #include <rtt/rtt.h>
43
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FPB remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
49 *
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
52 * any longer.
53 */
54
55 /* forward declarations */
56 static int cortex_m_store_core_reg_u32(struct target *target,
57 uint32_t num, uint32_t value);
58 static void cortex_m_dwt_free(struct target *target);
59
60 static int cortex_m_load_core_reg_u32(struct target *target,
61 uint32_t regsel, uint32_t *value)
62 {
63 struct armv7m_common *armv7m = target_to_armv7m(target);
64 int retval;
65 uint32_t dcrdr;
66
67 /* because the DCB_DCRDR is used for the emulated dcc channel
68 * we have to save/restore the DCB_DCRDR when used */
69 if (target->dbg_msg_enabled) {
70 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
71 if (retval != ERROR_OK)
72 return retval;
73 }
74
75 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
76 if (retval != ERROR_OK)
77 return retval;
78
79 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
80 if (retval != ERROR_OK)
81 return retval;
82
83 if (target->dbg_msg_enabled) {
84 /* restore DCB_DCRDR - this needs to be in a separate
85 * transaction otherwise the emulated DCC channel breaks */
86 if (retval == ERROR_OK)
87 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
88 }
89
90 return retval;
91 }
92
93 static int cortex_m_store_core_reg_u32(struct target *target,
94 uint32_t regsel, uint32_t value)
95 {
96 struct armv7m_common *armv7m = target_to_armv7m(target);
97 int retval;
98 uint32_t dcrdr;
99
100 /* because the DCB_DCRDR is used for the emulated dcc channel
101 * we have to save/restore the DCB_DCRDR when used */
102 if (target->dbg_msg_enabled) {
103 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
104 if (retval != ERROR_OK)
105 return retval;
106 }
107
108 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
109 if (retval != ERROR_OK)
110 return retval;
111
112 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
113 if (retval != ERROR_OK)
114 return retval;
115
116 if (target->dbg_msg_enabled) {
117 /* restore DCB_DCRDR - this needs to be in a separate
118 * transaction otherwise the emulated DCC channel breaks */
119 if (retval == ERROR_OK)
120 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
121 }
122
123 return retval;
124 }
125
126 static int cortex_m_write_debug_halt_mask(struct target *target,
127 uint32_t mask_on, uint32_t mask_off)
128 {
129 struct cortex_m_common *cortex_m = target_to_cm(target);
130 struct armv7m_common *armv7m = &cortex_m->armv7m;
131
132 /* mask off status bits */
133 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
134 /* create new register mask */
135 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
136
137 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
138 }
139
140 static int cortex_m_set_maskints(struct target *target, bool mask)
141 {
142 struct cortex_m_common *cortex_m = target_to_cm(target);
143 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
144 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
145 else
146 return ERROR_OK;
147 }
148
149 static int cortex_m_set_maskints_for_halt(struct target *target)
150 {
151 struct cortex_m_common *cortex_m = target_to_cm(target);
152 switch (cortex_m->isrmasking_mode) {
153 case CORTEX_M_ISRMASK_AUTO:
154 /* interrupts taken at resume, whether for step or run -> no mask */
155 return cortex_m_set_maskints(target, false);
156
157 case CORTEX_M_ISRMASK_OFF:
158 /* interrupts never masked */
159 return cortex_m_set_maskints(target, false);
160
161 case CORTEX_M_ISRMASK_ON:
162 /* interrupts always masked */
163 return cortex_m_set_maskints(target, true);
164
165 case CORTEX_M_ISRMASK_STEPONLY:
166 /* interrupts masked for single step only -> mask now if MASKINTS
167 * erratum, otherwise only mask before stepping */
168 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
169 }
170 return ERROR_OK;
171 }
172
173 static int cortex_m_set_maskints_for_run(struct target *target)
174 {
175 switch (target_to_cm(target)->isrmasking_mode) {
176 case CORTEX_M_ISRMASK_AUTO:
177 /* interrupts taken at resume, whether for step or run -> no mask */
178 return cortex_m_set_maskints(target, false);
179
180 case CORTEX_M_ISRMASK_OFF:
181 /* interrupts never masked */
182 return cortex_m_set_maskints(target, false);
183
184 case CORTEX_M_ISRMASK_ON:
185 /* interrupts always masked */
186 return cortex_m_set_maskints(target, true);
187
188 case CORTEX_M_ISRMASK_STEPONLY:
189 /* interrupts masked for single step only -> no mask */
190 return cortex_m_set_maskints(target, false);
191 }
192 return ERROR_OK;
193 }
194
195 static int cortex_m_set_maskints_for_step(struct target *target)
196 {
197 switch (target_to_cm(target)->isrmasking_mode) {
198 case CORTEX_M_ISRMASK_AUTO:
199 /* the auto-interrupt should already be done -> mask */
200 return cortex_m_set_maskints(target, true);
201
202 case CORTEX_M_ISRMASK_OFF:
203 /* interrupts never masked */
204 return cortex_m_set_maskints(target, false);
205
206 case CORTEX_M_ISRMASK_ON:
207 /* interrupts always masked */
208 return cortex_m_set_maskints(target, true);
209
210 case CORTEX_M_ISRMASK_STEPONLY:
211 /* interrupts masked for single step only -> mask */
212 return cortex_m_set_maskints(target, true);
213 }
214 return ERROR_OK;
215 }
216
217 static int cortex_m_clear_halt(struct target *target)
218 {
219 struct cortex_m_common *cortex_m = target_to_cm(target);
220 struct armv7m_common *armv7m = &cortex_m->armv7m;
221 int retval;
222
223 /* clear step if any */
224 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
225
226 /* Read Debug Fault Status Register */
227 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
228 if (retval != ERROR_OK)
229 return retval;
230
231 /* Clear Debug Fault Status */
232 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
233 if (retval != ERROR_OK)
234 return retval;
235 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
236
237 return ERROR_OK;
238 }
239
240 static int cortex_m_single_step_core(struct target *target)
241 {
242 struct cortex_m_common *cortex_m = target_to_cm(target);
243 struct armv7m_common *armv7m = &cortex_m->armv7m;
244 int retval;
245
246 /* Mask interrupts before clearing halt, if not done already. This avoids
247 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
248 * HALT can put the core into an unknown state.
249 */
250 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
251 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
252 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
253 if (retval != ERROR_OK)
254 return retval;
255 }
256 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
257 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
258 if (retval != ERROR_OK)
259 return retval;
260 LOG_DEBUG(" ");
261
262 /* restore dhcsr reg */
263 cortex_m_clear_halt(target);
264
265 return ERROR_OK;
266 }
267
268 static int cortex_m_enable_fpb(struct target *target)
269 {
270 int retval = target_write_u32(target, FP_CTRL, 3);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* check the fpb is actually enabled */
275 uint32_t fpctrl;
276 retval = target_read_u32(target, FP_CTRL, &fpctrl);
277 if (retval != ERROR_OK)
278 return retval;
279
280 if (fpctrl & 1)
281 return ERROR_OK;
282
283 return ERROR_FAIL;
284 }
285
286 static int cortex_m_endreset_event(struct target *target)
287 {
288 int retval;
289 uint32_t dcb_demcr;
290 struct cortex_m_common *cortex_m = target_to_cm(target);
291 struct armv7m_common *armv7m = &cortex_m->armv7m;
292 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
293 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
294 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
295
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
298 if (retval != ERROR_OK)
299 return retval;
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
301
302 /* this register is used for emulated dcc channel */
303 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
304 if (retval != ERROR_OK)
305 return retval;
306
307 /* Enable debug requests */
308 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
309 if (retval != ERROR_OK)
310 return retval;
311 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
312 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
313 if (retval != ERROR_OK)
314 return retval;
315 }
316
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target);
319
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
322 *
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
326 */
327 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
328 if (retval != ERROR_OK)
329 return retval;
330
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
333 */
334
335 /* Enable FPB */
336 retval = cortex_m_enable_fpb(target);
337 if (retval != ERROR_OK) {
338 LOG_ERROR("Failed to enable the FPB");
339 return retval;
340 }
341
342 cortex_m->fpb_enabled = true;
343
344 /* Restore FPB registers */
345 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
346 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350
351 /* Restore DWT registers */
352 for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) {
353 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
354 dwt_list[i].comp);
355 if (retval != ERROR_OK)
356 return retval;
357 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
358 dwt_list[i].mask);
359 if (retval != ERROR_OK)
360 return retval;
361 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
362 dwt_list[i].function);
363 if (retval != ERROR_OK)
364 return retval;
365 }
366 retval = dap_run(swjdp);
367 if (retval != ERROR_OK)
368 return retval;
369
370 register_cache_invalidate(armv7m->arm.core_cache);
371
372 /* make sure we have latest dhcsr flags */
373 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
374
375 return retval;
376 }
377
378 static int cortex_m_examine_debug_reason(struct target *target)
379 {
380 struct cortex_m_common *cortex_m = target_to_cm(target);
381
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
384
385 if ((target->debug_reason != DBG_REASON_DBGRQ)
386 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
387 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
388 target->debug_reason = DBG_REASON_BREAKPOINT;
389 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
390 target->debug_reason = DBG_REASON_WPTANDBKPT;
391 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
392 target->debug_reason = DBG_REASON_WATCHPOINT;
393 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
394 target->debug_reason = DBG_REASON_BREAKPOINT;
395 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
396 target->debug_reason = DBG_REASON_DBGRQ;
397 else /* HALTED */
398 target->debug_reason = DBG_REASON_UNDEFINED;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int cortex_m_examine_exception_reason(struct target *target)
405 {
406 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
407 struct armv7m_common *armv7m = target_to_armv7m(target);
408 struct adiv5_dap *swjdp = armv7m->arm.dap;
409 int retval;
410
411 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
412 if (retval != ERROR_OK)
413 return retval;
414 switch (armv7m->exception_number) {
415 case 2: /* NMI */
416 break;
417 case 3: /* Hard Fault */
418 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
419 if (retval != ERROR_OK)
420 return retval;
421 if (except_sr & 0x40000000) {
422 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
423 if (retval != ERROR_OK)
424 return retval;
425 }
426 break;
427 case 4: /* Memory Management */
428 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
429 if (retval != ERROR_OK)
430 return retval;
431 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
432 if (retval != ERROR_OK)
433 return retval;
434 break;
435 case 5: /* Bus Fault */
436 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
440 if (retval != ERROR_OK)
441 return retval;
442 break;
443 case 6: /* Usage Fault */
444 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
445 if (retval != ERROR_OK)
446 return retval;
447 break;
448 case 7: /* Secure Fault */
449 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
450 if (retval != ERROR_OK)
451 return retval;
452 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
453 if (retval != ERROR_OK)
454 return retval;
455 break;
456 case 11: /* SVCall */
457 break;
458 case 12: /* Debug Monitor */
459 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
460 if (retval != ERROR_OK)
461 return retval;
462 break;
463 case 14: /* PendSV */
464 break;
465 case 15: /* SysTick */
466 break;
467 default:
468 except_sr = 0;
469 break;
470 }
471 retval = dap_run(swjdp);
472 if (retval == ERROR_OK)
473 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
474 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
475 armv7m_exception_string(armv7m->exception_number),
476 shcsr, except_sr, cfsr, except_ar);
477 return retval;
478 }
479
480 static int cortex_m_debug_entry(struct target *target)
481 {
482 int i;
483 uint32_t xPSR;
484 int retval;
485 struct cortex_m_common *cortex_m = target_to_cm(target);
486 struct armv7m_common *armv7m = &cortex_m->armv7m;
487 struct arm *arm = &armv7m->arm;
488 struct reg *r;
489
490 LOG_DEBUG(" ");
491
492 /* Do this really early to minimize the window where the MASKINTS erratum
493 * can pile up pending interrupts. */
494 cortex_m_set_maskints_for_halt(target);
495
496 cortex_m_clear_halt(target);
497 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
498 if (retval != ERROR_OK)
499 return retval;
500
501 retval = armv7m->examine_debug_reason(target);
502 if (retval != ERROR_OK)
503 return retval;
504
505 /* examine PE security state */
506 bool secure_state = false;
507 if (armv7m->arm.is_armv8m) {
508 uint32_t dscsr;
509
510 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
511 if (retval != ERROR_OK)
512 return retval;
513
514 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
515 }
516
517 /* Examine target state and mode
518 * First load register accessible through core debug port */
519 int num_regs = arm->core_cache->num_regs;
520
521 for (i = 0; i < num_regs; i++) {
522 r = &armv7m->arm.core_cache->reg_list[i];
523 if (r->exist && !r->valid)
524 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
525 }
526
527 r = arm->cpsr;
528 xPSR = buf_get_u32(r->value, 0, 32);
529
530 /* Are we in an exception handler */
531 if (xPSR & 0x1FF) {
532 armv7m->exception_number = (xPSR & 0x1FF);
533
534 arm->core_mode = ARM_MODE_HANDLER;
535 arm->map = armv7m_msp_reg_map;
536 } else {
537 unsigned control = buf_get_u32(arm->core_cache
538 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
539
540 /* is this thread privileged? */
541 arm->core_mode = control & 1
542 ? ARM_MODE_USER_THREAD
543 : ARM_MODE_THREAD;
544
545 /* which stack is it using? */
546 if (control & 2)
547 arm->map = armv7m_psp_reg_map;
548 else
549 arm->map = armv7m_msp_reg_map;
550
551 armv7m->exception_number = 0;
552 }
553
554 if (armv7m->exception_number)
555 cortex_m_examine_exception_reason(target);
556
557 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
558 arm_mode_name(arm->core_mode),
559 buf_get_u32(arm->pc->value, 0, 32),
560 secure_state ? "Secure" : "Non-Secure",
561 target_state_name(target));
562
563 if (armv7m->post_debug_entry) {
564 retval = armv7m->post_debug_entry(target);
565 if (retval != ERROR_OK)
566 return retval;
567 }
568
569 return ERROR_OK;
570 }
571
572 static int cortex_m_poll(struct target *target)
573 {
574 int detected_failure = ERROR_OK;
575 int retval = ERROR_OK;
576 enum target_state prev_target_state = target->state;
577 struct cortex_m_common *cortex_m = target_to_cm(target);
578 struct armv7m_common *armv7m = &cortex_m->armv7m;
579
580 /* Read from Debug Halting Control and Status Register */
581 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
582 if (retval != ERROR_OK) {
583 target->state = TARGET_UNKNOWN;
584 return retval;
585 }
586
587 /* Recover from lockup. See ARMv7-M architecture spec,
588 * section B1.5.15 "Unrecoverable exception cases".
589 */
590 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
591 LOG_ERROR("%s -- clearing lockup after double fault",
592 target_name(target));
593 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
594 target->debug_reason = DBG_REASON_DBGRQ;
595
596 /* We have to execute the rest (the "finally" equivalent, but
597 * still throw this exception again).
598 */
599 detected_failure = ERROR_FAIL;
600
601 /* refresh status bits */
602 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
603 if (retval != ERROR_OK)
604 return retval;
605 }
606
607 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
608 if (target->state != TARGET_RESET) {
609 target->state = TARGET_RESET;
610 LOG_INFO("%s: external reset detected", target_name(target));
611 }
612 return ERROR_OK;
613 }
614
615 if (target->state == TARGET_RESET) {
616 /* Cannot switch context while running so endreset is
617 * called with target->state == TARGET_RESET
618 */
619 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
620 cortex_m->dcb_dhcsr);
621 retval = cortex_m_endreset_event(target);
622 if (retval != ERROR_OK) {
623 target->state = TARGET_UNKNOWN;
624 return retval;
625 }
626 target->state = TARGET_RUNNING;
627 prev_target_state = TARGET_RUNNING;
628 }
629
630 if (cortex_m->dcb_dhcsr & S_HALT) {
631 target->state = TARGET_HALTED;
632
633 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
634 retval = cortex_m_debug_entry(target);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (arm_semihosting(target, &retval) != 0)
639 return retval;
640
641 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
642 }
643 if (prev_target_state == TARGET_DEBUG_RUNNING) {
644 LOG_DEBUG(" ");
645 retval = cortex_m_debug_entry(target);
646 if (retval != ERROR_OK)
647 return retval;
648
649 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
650 }
651 }
652
653 if (target->state == TARGET_UNKNOWN) {
654 /* check if processor is retiring instructions or sleeping */
655 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
656 target->state = TARGET_RUNNING;
657 retval = ERROR_OK;
658 }
659 }
660
661 /* Check that target is truly halted, since the target could be resumed externally */
662 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
663 /* registers are now invalid */
664 register_cache_invalidate(armv7m->arm.core_cache);
665
666 target->state = TARGET_RUNNING;
667 LOG_WARNING("%s: external resume detected", target_name(target));
668 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
669 retval = ERROR_OK;
670 }
671
672 /* Did we detect a failure condition that we cleared? */
673 if (detected_failure != ERROR_OK)
674 retval = detected_failure;
675 return retval;
676 }
677
678 static int cortex_m_halt(struct target *target)
679 {
680 LOG_DEBUG("target->state: %s",
681 target_state_name(target));
682
683 if (target->state == TARGET_HALTED) {
684 LOG_DEBUG("target was already halted");
685 return ERROR_OK;
686 }
687
688 if (target->state == TARGET_UNKNOWN)
689 LOG_WARNING("target was in unknown state when halt was requested");
690
691 if (target->state == TARGET_RESET) {
692 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
693 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
694 return ERROR_TARGET_FAILURE;
695 } else {
696 /* we came here in a reset_halt or reset_init sequence
697 * debug entry was already prepared in cortex_m3_assert_reset()
698 */
699 target->debug_reason = DBG_REASON_DBGRQ;
700
701 return ERROR_OK;
702 }
703 }
704
705 /* Write to Debug Halting Control and Status Register */
706 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
707
708 /* Do this really early to minimize the window where the MASKINTS erratum
709 * can pile up pending interrupts. */
710 cortex_m_set_maskints_for_halt(target);
711
712 target->debug_reason = DBG_REASON_DBGRQ;
713
714 return ERROR_OK;
715 }
716
717 static int cortex_m_soft_reset_halt(struct target *target)
718 {
719 struct cortex_m_common *cortex_m = target_to_cm(target);
720 struct armv7m_common *armv7m = &cortex_m->armv7m;
721 uint32_t dcb_dhcsr = 0;
722 int retval, timeout = 0;
723
724 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
725 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
726 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
727 * core, not the peripherals */
728 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
729
730 if (!cortex_m->vectreset_supported) {
731 LOG_ERROR("VECTRESET is not supported on this Cortex-M core");
732 return ERROR_FAIL;
733 }
734
735 /* Set C_DEBUGEN */
736 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
737 if (retval != ERROR_OK)
738 return retval;
739
740 /* Enter debug state on reset; restore DEMCR in endreset_event() */
741 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
742 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
743 if (retval != ERROR_OK)
744 return retval;
745
746 /* Request a core-only reset */
747 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
748 AIRCR_VECTKEY | AIRCR_VECTRESET);
749 if (retval != ERROR_OK)
750 return retval;
751 target->state = TARGET_RESET;
752
753 /* registers are now invalid */
754 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
755
756 while (timeout < 100) {
757 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
758 if (retval == ERROR_OK) {
759 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
760 &cortex_m->nvic_dfsr);
761 if (retval != ERROR_OK)
762 return retval;
763 if ((dcb_dhcsr & S_HALT)
764 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
765 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
766 "DFSR 0x%08x",
767 (unsigned) dcb_dhcsr,
768 (unsigned) cortex_m->nvic_dfsr);
769 cortex_m_poll(target);
770 /* FIXME restore user's vector catch config */
771 return ERROR_OK;
772 } else
773 LOG_DEBUG("waiting for system reset-halt, "
774 "DHCSR 0x%08x, %d ms",
775 (unsigned) dcb_dhcsr, timeout);
776 }
777 timeout++;
778 alive_sleep(1);
779 }
780
781 return ERROR_OK;
782 }
783
784 void cortex_m_enable_breakpoints(struct target *target)
785 {
786 struct breakpoint *breakpoint = target->breakpoints;
787
788 /* set any pending breakpoints */
789 while (breakpoint) {
790 if (!breakpoint->set)
791 cortex_m_set_breakpoint(target, breakpoint);
792 breakpoint = breakpoint->next;
793 }
794 }
795
796 static int cortex_m_resume(struct target *target, int current,
797 target_addr_t address, int handle_breakpoints, int debug_execution)
798 {
799 struct armv7m_common *armv7m = target_to_armv7m(target);
800 struct breakpoint *breakpoint = NULL;
801 uint32_t resume_pc;
802 struct reg *r;
803
804 if (target->state != TARGET_HALTED) {
805 LOG_WARNING("target not halted");
806 return ERROR_TARGET_NOT_HALTED;
807 }
808
809 if (!debug_execution) {
810 target_free_all_working_areas(target);
811 cortex_m_enable_breakpoints(target);
812 cortex_m_enable_watchpoints(target);
813 }
814
815 if (debug_execution) {
816 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
817
818 /* Disable interrupts */
819 /* We disable interrupts in the PRIMASK register instead of
820 * masking with C_MASKINTS. This is probably the same issue
821 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
822 * in parallel with disabled interrupts can cause local faults
823 * to not be taken.
824 *
825 * This breaks non-debug (application) execution if not
826 * called from armv7m_start_algorithm() which saves registers.
827 */
828 buf_set_u32(r->value, 0, 1, 1);
829 r->dirty = true;
830 r->valid = true;
831
832 /* Make sure we are in Thumb mode, set xPSR.T bit */
833 /* armv7m_start_algorithm() initializes entire xPSR register.
834 * This duplicity handles the case when cortex_m_resume()
835 * is used with the debug_execution flag directly,
836 * not called through armv7m_start_algorithm().
837 */
838 r = armv7m->arm.cpsr;
839 buf_set_u32(r->value, 24, 1, 1);
840 r->dirty = true;
841 r->valid = true;
842 }
843
844 /* current = 1: continue on current pc, otherwise continue at <address> */
845 r = armv7m->arm.pc;
846 if (!current) {
847 buf_set_u32(r->value, 0, 32, address);
848 r->dirty = true;
849 r->valid = true;
850 }
851
852 /* if we halted last time due to a bkpt instruction
853 * then we have to manually step over it, otherwise
854 * the core will break again */
855
856 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
857 && !debug_execution)
858 armv7m_maybe_skip_bkpt_inst(target, NULL);
859
860 resume_pc = buf_get_u32(r->value, 0, 32);
861
862 armv7m_restore_context(target);
863
864 /* the front-end may request us not to handle breakpoints */
865 if (handle_breakpoints) {
866 /* Single step past breakpoint at current address */
867 breakpoint = breakpoint_find(target, resume_pc);
868 if (breakpoint) {
869 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
870 breakpoint->address,
871 breakpoint->unique_id);
872 cortex_m_unset_breakpoint(target, breakpoint);
873 cortex_m_single_step_core(target);
874 cortex_m_set_breakpoint(target, breakpoint);
875 }
876 }
877
878 /* Restart core */
879 cortex_m_set_maskints_for_run(target);
880 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
881
882 target->debug_reason = DBG_REASON_NOTHALTED;
883
884 /* registers are now invalid */
885 register_cache_invalidate(armv7m->arm.core_cache);
886
887 if (!debug_execution) {
888 target->state = TARGET_RUNNING;
889 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
890 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
891 } else {
892 target->state = TARGET_DEBUG_RUNNING;
893 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
894 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
895 }
896
897 return ERROR_OK;
898 }
899
900 /* int irqstepcount = 0; */
901 static int cortex_m_step(struct target *target, int current,
902 target_addr_t address, int handle_breakpoints)
903 {
904 struct cortex_m_common *cortex_m = target_to_cm(target);
905 struct armv7m_common *armv7m = &cortex_m->armv7m;
906 struct breakpoint *breakpoint = NULL;
907 struct reg *pc = armv7m->arm.pc;
908 bool bkpt_inst_found = false;
909 int retval;
910 bool isr_timed_out = false;
911
912 if (target->state != TARGET_HALTED) {
913 LOG_WARNING("target not halted");
914 return ERROR_TARGET_NOT_HALTED;
915 }
916
917 /* current = 1: continue on current pc, otherwise continue at <address> */
918 if (!current)
919 buf_set_u32(pc->value, 0, 32, address);
920
921 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
922
923 /* the front-end may request us not to handle breakpoints */
924 if (handle_breakpoints) {
925 breakpoint = breakpoint_find(target, pc_value);
926 if (breakpoint)
927 cortex_m_unset_breakpoint(target, breakpoint);
928 }
929
930 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
931
932 target->debug_reason = DBG_REASON_SINGLESTEP;
933
934 armv7m_restore_context(target);
935
936 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
937
938 /* if no bkpt instruction is found at pc then we can perform
939 * a normal step, otherwise we have to manually step over the bkpt
940 * instruction - as such simulate a step */
941 if (bkpt_inst_found == false) {
942 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
943 /* Automatic ISR masking mode off: Just step over the next
944 * instruction, with interrupts on or off as appropriate. */
945 cortex_m_set_maskints_for_step(target);
946 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
947 } else {
948 /* Process interrupts during stepping in a way they don't interfere
949 * debugging.
950 *
951 * Principle:
952 *
953 * Set a temporary break point at the current pc and let the core run
954 * with interrupts enabled. Pending interrupts get served and we run
955 * into the breakpoint again afterwards. Then we step over the next
956 * instruction with interrupts disabled.
957 *
958 * If the pending interrupts don't complete within time, we leave the
959 * core running. This may happen if the interrupts trigger faster
960 * than the core can process them or the handler doesn't return.
961 *
962 * If no more breakpoints are available we simply do a step with
963 * interrupts enabled.
964 *
965 */
966
967 /* 2012-09-29 ph
968 *
969 * If a break point is already set on the lower half word then a break point on
970 * the upper half word will not break again when the core is restarted. So we
971 * just step over the instruction with interrupts disabled.
972 *
973 * The documentation has no information about this, it was found by observation
974 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
975 * suffer from this problem.
976 *
977 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
978 * address has it always cleared. The former is done to indicate thumb mode
979 * to gdb.
980 *
981 */
982 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
983 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
984 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
985 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
986 /* Re-enable interrupts if appropriate */
987 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
988 cortex_m_set_maskints_for_halt(target);
989 } else {
990
991 /* Set a temporary break point */
992 if (breakpoint) {
993 retval = cortex_m_set_breakpoint(target, breakpoint);
994 } else {
995 enum breakpoint_type type = BKPT_HARD;
996 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
997 /* FPB rev.1 cannot handle such addr, try BKPT instr */
998 type = BKPT_SOFT;
999 }
1000 retval = breakpoint_add(target, pc_value, 2, type);
1001 }
1002
1003 bool tmp_bp_set = (retval == ERROR_OK);
1004
1005 /* No more breakpoints left, just do a step */
1006 if (!tmp_bp_set) {
1007 cortex_m_set_maskints_for_step(target);
1008 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1009 /* Re-enable interrupts if appropriate */
1010 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1011 cortex_m_set_maskints_for_halt(target);
1012 } else {
1013 /* Start the core */
1014 LOG_DEBUG("Starting core to serve pending interrupts");
1015 int64_t t_start = timeval_ms();
1016 cortex_m_set_maskints_for_run(target);
1017 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1018
1019 /* Wait for pending handlers to complete or timeout */
1020 do {
1021 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1022 DCB_DHCSR,
1023 &cortex_m->dcb_dhcsr);
1024 if (retval != ERROR_OK) {
1025 target->state = TARGET_UNKNOWN;
1026 return retval;
1027 }
1028 isr_timed_out = ((timeval_ms() - t_start) > 500);
1029 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1030
1031 /* only remove breakpoint if we created it */
1032 if (breakpoint)
1033 cortex_m_unset_breakpoint(target, breakpoint);
1034 else {
1035 /* Remove the temporary breakpoint */
1036 breakpoint_remove(target, pc_value);
1037 }
1038
1039 if (isr_timed_out) {
1040 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1041 "leaving target running");
1042 } else {
1043 /* Step over next instruction with interrupts disabled */
1044 cortex_m_set_maskints_for_step(target);
1045 cortex_m_write_debug_halt_mask(target,
1046 C_HALT | C_MASKINTS,
1047 0);
1048 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1049 /* Re-enable interrupts if appropriate */
1050 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1051 cortex_m_set_maskints_for_halt(target);
1052 }
1053 }
1054 }
1055 }
1056 }
1057
1058 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1059 if (retval != ERROR_OK)
1060 return retval;
1061
1062 /* registers are now invalid */
1063 register_cache_invalidate(armv7m->arm.core_cache);
1064
1065 if (breakpoint)
1066 cortex_m_set_breakpoint(target, breakpoint);
1067
1068 if (isr_timed_out) {
1069 /* Leave the core running. The user has to stop execution manually. */
1070 target->debug_reason = DBG_REASON_NOTHALTED;
1071 target->state = TARGET_RUNNING;
1072 return ERROR_OK;
1073 }
1074
1075 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1076 " nvic_icsr = 0x%" PRIx32,
1077 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1078
1079 retval = cortex_m_debug_entry(target);
1080 if (retval != ERROR_OK)
1081 return retval;
1082 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1083
1084 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1085 " nvic_icsr = 0x%" PRIx32,
1086 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1087
1088 return ERROR_OK;
1089 }
1090
1091 static int cortex_m_assert_reset(struct target *target)
1092 {
1093 struct cortex_m_common *cortex_m = target_to_cm(target);
1094 struct armv7m_common *armv7m = &cortex_m->armv7m;
1095 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1096
1097 LOG_DEBUG("target->state: %s",
1098 target_state_name(target));
1099
1100 enum reset_types jtag_reset_config = jtag_get_reset_config();
1101
1102 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1103 /* allow scripts to override the reset event */
1104
1105 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1106 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1107 target->state = TARGET_RESET;
1108
1109 return ERROR_OK;
1110 }
1111
1112 /* some cores support connecting while srst is asserted
1113 * use that mode is it has been configured */
1114
1115 bool srst_asserted = false;
1116
1117 if (!target_was_examined(target)) {
1118 if (jtag_reset_config & RESET_HAS_SRST) {
1119 adapter_assert_reset();
1120 if (target->reset_halt)
1121 LOG_ERROR("Target not examined, will not halt after reset!");
1122 return ERROR_OK;
1123 } else {
1124 LOG_ERROR("Target not examined, reset NOT asserted!");
1125 return ERROR_FAIL;
1126 }
1127 }
1128
1129 if ((jtag_reset_config & RESET_HAS_SRST) &&
1130 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1131 adapter_assert_reset();
1132 srst_asserted = true;
1133 }
1134
1135 /* Enable debug requests */
1136 int retval;
1137 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1138 /* Store important errors instead of failing and proceed to reset assert */
1139
1140 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1141 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1142
1143 /* If the processor is sleeping in a WFI or WFE instruction, the
1144 * C_HALT bit must be asserted to regain control */
1145 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1146 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1147
1148 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1149 /* Ignore less important errors */
1150
1151 if (!target->reset_halt) {
1152 /* Set/Clear C_MASKINTS in a separate operation */
1153 cortex_m_set_maskints_for_run(target);
1154
1155 /* clear any debug flags before resuming */
1156 cortex_m_clear_halt(target);
1157
1158 /* clear C_HALT in dhcsr reg */
1159 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1160 } else {
1161 /* Halt in debug on reset; endreset_event() restores DEMCR.
1162 *
1163 * REVISIT catching BUSERR presumably helps to defend against
1164 * bad vector table entries. Should this include MMERR or
1165 * other flags too?
1166 */
1167 int retval2;
1168 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1169 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1170 if (retval != ERROR_OK || retval2 != ERROR_OK)
1171 LOG_INFO("AP write error, reset will not halt");
1172 }
1173
1174 if (jtag_reset_config & RESET_HAS_SRST) {
1175 /* default to asserting srst */
1176 if (!srst_asserted)
1177 adapter_assert_reset();
1178
1179 /* srst is asserted, ignore AP access errors */
1180 retval = ERROR_OK;
1181 } else {
1182 /* Use a standard Cortex-M3 software reset mechanism.
1183 * We default to using VECRESET as it is supported on all current cores
1184 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1185 * This has the disadvantage of not resetting the peripherals, so a
1186 * reset-init event handler is needed to perform any peripheral resets.
1187 */
1188 if (!cortex_m->vectreset_supported
1189 && reset_config == CORTEX_M_RESET_VECTRESET) {
1190 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1191 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1192 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1193 }
1194
1195 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1196 ? "SYSRESETREQ" : "VECTRESET");
1197
1198 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1199 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1200 "handler to reset any peripherals or configure hardware srst support.");
1201 }
1202
1203 int retval3;
1204 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1205 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1206 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1207 if (retval3 != ERROR_OK)
1208 LOG_DEBUG("Ignoring AP write error right after reset");
1209
1210 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1211 if (retval3 != ERROR_OK) {
1212 LOG_ERROR("DP initialisation failed");
1213 /* The error return value must not be propagated in this case.
1214 * SYSRESETREQ or VECTRESET have been possibly triggered
1215 * so reset processing should continue */
1216 } else {
1217 /* I do not know why this is necessary, but it
1218 * fixes strange effects (step/resume cause NMI
1219 * after reset) on LM3S6918 -- Michael Schwingen
1220 */
1221 uint32_t tmp;
1222 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1223 }
1224 }
1225
1226 target->state = TARGET_RESET;
1227 jtag_sleep(50000);
1228
1229 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1230
1231 /* now return stored error code if any */
1232 if (retval != ERROR_OK)
1233 return retval;
1234
1235 if (target->reset_halt) {
1236 retval = target_halt(target);
1237 if (retval != ERROR_OK)
1238 return retval;
1239 }
1240
1241 return ERROR_OK;
1242 }
1243
1244 static int cortex_m_deassert_reset(struct target *target)
1245 {
1246 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1247
1248 LOG_DEBUG("target->state: %s",
1249 target_state_name(target));
1250
1251 /* deassert reset lines */
1252 adapter_deassert_reset();
1253
1254 enum reset_types jtag_reset_config = jtag_get_reset_config();
1255
1256 if ((jtag_reset_config & RESET_HAS_SRST) &&
1257 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1258 target_was_examined(target)) {
1259
1260 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1261 if (retval != ERROR_OK) {
1262 LOG_ERROR("DP initialisation failed");
1263 return retval;
1264 }
1265 }
1266
1267 return ERROR_OK;
1268 }
1269
1270 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1271 {
1272 int retval;
1273 unsigned int fp_num = 0;
1274 struct cortex_m_common *cortex_m = target_to_cm(target);
1275 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1276
1277 if (breakpoint->set) {
1278 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1279 return ERROR_OK;
1280 }
1281
1282 if (breakpoint->type == BKPT_HARD) {
1283 uint32_t fpcr_value;
1284 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1285 fp_num++;
1286 if (fp_num >= cortex_m->fp_num_code) {
1287 LOG_ERROR("Can not find free FPB Comparator!");
1288 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1289 }
1290 breakpoint->set = fp_num + 1;
1291 fpcr_value = breakpoint->address | 1;
1292 if (cortex_m->fp_rev == 0) {
1293 if (breakpoint->address > 0x1FFFFFFF) {
1294 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1295 return ERROR_FAIL;
1296 }
1297 uint32_t hilo;
1298 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1299 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1300 } else if (cortex_m->fp_rev > 1) {
1301 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1302 return ERROR_FAIL;
1303 }
1304 comparator_list[fp_num].used = true;
1305 comparator_list[fp_num].fpcr_value = fpcr_value;
1306 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1307 comparator_list[fp_num].fpcr_value);
1308 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1309 fp_num,
1310 comparator_list[fp_num].fpcr_value);
1311 if (!cortex_m->fpb_enabled) {
1312 LOG_DEBUG("FPB wasn't enabled, do it now");
1313 retval = cortex_m_enable_fpb(target);
1314 if (retval != ERROR_OK) {
1315 LOG_ERROR("Failed to enable the FPB");
1316 return retval;
1317 }
1318
1319 cortex_m->fpb_enabled = true;
1320 }
1321 } else if (breakpoint->type == BKPT_SOFT) {
1322 uint8_t code[4];
1323
1324 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1325 * semihosting; don't use that. Otherwise the BKPT
1326 * parameter is arbitrary.
1327 */
1328 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1329 retval = target_read_memory(target,
1330 breakpoint->address & 0xFFFFFFFE,
1331 breakpoint->length, 1,
1332 breakpoint->orig_instr);
1333 if (retval != ERROR_OK)
1334 return retval;
1335 retval = target_write_memory(target,
1336 breakpoint->address & 0xFFFFFFFE,
1337 breakpoint->length, 1,
1338 code);
1339 if (retval != ERROR_OK)
1340 return retval;
1341 breakpoint->set = true;
1342 }
1343
1344 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1345 breakpoint->unique_id,
1346 (int)(breakpoint->type),
1347 breakpoint->address,
1348 breakpoint->length,
1349 breakpoint->set);
1350
1351 return ERROR_OK;
1352 }
1353
1354 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1355 {
1356 int retval;
1357 struct cortex_m_common *cortex_m = target_to_cm(target);
1358 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1359
1360 if (breakpoint->set <= 0) {
1361 LOG_WARNING("breakpoint not set");
1362 return ERROR_OK;
1363 }
1364
1365 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1366 breakpoint->unique_id,
1367 (int)(breakpoint->type),
1368 breakpoint->address,
1369 breakpoint->length,
1370 breakpoint->set);
1371
1372 if (breakpoint->type == BKPT_HARD) {
1373 unsigned int fp_num = breakpoint->set - 1;
1374 if (fp_num >= cortex_m->fp_num_code) {
1375 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1376 return ERROR_OK;
1377 }
1378 comparator_list[fp_num].used = false;
1379 comparator_list[fp_num].fpcr_value = 0;
1380 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1381 comparator_list[fp_num].fpcr_value);
1382 } else {
1383 /* restore original instruction (kept in target endianness) */
1384 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1385 breakpoint->length, 1,
1386 breakpoint->orig_instr);
1387 if (retval != ERROR_OK)
1388 return retval;
1389 }
1390 breakpoint->set = false;
1391
1392 return ERROR_OK;
1393 }
1394
1395 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1396 {
1397 if (breakpoint->length == 3) {
1398 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1399 breakpoint->length = 2;
1400 }
1401
1402 if ((breakpoint->length != 2)) {
1403 LOG_INFO("only breakpoints of two bytes length supported");
1404 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1405 }
1406
1407 return cortex_m_set_breakpoint(target, breakpoint);
1408 }
1409
1410 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1411 {
1412 if (!breakpoint->set)
1413 return ERROR_OK;
1414
1415 return cortex_m_unset_breakpoint(target, breakpoint);
1416 }
1417
1418 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1419 {
1420 unsigned int dwt_num = 0;
1421 struct cortex_m_common *cortex_m = target_to_cm(target);
1422
1423 /* REVISIT Don't fully trust these "not used" records ... users
1424 * may set up breakpoints by hand, e.g. dual-address data value
1425 * watchpoint using comparator #1; comparator #0 matching cycle
1426 * count; send data trace info through ITM and TPIU; etc
1427 */
1428 struct cortex_m_dwt_comparator *comparator;
1429
1430 for (comparator = cortex_m->dwt_comparator_list;
1431 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1432 comparator++, dwt_num++)
1433 continue;
1434 if (dwt_num >= cortex_m->dwt_num_comp) {
1435 LOG_ERROR("Can not find free DWT Comparator");
1436 return ERROR_FAIL;
1437 }
1438 comparator->used = true;
1439 watchpoint->set = dwt_num + 1;
1440
1441 comparator->comp = watchpoint->address;
1442 target_write_u32(target, comparator->dwt_comparator_address + 0,
1443 comparator->comp);
1444
1445 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1446 uint32_t mask = 0, temp;
1447
1448 /* watchpoint params were validated earlier */
1449 temp = watchpoint->length;
1450 while (temp) {
1451 temp >>= 1;
1452 mask++;
1453 }
1454 mask--;
1455
1456 comparator->mask = mask;
1457 target_write_u32(target, comparator->dwt_comparator_address + 4,
1458 comparator->mask);
1459
1460 switch (watchpoint->rw) {
1461 case WPT_READ:
1462 comparator->function = 5;
1463 break;
1464 case WPT_WRITE:
1465 comparator->function = 6;
1466 break;
1467 case WPT_ACCESS:
1468 comparator->function = 7;
1469 break;
1470 }
1471 } else {
1472 uint32_t data_size = watchpoint->length >> 1;
1473 comparator->mask = (watchpoint->length >> 1) | 1;
1474
1475 switch (watchpoint->rw) {
1476 case WPT_ACCESS:
1477 comparator->function = 4;
1478 break;
1479 case WPT_WRITE:
1480 comparator->function = 5;
1481 break;
1482 case WPT_READ:
1483 comparator->function = 6;
1484 break;
1485 }
1486 comparator->function = comparator->function | (1 << 4) |
1487 (data_size << 10);
1488 }
1489
1490 target_write_u32(target, comparator->dwt_comparator_address + 8,
1491 comparator->function);
1492
1493 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1494 watchpoint->unique_id, dwt_num,
1495 (unsigned) comparator->comp,
1496 (unsigned) comparator->mask,
1497 (unsigned) comparator->function);
1498 return ERROR_OK;
1499 }
1500
1501 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1502 {
1503 struct cortex_m_common *cortex_m = target_to_cm(target);
1504 struct cortex_m_dwt_comparator *comparator;
1505
1506 if (watchpoint->set <= 0) {
1507 LOG_WARNING("watchpoint (wpid: %d) not set",
1508 watchpoint->unique_id);
1509 return ERROR_OK;
1510 }
1511
1512 unsigned int dwt_num = watchpoint->set - 1;
1513
1514 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1515 watchpoint->unique_id, dwt_num,
1516 (unsigned) watchpoint->address);
1517
1518 if (dwt_num >= cortex_m->dwt_num_comp) {
1519 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1520 return ERROR_OK;
1521 }
1522
1523 comparator = cortex_m->dwt_comparator_list + dwt_num;
1524 comparator->used = false;
1525 comparator->function = 0;
1526 target_write_u32(target, comparator->dwt_comparator_address + 8,
1527 comparator->function);
1528
1529 watchpoint->set = false;
1530
1531 return ERROR_OK;
1532 }
1533
1534 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1535 {
1536 struct cortex_m_common *cortex_m = target_to_cm(target);
1537
1538 if (cortex_m->dwt_comp_available < 1) {
1539 LOG_DEBUG("no comparators?");
1540 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1541 }
1542
1543 /* hardware doesn't support data value masking */
1544 if (watchpoint->mask != ~(uint32_t)0) {
1545 LOG_DEBUG("watchpoint value masks not supported");
1546 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1547 }
1548
1549 /* hardware allows address masks of up to 32K */
1550 unsigned mask;
1551
1552 for (mask = 0; mask < 16; mask++) {
1553 if ((1u << mask) == watchpoint->length)
1554 break;
1555 }
1556 if (mask == 16) {
1557 LOG_DEBUG("unsupported watchpoint length");
1558 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1559 }
1560 if (watchpoint->address & ((1 << mask) - 1)) {
1561 LOG_DEBUG("watchpoint address is unaligned");
1562 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1563 }
1564
1565 /* Caller doesn't seem to be able to describe watching for data
1566 * values of zero; that flags "no value".
1567 *
1568 * REVISIT This DWT may well be able to watch for specific data
1569 * values. Requires comparator #1 to set DATAVMATCH and match
1570 * the data, and another comparator (DATAVADDR0) matching addr.
1571 */
1572 if (watchpoint->value) {
1573 LOG_DEBUG("data value watchpoint not YET supported");
1574 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1575 }
1576
1577 cortex_m->dwt_comp_available--;
1578 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1579
1580 return ERROR_OK;
1581 }
1582
1583 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1584 {
1585 struct cortex_m_common *cortex_m = target_to_cm(target);
1586
1587 /* REVISIT why check? DWT can be updated with core running ... */
1588 if (target->state != TARGET_HALTED) {
1589 LOG_WARNING("target not halted");
1590 return ERROR_TARGET_NOT_HALTED;
1591 }
1592
1593 if (watchpoint->set)
1594 cortex_m_unset_watchpoint(target, watchpoint);
1595
1596 cortex_m->dwt_comp_available++;
1597 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1598
1599 return ERROR_OK;
1600 }
1601
1602 int cortex_m_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1603 {
1604 if (target->debug_reason != DBG_REASON_WATCHPOINT)
1605 return ERROR_FAIL;
1606
1607 struct cortex_m_common *cortex_m = target_to_cm(target);
1608
1609 for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
1610 if (!wp->set)
1611 continue;
1612
1613 unsigned int dwt_num = wp->set - 1;
1614 struct cortex_m_dwt_comparator *comparator = cortex_m->dwt_comparator_list + dwt_num;
1615
1616 uint32_t dwt_function;
1617 int retval = target_read_u32(target, comparator->dwt_comparator_address + 8, &dwt_function);
1618 if (retval != ERROR_OK)
1619 return ERROR_FAIL;
1620
1621 /* check the MATCHED bit */
1622 if (dwt_function & BIT(24)) {
1623 *hit_watchpoint = wp;
1624 return ERROR_OK;
1625 }
1626 }
1627
1628 return ERROR_FAIL;
1629 }
1630
1631 void cortex_m_enable_watchpoints(struct target *target)
1632 {
1633 struct watchpoint *watchpoint = target->watchpoints;
1634
1635 /* set any pending watchpoints */
1636 while (watchpoint) {
1637 if (!watchpoint->set)
1638 cortex_m_set_watchpoint(target, watchpoint);
1639 watchpoint = watchpoint->next;
1640 }
1641 }
1642
1643 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1644 uint32_t size, uint32_t count, uint8_t *buffer)
1645 {
1646 struct armv7m_common *armv7m = target_to_armv7m(target);
1647
1648 if (armv7m->arm.is_armv6m) {
1649 /* armv6m does not handle unaligned memory access */
1650 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1651 return ERROR_TARGET_UNALIGNED_ACCESS;
1652 }
1653
1654 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1655 }
1656
1657 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1658 uint32_t size, uint32_t count, const uint8_t *buffer)
1659 {
1660 struct armv7m_common *armv7m = target_to_armv7m(target);
1661
1662 if (armv7m->arm.is_armv6m) {
1663 /* armv6m does not handle unaligned memory access */
1664 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1665 return ERROR_TARGET_UNALIGNED_ACCESS;
1666 }
1667
1668 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1669 }
1670
1671 static int cortex_m_init_target(struct command_context *cmd_ctx,
1672 struct target *target)
1673 {
1674 armv7m_build_reg_cache(target);
1675 arm_semihosting_init(target);
1676 return ERROR_OK;
1677 }
1678
1679 void cortex_m_deinit_target(struct target *target)
1680 {
1681 struct cortex_m_common *cortex_m = target_to_cm(target);
1682
1683 free(cortex_m->fp_comparator_list);
1684
1685 cortex_m_dwt_free(target);
1686 armv7m_free_reg_cache(target);
1687
1688 free(target->private_config);
1689 free(cortex_m);
1690 }
1691
1692 int cortex_m_profiling(struct target *target, uint32_t *samples,
1693 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1694 {
1695 struct timeval timeout, now;
1696 struct armv7m_common *armv7m = target_to_armv7m(target);
1697 uint32_t reg_value;
1698 int retval;
1699
1700 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1701 if (retval != ERROR_OK) {
1702 LOG_ERROR("Error while reading PCSR");
1703 return retval;
1704 }
1705 if (reg_value == 0) {
1706 LOG_INFO("PCSR sampling not supported on this processor.");
1707 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1708 }
1709
1710 gettimeofday(&timeout, NULL);
1711 timeval_add_time(&timeout, seconds, 0);
1712
1713 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1714
1715 /* Make sure the target is running */
1716 target_poll(target);
1717 if (target->state == TARGET_HALTED)
1718 retval = target_resume(target, 1, 0, 0, 0);
1719
1720 if (retval != ERROR_OK) {
1721 LOG_ERROR("Error while resuming target");
1722 return retval;
1723 }
1724
1725 uint32_t sample_count = 0;
1726
1727 for (;;) {
1728 if (armv7m && armv7m->debug_ap) {
1729 uint32_t read_count = max_num_samples - sample_count;
1730 if (read_count > 1024)
1731 read_count = 1024;
1732
1733 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1734 (void *)&samples[sample_count],
1735 4, read_count, DWT_PCSR);
1736 sample_count += read_count;
1737 } else {
1738 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1739 }
1740
1741 if (retval != ERROR_OK) {
1742 LOG_ERROR("Error while reading PCSR");
1743 return retval;
1744 }
1745
1746
1747 gettimeofday(&now, NULL);
1748 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1749 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1750 break;
1751 }
1752 }
1753
1754 *num_samples = sample_count;
1755 return retval;
1756 }
1757
1758
1759 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1760 * on r/w if the core is not running, and clear on resume or reset ... or
1761 * at least, in a post_restore_context() method.
1762 */
1763
1764 struct dwt_reg_state {
1765 struct target *target;
1766 uint32_t addr;
1767 uint8_t value[4]; /* scratch/cache */
1768 };
1769
1770 static int cortex_m_dwt_get_reg(struct reg *reg)
1771 {
1772 struct dwt_reg_state *state = reg->arch_info;
1773
1774 uint32_t tmp;
1775 int retval = target_read_u32(state->target, state->addr, &tmp);
1776 if (retval != ERROR_OK)
1777 return retval;
1778
1779 buf_set_u32(state->value, 0, 32, tmp);
1780 return ERROR_OK;
1781 }
1782
1783 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1784 {
1785 struct dwt_reg_state *state = reg->arch_info;
1786
1787 return target_write_u32(state->target, state->addr,
1788 buf_get_u32(buf, 0, reg->size));
1789 }
1790
1791 struct dwt_reg {
1792 uint32_t addr;
1793 const char *name;
1794 unsigned size;
1795 };
1796
1797 static const struct dwt_reg dwt_base_regs[] = {
1798 { DWT_CTRL, "dwt_ctrl", 32, },
1799 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1800 * increments while the core is asleep.
1801 */
1802 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1803 /* plus some 8 bit counters, useful for profiling with TPIU */
1804 };
1805
1806 static const struct dwt_reg dwt_comp[] = {
1807 #define DWT_COMPARATOR(i) \
1808 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1809 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1810 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1811 DWT_COMPARATOR(0),
1812 DWT_COMPARATOR(1),
1813 DWT_COMPARATOR(2),
1814 DWT_COMPARATOR(3),
1815 DWT_COMPARATOR(4),
1816 DWT_COMPARATOR(5),
1817 DWT_COMPARATOR(6),
1818 DWT_COMPARATOR(7),
1819 DWT_COMPARATOR(8),
1820 DWT_COMPARATOR(9),
1821 DWT_COMPARATOR(10),
1822 DWT_COMPARATOR(11),
1823 DWT_COMPARATOR(12),
1824 DWT_COMPARATOR(13),
1825 DWT_COMPARATOR(14),
1826 DWT_COMPARATOR(15),
1827 #undef DWT_COMPARATOR
1828 };
1829
1830 static const struct reg_arch_type dwt_reg_type = {
1831 .get = cortex_m_dwt_get_reg,
1832 .set = cortex_m_dwt_set_reg,
1833 };
1834
1835 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1836 {
1837 struct dwt_reg_state *state;
1838
1839 state = calloc(1, sizeof(*state));
1840 if (!state)
1841 return;
1842 state->addr = d->addr;
1843 state->target = t;
1844
1845 r->name = d->name;
1846 r->size = d->size;
1847 r->value = state->value;
1848 r->arch_info = state;
1849 r->type = &dwt_reg_type;
1850 }
1851
1852 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1853 {
1854 uint32_t dwtcr;
1855 struct reg_cache *cache;
1856 struct cortex_m_dwt_comparator *comparator;
1857 int reg;
1858
1859 target_read_u32(target, DWT_CTRL, &dwtcr);
1860 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1861 if (!dwtcr) {
1862 LOG_DEBUG("no DWT");
1863 return;
1864 }
1865
1866 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1867 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1868
1869 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1870 cm->dwt_comp_available = cm->dwt_num_comp;
1871 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1872 sizeof(struct cortex_m_dwt_comparator));
1873 if (!cm->dwt_comparator_list) {
1874 fail0:
1875 cm->dwt_num_comp = 0;
1876 LOG_ERROR("out of mem");
1877 return;
1878 }
1879
1880 cache = calloc(1, sizeof(*cache));
1881 if (!cache) {
1882 fail1:
1883 free(cm->dwt_comparator_list);
1884 goto fail0;
1885 }
1886 cache->name = "Cortex-M DWT registers";
1887 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1888 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1889 if (!cache->reg_list) {
1890 free(cache);
1891 goto fail1;
1892 }
1893
1894 for (reg = 0; reg < 2; reg++)
1895 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1896 dwt_base_regs + reg);
1897
1898 comparator = cm->dwt_comparator_list;
1899 for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1900 int j;
1901
1902 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1903 for (j = 0; j < 3; j++, reg++)
1904 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1905 dwt_comp + 3 * i + j);
1906
1907 /* make sure we clear any watchpoints enabled on the target */
1908 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1909 }
1910
1911 *register_get_last_cache_p(&target->reg_cache) = cache;
1912 cm->dwt_cache = cache;
1913
1914 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1915 dwtcr, cm->dwt_num_comp,
1916 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1917
1918 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1919 * implement single-address data value watchpoints ... so we
1920 * won't need to check it later, when asked to set one up.
1921 */
1922 }
1923
1924 static void cortex_m_dwt_free(struct target *target)
1925 {
1926 struct cortex_m_common *cm = target_to_cm(target);
1927 struct reg_cache *cache = cm->dwt_cache;
1928
1929 free(cm->dwt_comparator_list);
1930 cm->dwt_comparator_list = NULL;
1931 cm->dwt_num_comp = 0;
1932
1933 if (cache) {
1934 register_unlink_cache(&target->reg_cache, cache);
1935
1936 if (cache->reg_list) {
1937 for (size_t i = 0; i < cache->num_regs; i++)
1938 free(cache->reg_list[i].arch_info);
1939 free(cache->reg_list);
1940 }
1941 free(cache);
1942 }
1943 cm->dwt_cache = NULL;
1944 }
1945
1946 #define MVFR0 0xe000ef40
1947 #define MVFR1 0xe000ef44
1948
1949 #define MVFR0_DEFAULT_M4 0x10110021
1950 #define MVFR1_DEFAULT_M4 0x11000011
1951
1952 #define MVFR0_DEFAULT_M7_SP 0x10110021
1953 #define MVFR0_DEFAULT_M7_DP 0x10110221
1954 #define MVFR1_DEFAULT_M7_SP 0x11000011
1955 #define MVFR1_DEFAULT_M7_DP 0x12000011
1956
1957 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
1958 struct adiv5_ap **debug_ap)
1959 {
1960 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
1961 return ERROR_OK;
1962
1963 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
1964 }
1965
1966 int cortex_m_examine(struct target *target)
1967 {
1968 int retval;
1969 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1970 struct cortex_m_common *cortex_m = target_to_cm(target);
1971 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1972 struct armv7m_common *armv7m = target_to_armv7m(target);
1973
1974 /* stlink shares the examine handler but does not support
1975 * all its calls */
1976 if (!armv7m->stlink) {
1977 if (cortex_m->apsel == DP_APSEL_INVALID) {
1978 /* Search for the MEM-AP */
1979 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
1980 if (retval != ERROR_OK) {
1981 LOG_ERROR("Could not find MEM-AP to control the core");
1982 return retval;
1983 }
1984 } else {
1985 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1986 }
1987
1988 /* Leave (only) generic DAP stuff for debugport_init(); */
1989 armv7m->debug_ap->memaccess_tck = 8;
1990
1991 retval = mem_ap_init(armv7m->debug_ap);
1992 if (retval != ERROR_OK)
1993 return retval;
1994 }
1995
1996 if (!target_was_examined(target)) {
1997 target_set_examined(target);
1998
1999 /* Read from Device Identification Registers */
2000 retval = target_read_u32(target, CPUID, &cpuid);
2001 if (retval != ERROR_OK)
2002 return retval;
2003
2004 /* Get CPU Type */
2005 unsigned int core = (cpuid >> 4) & 0xf;
2006
2007 /* Check if it is an ARMv8-M core */
2008 armv7m->arm.is_armv8m = true;
2009
2010 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
2011 case CORTEX_M23_PARTNO:
2012 core = 23;
2013 break;
2014 case CORTEX_M33_PARTNO:
2015 core = 33;
2016 break;
2017 case CORTEX_M35P_PARTNO:
2018 core = 35;
2019 break;
2020 case CORTEX_M55_PARTNO:
2021 core = 55;
2022 break;
2023 default:
2024 armv7m->arm.is_armv8m = false;
2025 break;
2026 }
2027
2028
2029 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2030 core, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2031 cortex_m->maskints_erratum = false;
2032 if (core == 7) {
2033 uint8_t rev, patch;
2034 rev = (cpuid >> 20) & 0xf;
2035 patch = (cpuid >> 0) & 0xf;
2036 if ((rev == 0) && (patch < 2)) {
2037 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2038 cortex_m->maskints_erratum = true;
2039 }
2040 }
2041 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2042
2043 if (core == 4) {
2044 target_read_u32(target, MVFR0, &mvfr0);
2045 target_read_u32(target, MVFR1, &mvfr1);
2046
2047 /* test for floating point feature on Cortex-M4 */
2048 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2049 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", core);
2050 armv7m->fp_feature = FPV4_SP;
2051 }
2052 } else if (core == 7 || core == 33 || core == 35 || core == 55) {
2053 target_read_u32(target, MVFR0, &mvfr0);
2054 target_read_u32(target, MVFR1, &mvfr1);
2055
2056 /* test for floating point features on Cortex-M7 */
2057 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2058 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", core);
2059 armv7m->fp_feature = FPV5_SP;
2060 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2061 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", core);
2062 armv7m->fp_feature = FPV5_DP;
2063 }
2064 } else if (core == 0) {
2065 /* Cortex-M0 does not support unaligned memory access */
2066 armv7m->arm.is_armv6m = true;
2067 }
2068
2069 /* VECTRESET is supported only on ARMv7-M cores */
2070 cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
2071
2072 /* Check for FPU, otherwise mark FPU register as non-existent */
2073 if (armv7m->fp_feature == FP_NONE)
2074 for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2075 armv7m->arm.core_cache->reg_list[idx].exist = false;
2076
2077 if (!armv7m->arm.is_armv8m)
2078 for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++)
2079 armv7m->arm.core_cache->reg_list[idx].exist = false;
2080
2081 if (!armv7m->stlink) {
2082 if (core == 3 || core == 4)
2083 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2084 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2085 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2086 else if (core == 7)
2087 /* Cortex-M7 has only 1024 bytes autoincrement range */
2088 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2089 }
2090
2091 /* Enable debug requests */
2092 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2093 if (retval != ERROR_OK)
2094 return retval;
2095 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2096 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2097
2098 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2099 if (retval != ERROR_OK)
2100 return retval;
2101 cortex_m->dcb_dhcsr = dhcsr;
2102 }
2103
2104 /* Configure trace modules */
2105 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2106 if (retval != ERROR_OK)
2107 return retval;
2108
2109 if (armv7m->trace_config.itm_deferred_config)
2110 armv7m_trace_itm_config(target);
2111
2112 /* NOTE: FPB and DWT are both optional. */
2113
2114 /* Setup FPB */
2115 target_read_u32(target, FP_CTRL, &fpcr);
2116 /* bits [14:12] and [7:4] */
2117 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2118 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2119 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2120 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2121 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2122 free(cortex_m->fp_comparator_list);
2123 cortex_m->fp_comparator_list = calloc(
2124 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2125 sizeof(struct cortex_m_fp_comparator));
2126 cortex_m->fpb_enabled = fpcr & 1;
2127 for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2128 cortex_m->fp_comparator_list[i].type =
2129 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2130 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2131
2132 /* make sure we clear any breakpoints enabled on the target */
2133 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2134 }
2135 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2136 fpcr,
2137 cortex_m->fp_num_code,
2138 cortex_m->fp_num_lit);
2139
2140 /* Setup DWT */
2141 cortex_m_dwt_free(target);
2142 cortex_m_dwt_setup(cortex_m, target);
2143
2144 /* These hardware breakpoints only work for code in flash! */
2145 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2146 target_name(target),
2147 cortex_m->fp_num_code,
2148 cortex_m->dwt_num_comp);
2149 }
2150
2151 return ERROR_OK;
2152 }
2153
2154 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2155 {
2156 struct armv7m_common *armv7m = target_to_armv7m(target);
2157 uint16_t dcrdr;
2158 uint8_t buf[2];
2159 int retval;
2160
2161 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2162 if (retval != ERROR_OK)
2163 return retval;
2164
2165 dcrdr = target_buffer_get_u16(target, buf);
2166 *ctrl = (uint8_t)dcrdr;
2167 *value = (uint8_t)(dcrdr >> 8);
2168
2169 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2170
2171 /* write ack back to software dcc register
2172 * signify we have read data */
2173 if (dcrdr & (1 << 0)) {
2174 target_buffer_set_u16(target, buf, 0);
2175 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2176 if (retval != ERROR_OK)
2177 return retval;
2178 }
2179
2180 return ERROR_OK;
2181 }
2182
2183 static int cortex_m_target_request_data(struct target *target,
2184 uint32_t size, uint8_t *buffer)
2185 {
2186 uint8_t data;
2187 uint8_t ctrl;
2188 uint32_t i;
2189
2190 for (i = 0; i < (size * 4); i++) {
2191 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2192 if (retval != ERROR_OK)
2193 return retval;
2194 buffer[i] = data;
2195 }
2196
2197 return ERROR_OK;
2198 }
2199
2200 static int cortex_m_handle_target_request(void *priv)
2201 {
2202 struct target *target = priv;
2203 if (!target_was_examined(target))
2204 return ERROR_OK;
2205
2206 if (!target->dbg_msg_enabled)
2207 return ERROR_OK;
2208
2209 if (target->state == TARGET_RUNNING) {
2210 uint8_t data;
2211 uint8_t ctrl;
2212 int retval;
2213
2214 retval = cortex_m_dcc_read(target, &data, &ctrl);
2215 if (retval != ERROR_OK)
2216 return retval;
2217
2218 /* check if we have data */
2219 if (ctrl & (1 << 0)) {
2220 uint32_t request;
2221
2222 /* we assume target is quick enough */
2223 request = data;
2224 for (int i = 1; i <= 3; i++) {
2225 retval = cortex_m_dcc_read(target, &data, &ctrl);
2226 if (retval != ERROR_OK)
2227 return retval;
2228 request |= ((uint32_t)data << (i * 8));
2229 }
2230 target_request(target, request);
2231 }
2232 }
2233
2234 return ERROR_OK;
2235 }
2236
2237 static int cortex_m_init_arch_info(struct target *target,
2238 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2239 {
2240 struct armv7m_common *armv7m = &cortex_m->armv7m;
2241
2242 armv7m_init_arch_info(target, armv7m);
2243
2244 /* default reset mode is to use srst if fitted
2245 * if not it will use CORTEX_M3_RESET_VECTRESET */
2246 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2247
2248 armv7m->arm.dap = dap;
2249
2250 /* register arch-specific functions */
2251 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2252
2253 armv7m->post_debug_entry = NULL;
2254
2255 armv7m->pre_restore_context = NULL;
2256
2257 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2258 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2259
2260 target_register_timer_callback(cortex_m_handle_target_request, 1,
2261 TARGET_TIMER_TYPE_PERIODIC, target);
2262
2263 return ERROR_OK;
2264 }
2265
2266 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2267 {
2268 struct adiv5_private_config *pc;
2269
2270 pc = (struct adiv5_private_config *)target->private_config;
2271 if (adiv5_verify_config(pc) != ERROR_OK)
2272 return ERROR_FAIL;
2273
2274 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2275 if (cortex_m == NULL) {
2276 LOG_ERROR("No memory creating target");
2277 return ERROR_FAIL;
2278 }
2279
2280 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2281 cortex_m->apsel = pc->ap_num;
2282
2283 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2284
2285 return ERROR_OK;
2286 }
2287
2288 /*--------------------------------------------------------------------------*/
2289
2290 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2291 struct cortex_m_common *cm)
2292 {
2293 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2294 command_print(cmd, "target is not a Cortex-M");
2295 return ERROR_TARGET_INVALID;
2296 }
2297 return ERROR_OK;
2298 }
2299
2300 /*
2301 * Only stuff below this line should need to verify that its target
2302 * is a Cortex-M3. Everything else should have indirected through the
2303 * cortexm3_target structure, which is only used with CM3 targets.
2304 */
2305
2306 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2307 {
2308 struct target *target = get_current_target(CMD_CTX);
2309 struct cortex_m_common *cortex_m = target_to_cm(target);
2310 struct armv7m_common *armv7m = &cortex_m->armv7m;
2311 uint32_t demcr = 0;
2312 int retval;
2313
2314 static const struct {
2315 char name[10];
2316 unsigned mask;
2317 } vec_ids[] = {
2318 { "hard_err", VC_HARDERR, },
2319 { "int_err", VC_INTERR, },
2320 { "bus_err", VC_BUSERR, },
2321 { "state_err", VC_STATERR, },
2322 { "chk_err", VC_CHKERR, },
2323 { "nocp_err", VC_NOCPERR, },
2324 { "mm_err", VC_MMERR, },
2325 { "reset", VC_CORERESET, },
2326 };
2327
2328 retval = cortex_m_verify_pointer(CMD, cortex_m);
2329 if (retval != ERROR_OK)
2330 return retval;
2331
2332 if (!target_was_examined(target)) {
2333 LOG_ERROR("Target not examined yet");
2334 return ERROR_FAIL;
2335 }
2336
2337 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2338 if (retval != ERROR_OK)
2339 return retval;
2340
2341 if (CMD_ARGC > 0) {
2342 unsigned catch = 0;
2343
2344 if (CMD_ARGC == 1) {
2345 if (strcmp(CMD_ARGV[0], "all") == 0) {
2346 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2347 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2348 | VC_MMERR | VC_CORERESET;
2349 goto write;
2350 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2351 goto write;
2352 }
2353 while (CMD_ARGC-- > 0) {
2354 unsigned i;
2355 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2356 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2357 continue;
2358 catch |= vec_ids[i].mask;
2359 break;
2360 }
2361 if (i == ARRAY_SIZE(vec_ids)) {
2362 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2363 return ERROR_COMMAND_SYNTAX_ERROR;
2364 }
2365 }
2366 write:
2367 /* For now, armv7m->demcr only stores vector catch flags. */
2368 armv7m->demcr = catch;
2369
2370 demcr &= ~0xffff;
2371 demcr |= catch;
2372
2373 /* write, but don't assume it stuck (why not??) */
2374 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2375 if (retval != ERROR_OK)
2376 return retval;
2377 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2378 if (retval != ERROR_OK)
2379 return retval;
2380
2381 /* FIXME be sure to clear DEMCR on clean server shutdown.
2382 * Otherwise the vector catch hardware could fire when there's
2383 * no debugger hooked up, causing much confusion...
2384 */
2385 }
2386
2387 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2388 command_print(CMD, "%9s: %s", vec_ids[i].name,
2389 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2390 }
2391
2392 return ERROR_OK;
2393 }
2394
2395 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2396 {
2397 struct target *target = get_current_target(CMD_CTX);
2398 struct cortex_m_common *cortex_m = target_to_cm(target);
2399 int retval;
2400
2401 static const struct jim_nvp nvp_maskisr_modes[] = {
2402 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2403 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2404 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2405 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2406 { .name = NULL, .value = -1 },
2407 };
2408 const struct jim_nvp *n;
2409
2410
2411 retval = cortex_m_verify_pointer(CMD, cortex_m);
2412 if (retval != ERROR_OK)
2413 return retval;
2414
2415 if (target->state != TARGET_HALTED) {
2416 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2417 return ERROR_OK;
2418 }
2419
2420 if (CMD_ARGC > 0) {
2421 n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2422 if (n->name == NULL)
2423 return ERROR_COMMAND_SYNTAX_ERROR;
2424 cortex_m->isrmasking_mode = n->value;
2425 cortex_m_set_maskints_for_halt(target);
2426 }
2427
2428 n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2429 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2430
2431 return ERROR_OK;
2432 }
2433
2434 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2435 {
2436 struct target *target = get_current_target(CMD_CTX);
2437 struct cortex_m_common *cortex_m = target_to_cm(target);
2438 int retval;
2439 char *reset_config;
2440
2441 retval = cortex_m_verify_pointer(CMD, cortex_m);
2442 if (retval != ERROR_OK)
2443 return retval;
2444
2445 if (CMD_ARGC > 0) {
2446 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2447 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2448
2449 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2450 if (target_was_examined(target)
2451 && !cortex_m->vectreset_supported)
2452 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2453 else
2454 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2455
2456 } else
2457 return ERROR_COMMAND_SYNTAX_ERROR;
2458 }
2459
2460 switch (cortex_m->soft_reset_config) {
2461 case CORTEX_M_RESET_SYSRESETREQ:
2462 reset_config = "sysresetreq";
2463 break;
2464
2465 case CORTEX_M_RESET_VECTRESET:
2466 reset_config = "vectreset";
2467 break;
2468
2469 default:
2470 reset_config = "unknown";
2471 break;
2472 }
2473
2474 command_print(CMD, "cortex_m reset_config %s", reset_config);
2475
2476 return ERROR_OK;
2477 }
2478
2479 static const struct command_registration cortex_m_exec_command_handlers[] = {
2480 {
2481 .name = "maskisr",
2482 .handler = handle_cortex_m_mask_interrupts_command,
2483 .mode = COMMAND_EXEC,
2484 .help = "mask cortex_m interrupts",
2485 .usage = "['auto'|'on'|'off'|'steponly']",
2486 },
2487 {
2488 .name = "vector_catch",
2489 .handler = handle_cortex_m_vector_catch_command,
2490 .mode = COMMAND_EXEC,
2491 .help = "configure hardware vectors to trigger debug entry",
2492 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2493 },
2494 {
2495 .name = "reset_config",
2496 .handler = handle_cortex_m_reset_config_command,
2497 .mode = COMMAND_ANY,
2498 .help = "configure software reset handling",
2499 .usage = "['sysresetreq'|'vectreset']",
2500 },
2501 COMMAND_REGISTRATION_DONE
2502 };
2503 static const struct command_registration cortex_m_command_handlers[] = {
2504 {
2505 .chain = armv7m_command_handlers,
2506 },
2507 {
2508 .chain = armv7m_trace_command_handlers,
2509 },
2510 /* START_DEPRECATED_TPIU */
2511 {
2512 .chain = arm_tpiu_deprecated_command_handlers,
2513 },
2514 /* END_DEPRECATED_TPIU */
2515 {
2516 .name = "cortex_m",
2517 .mode = COMMAND_EXEC,
2518 .help = "Cortex-M command group",
2519 .usage = "",
2520 .chain = cortex_m_exec_command_handlers,
2521 },
2522 {
2523 .chain = rtt_target_command_handlers,
2524 },
2525 COMMAND_REGISTRATION_DONE
2526 };
2527
2528 struct target_type cortexm_target = {
2529 .name = "cortex_m",
2530
2531 .poll = cortex_m_poll,
2532 .arch_state = armv7m_arch_state,
2533
2534 .target_request_data = cortex_m_target_request_data,
2535
2536 .halt = cortex_m_halt,
2537 .resume = cortex_m_resume,
2538 .step = cortex_m_step,
2539
2540 .assert_reset = cortex_m_assert_reset,
2541 .deassert_reset = cortex_m_deassert_reset,
2542 .soft_reset_halt = cortex_m_soft_reset_halt,
2543
2544 .get_gdb_arch = arm_get_gdb_arch,
2545 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2546
2547 .read_memory = cortex_m_read_memory,
2548 .write_memory = cortex_m_write_memory,
2549 .checksum_memory = armv7m_checksum_memory,
2550 .blank_check_memory = armv7m_blank_check_memory,
2551
2552 .run_algorithm = armv7m_run_algorithm,
2553 .start_algorithm = armv7m_start_algorithm,
2554 .wait_algorithm = armv7m_wait_algorithm,
2555
2556 .add_breakpoint = cortex_m_add_breakpoint,
2557 .remove_breakpoint = cortex_m_remove_breakpoint,
2558 .add_watchpoint = cortex_m_add_watchpoint,
2559 .remove_watchpoint = cortex_m_remove_watchpoint,
2560 .hit_watchpoint = cortex_m_hit_watchpoint,
2561
2562 .commands = cortex_m_command_handlers,
2563 .target_create = cortex_m_target_create,
2564 .target_jim_configure = adiv5_jim_configure,
2565 .init_target = cortex_m_init_target,
2566 .examine = cortex_m_examine,
2567 .deinit_target = cortex_m_deinit_target,
2568
2569 .profiling = cortex_m_profiling,
2570 };
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