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cortex_m: mark FPU register as non-existent instead of playing with num_regs
[openocd.git] / src / target / cortex_m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42 #include <rtt/rtt.h>
43
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FPB remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
49 *
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
52 * any longer.
53 */
54
55 /* forward declarations */
56 static int cortex_m_store_core_reg_u32(struct target *target,
57 uint32_t num, uint32_t value);
58 static void cortex_m_dwt_free(struct target *target);
59
60 static int cortex_m_load_core_reg_u32(struct target *target,
61 uint32_t regsel, uint32_t *value)
62 {
63 struct armv7m_common *armv7m = target_to_armv7m(target);
64 int retval;
65 uint32_t dcrdr;
66
67 /* because the DCB_DCRDR is used for the emulated dcc channel
68 * we have to save/restore the DCB_DCRDR when used */
69 if (target->dbg_msg_enabled) {
70 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
71 if (retval != ERROR_OK)
72 return retval;
73 }
74
75 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
76 if (retval != ERROR_OK)
77 return retval;
78
79 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
80 if (retval != ERROR_OK)
81 return retval;
82
83 if (target->dbg_msg_enabled) {
84 /* restore DCB_DCRDR - this needs to be in a separate
85 * transaction otherwise the emulated DCC channel breaks */
86 if (retval == ERROR_OK)
87 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
88 }
89
90 return retval;
91 }
92
93 static int cortex_m_store_core_reg_u32(struct target *target,
94 uint32_t regsel, uint32_t value)
95 {
96 struct armv7m_common *armv7m = target_to_armv7m(target);
97 int retval;
98 uint32_t dcrdr;
99
100 /* because the DCB_DCRDR is used for the emulated dcc channel
101 * we have to save/restore the DCB_DCRDR when used */
102 if (target->dbg_msg_enabled) {
103 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
104 if (retval != ERROR_OK)
105 return retval;
106 }
107
108 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
109 if (retval != ERROR_OK)
110 return retval;
111
112 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
113 if (retval != ERROR_OK)
114 return retval;
115
116 if (target->dbg_msg_enabled) {
117 /* restore DCB_DCRDR - this needs to be in a separate
118 * transaction otherwise the emulated DCC channel breaks */
119 if (retval == ERROR_OK)
120 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
121 }
122
123 return retval;
124 }
125
126 static int cortex_m_write_debug_halt_mask(struct target *target,
127 uint32_t mask_on, uint32_t mask_off)
128 {
129 struct cortex_m_common *cortex_m = target_to_cm(target);
130 struct armv7m_common *armv7m = &cortex_m->armv7m;
131
132 /* mask off status bits */
133 cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
134 /* create new register mask */
135 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
136
137 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
138 }
139
140 static int cortex_m_set_maskints(struct target *target, bool mask)
141 {
142 struct cortex_m_common *cortex_m = target_to_cm(target);
143 if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
144 return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
145 else
146 return ERROR_OK;
147 }
148
149 static int cortex_m_set_maskints_for_halt(struct target *target)
150 {
151 struct cortex_m_common *cortex_m = target_to_cm(target);
152 switch (cortex_m->isrmasking_mode) {
153 case CORTEX_M_ISRMASK_AUTO:
154 /* interrupts taken at resume, whether for step or run -> no mask */
155 return cortex_m_set_maskints(target, false);
156
157 case CORTEX_M_ISRMASK_OFF:
158 /* interrupts never masked */
159 return cortex_m_set_maskints(target, false);
160
161 case CORTEX_M_ISRMASK_ON:
162 /* interrupts always masked */
163 return cortex_m_set_maskints(target, true);
164
165 case CORTEX_M_ISRMASK_STEPONLY:
166 /* interrupts masked for single step only -> mask now if MASKINTS
167 * erratum, otherwise only mask before stepping */
168 return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
169 }
170 return ERROR_OK;
171 }
172
173 static int cortex_m_set_maskints_for_run(struct target *target)
174 {
175 switch (target_to_cm(target)->isrmasking_mode) {
176 case CORTEX_M_ISRMASK_AUTO:
177 /* interrupts taken at resume, whether for step or run -> no mask */
178 return cortex_m_set_maskints(target, false);
179
180 case CORTEX_M_ISRMASK_OFF:
181 /* interrupts never masked */
182 return cortex_m_set_maskints(target, false);
183
184 case CORTEX_M_ISRMASK_ON:
185 /* interrupts always masked */
186 return cortex_m_set_maskints(target, true);
187
188 case CORTEX_M_ISRMASK_STEPONLY:
189 /* interrupts masked for single step only -> no mask */
190 return cortex_m_set_maskints(target, false);
191 }
192 return ERROR_OK;
193 }
194
195 static int cortex_m_set_maskints_for_step(struct target *target)
196 {
197 switch (target_to_cm(target)->isrmasking_mode) {
198 case CORTEX_M_ISRMASK_AUTO:
199 /* the auto-interrupt should already be done -> mask */
200 return cortex_m_set_maskints(target, true);
201
202 case CORTEX_M_ISRMASK_OFF:
203 /* interrupts never masked */
204 return cortex_m_set_maskints(target, false);
205
206 case CORTEX_M_ISRMASK_ON:
207 /* interrupts always masked */
208 return cortex_m_set_maskints(target, true);
209
210 case CORTEX_M_ISRMASK_STEPONLY:
211 /* interrupts masked for single step only -> mask */
212 return cortex_m_set_maskints(target, true);
213 }
214 return ERROR_OK;
215 }
216
217 static int cortex_m_clear_halt(struct target *target)
218 {
219 struct cortex_m_common *cortex_m = target_to_cm(target);
220 struct armv7m_common *armv7m = &cortex_m->armv7m;
221 int retval;
222
223 /* clear step if any */
224 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
225
226 /* Read Debug Fault Status Register */
227 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
228 if (retval != ERROR_OK)
229 return retval;
230
231 /* Clear Debug Fault Status */
232 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
233 if (retval != ERROR_OK)
234 return retval;
235 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
236
237 return ERROR_OK;
238 }
239
240 static int cortex_m_single_step_core(struct target *target)
241 {
242 struct cortex_m_common *cortex_m = target_to_cm(target);
243 struct armv7m_common *armv7m = &cortex_m->armv7m;
244 int retval;
245
246 /* Mask interrupts before clearing halt, if not done already. This avoids
247 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
248 * HALT can put the core into an unknown state.
249 */
250 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
251 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
252 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
253 if (retval != ERROR_OK)
254 return retval;
255 }
256 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
257 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
258 if (retval != ERROR_OK)
259 return retval;
260 LOG_DEBUG(" ");
261
262 /* restore dhcsr reg */
263 cortex_m_clear_halt(target);
264
265 return ERROR_OK;
266 }
267
268 static int cortex_m_enable_fpb(struct target *target)
269 {
270 int retval = target_write_u32(target, FP_CTRL, 3);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* check the fpb is actually enabled */
275 uint32_t fpctrl;
276 retval = target_read_u32(target, FP_CTRL, &fpctrl);
277 if (retval != ERROR_OK)
278 return retval;
279
280 if (fpctrl & 1)
281 return ERROR_OK;
282
283 return ERROR_FAIL;
284 }
285
286 static int cortex_m_endreset_event(struct target *target)
287 {
288 int i;
289 int retval;
290 uint32_t dcb_demcr;
291 struct cortex_m_common *cortex_m = target_to_cm(target);
292 struct armv7m_common *armv7m = &cortex_m->armv7m;
293 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
294 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
295 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
296
297 /* REVISIT The four debug monitor bits are currently ignored... */
298 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
299 if (retval != ERROR_OK)
300 return retval;
301 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
302
303 /* this register is used for emulated dcc channel */
304 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* Enable debug requests */
309 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
310 if (retval != ERROR_OK)
311 return retval;
312 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
313 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
314 if (retval != ERROR_OK)
315 return retval;
316 }
317
318 /* Restore proper interrupt masking setting for running CPU. */
319 cortex_m_set_maskints_for_run(target);
320
321 /* Enable features controlled by ITM and DWT blocks, and catch only
322 * the vectors we were told to pay attention to.
323 *
324 * Target firmware is responsible for all fault handling policy
325 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
326 * or manual updates to the NVIC SHCSR and CCR registers.
327 */
328 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
329 if (retval != ERROR_OK)
330 return retval;
331
332 /* Paranoia: evidently some (early?) chips don't preserve all the
333 * debug state (including FPB, DWT, etc) across reset...
334 */
335
336 /* Enable FPB */
337 retval = cortex_m_enable_fpb(target);
338 if (retval != ERROR_OK) {
339 LOG_ERROR("Failed to enable the FPB");
340 return retval;
341 }
342
343 cortex_m->fpb_enabled = true;
344
345 /* Restore FPB registers */
346 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
347 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
348 if (retval != ERROR_OK)
349 return retval;
350 }
351
352 /* Restore DWT registers */
353 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
354 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
355 dwt_list[i].comp);
356 if (retval != ERROR_OK)
357 return retval;
358 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
359 dwt_list[i].mask);
360 if (retval != ERROR_OK)
361 return retval;
362 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
363 dwt_list[i].function);
364 if (retval != ERROR_OK)
365 return retval;
366 }
367 retval = dap_run(swjdp);
368 if (retval != ERROR_OK)
369 return retval;
370
371 register_cache_invalidate(armv7m->arm.core_cache);
372
373 /* make sure we have latest dhcsr flags */
374 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
375
376 return retval;
377 }
378
379 static int cortex_m_examine_debug_reason(struct target *target)
380 {
381 struct cortex_m_common *cortex_m = target_to_cm(target);
382
383 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
384 * only check the debug reason if we don't know it already */
385
386 if ((target->debug_reason != DBG_REASON_DBGRQ)
387 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
388 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
389 target->debug_reason = DBG_REASON_BREAKPOINT;
390 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
391 target->debug_reason = DBG_REASON_WPTANDBKPT;
392 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
393 target->debug_reason = DBG_REASON_WATCHPOINT;
394 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
395 target->debug_reason = DBG_REASON_BREAKPOINT;
396 else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
397 target->debug_reason = DBG_REASON_DBGRQ;
398 else /* HALTED */
399 target->debug_reason = DBG_REASON_UNDEFINED;
400 }
401
402 return ERROR_OK;
403 }
404
405 static int cortex_m_examine_exception_reason(struct target *target)
406 {
407 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
408 struct armv7m_common *armv7m = target_to_armv7m(target);
409 struct adiv5_dap *swjdp = armv7m->arm.dap;
410 int retval;
411
412 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
413 if (retval != ERROR_OK)
414 return retval;
415 switch (armv7m->exception_number) {
416 case 2: /* NMI */
417 break;
418 case 3: /* Hard Fault */
419 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
420 if (retval != ERROR_OK)
421 return retval;
422 if (except_sr & 0x40000000) {
423 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
424 if (retval != ERROR_OK)
425 return retval;
426 }
427 break;
428 case 4: /* Memory Management */
429 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
430 if (retval != ERROR_OK)
431 return retval;
432 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
433 if (retval != ERROR_OK)
434 return retval;
435 break;
436 case 5: /* Bus Fault */
437 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
438 if (retval != ERROR_OK)
439 return retval;
440 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
441 if (retval != ERROR_OK)
442 return retval;
443 break;
444 case 6: /* Usage Fault */
445 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
446 if (retval != ERROR_OK)
447 return retval;
448 break;
449 case 7: /* Secure Fault */
450 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
451 if (retval != ERROR_OK)
452 return retval;
453 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
454 if (retval != ERROR_OK)
455 return retval;
456 break;
457 case 11: /* SVCall */
458 break;
459 case 12: /* Debug Monitor */
460 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
461 if (retval != ERROR_OK)
462 return retval;
463 break;
464 case 14: /* PendSV */
465 break;
466 case 15: /* SysTick */
467 break;
468 default:
469 except_sr = 0;
470 break;
471 }
472 retval = dap_run(swjdp);
473 if (retval == ERROR_OK)
474 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
475 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
476 armv7m_exception_string(armv7m->exception_number),
477 shcsr, except_sr, cfsr, except_ar);
478 return retval;
479 }
480
481 static int cortex_m_debug_entry(struct target *target)
482 {
483 int i;
484 uint32_t xPSR;
485 int retval;
486 struct cortex_m_common *cortex_m = target_to_cm(target);
487 struct armv7m_common *armv7m = &cortex_m->armv7m;
488 struct arm *arm = &armv7m->arm;
489 struct reg *r;
490
491 LOG_DEBUG(" ");
492
493 /* Do this really early to minimize the window where the MASKINTS erratum
494 * can pile up pending interrupts. */
495 cortex_m_set_maskints_for_halt(target);
496
497 cortex_m_clear_halt(target);
498 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
499 if (retval != ERROR_OK)
500 return retval;
501
502 retval = armv7m->examine_debug_reason(target);
503 if (retval != ERROR_OK)
504 return retval;
505
506 /* examine PE security state */
507 bool secure_state = false;
508 if (armv7m->arm.is_armv8m) {
509 uint32_t dscsr;
510
511 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
512 if (retval != ERROR_OK)
513 return retval;
514
515 secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
516 }
517
518 /* Examine target state and mode
519 * First load register accessible through core debug port */
520 int num_regs = arm->core_cache->num_regs;
521
522 for (i = 0; i < num_regs; i++) {
523 r = &armv7m->arm.core_cache->reg_list[i];
524 if (r->exist && !r->valid)
525 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
526 }
527
528 r = arm->cpsr;
529 xPSR = buf_get_u32(r->value, 0, 32);
530
531 /* Are we in an exception handler */
532 if (xPSR & 0x1FF) {
533 armv7m->exception_number = (xPSR & 0x1FF);
534
535 arm->core_mode = ARM_MODE_HANDLER;
536 arm->map = armv7m_msp_reg_map;
537 } else {
538 unsigned control = buf_get_u32(arm->core_cache
539 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
540
541 /* is this thread privileged? */
542 arm->core_mode = control & 1
543 ? ARM_MODE_USER_THREAD
544 : ARM_MODE_THREAD;
545
546 /* which stack is it using? */
547 if (control & 2)
548 arm->map = armv7m_psp_reg_map;
549 else
550 arm->map = armv7m_msp_reg_map;
551
552 armv7m->exception_number = 0;
553 }
554
555 if (armv7m->exception_number)
556 cortex_m_examine_exception_reason(target);
557
558 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
559 arm_mode_name(arm->core_mode),
560 buf_get_u32(arm->pc->value, 0, 32),
561 secure_state ? "Secure" : "Non-Secure",
562 target_state_name(target));
563
564 if (armv7m->post_debug_entry) {
565 retval = armv7m->post_debug_entry(target);
566 if (retval != ERROR_OK)
567 return retval;
568 }
569
570 return ERROR_OK;
571 }
572
573 static int cortex_m_poll(struct target *target)
574 {
575 int detected_failure = ERROR_OK;
576 int retval = ERROR_OK;
577 enum target_state prev_target_state = target->state;
578 struct cortex_m_common *cortex_m = target_to_cm(target);
579 struct armv7m_common *armv7m = &cortex_m->armv7m;
580
581 /* Read from Debug Halting Control and Status Register */
582 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
583 if (retval != ERROR_OK) {
584 target->state = TARGET_UNKNOWN;
585 return retval;
586 }
587
588 /* Recover from lockup. See ARMv7-M architecture spec,
589 * section B1.5.15 "Unrecoverable exception cases".
590 */
591 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
592 LOG_ERROR("%s -- clearing lockup after double fault",
593 target_name(target));
594 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
595 target->debug_reason = DBG_REASON_DBGRQ;
596
597 /* We have to execute the rest (the "finally" equivalent, but
598 * still throw this exception again).
599 */
600 detected_failure = ERROR_FAIL;
601
602 /* refresh status bits */
603 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
604 if (retval != ERROR_OK)
605 return retval;
606 }
607
608 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
609 if (target->state != TARGET_RESET) {
610 target->state = TARGET_RESET;
611 LOG_INFO("%s: external reset detected", target_name(target));
612 }
613 return ERROR_OK;
614 }
615
616 if (target->state == TARGET_RESET) {
617 /* Cannot switch context while running so endreset is
618 * called with target->state == TARGET_RESET
619 */
620 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
621 cortex_m->dcb_dhcsr);
622 retval = cortex_m_endreset_event(target);
623 if (retval != ERROR_OK) {
624 target->state = TARGET_UNKNOWN;
625 return retval;
626 }
627 target->state = TARGET_RUNNING;
628 prev_target_state = TARGET_RUNNING;
629 }
630
631 if (cortex_m->dcb_dhcsr & S_HALT) {
632 target->state = TARGET_HALTED;
633
634 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
635 retval = cortex_m_debug_entry(target);
636 if (retval != ERROR_OK)
637 return retval;
638
639 if (arm_semihosting(target, &retval) != 0)
640 return retval;
641
642 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
643 }
644 if (prev_target_state == TARGET_DEBUG_RUNNING) {
645 LOG_DEBUG(" ");
646 retval = cortex_m_debug_entry(target);
647 if (retval != ERROR_OK)
648 return retval;
649
650 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
651 }
652 }
653
654 if (target->state == TARGET_UNKNOWN) {
655 /* check if processor is retiring instructions or sleeping */
656 if (cortex_m->dcb_dhcsr & S_RETIRE_ST || cortex_m->dcb_dhcsr & S_SLEEP) {
657 target->state = TARGET_RUNNING;
658 retval = ERROR_OK;
659 }
660 }
661
662 /* Check that target is truly halted, since the target could be resumed externally */
663 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
664 /* registers are now invalid */
665 register_cache_invalidate(armv7m->arm.core_cache);
666
667 target->state = TARGET_RUNNING;
668 LOG_WARNING("%s: external resume detected", target_name(target));
669 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
670 retval = ERROR_OK;
671 }
672
673 /* Did we detect a failure condition that we cleared? */
674 if (detected_failure != ERROR_OK)
675 retval = detected_failure;
676 return retval;
677 }
678
679 static int cortex_m_halt(struct target *target)
680 {
681 LOG_DEBUG("target->state: %s",
682 target_state_name(target));
683
684 if (target->state == TARGET_HALTED) {
685 LOG_DEBUG("target was already halted");
686 return ERROR_OK;
687 }
688
689 if (target->state == TARGET_UNKNOWN)
690 LOG_WARNING("target was in unknown state when halt was requested");
691
692 if (target->state == TARGET_RESET) {
693 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
694 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
695 return ERROR_TARGET_FAILURE;
696 } else {
697 /* we came here in a reset_halt or reset_init sequence
698 * debug entry was already prepared in cortex_m3_assert_reset()
699 */
700 target->debug_reason = DBG_REASON_DBGRQ;
701
702 return ERROR_OK;
703 }
704 }
705
706 /* Write to Debug Halting Control and Status Register */
707 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
708
709 /* Do this really early to minimize the window where the MASKINTS erratum
710 * can pile up pending interrupts. */
711 cortex_m_set_maskints_for_halt(target);
712
713 target->debug_reason = DBG_REASON_DBGRQ;
714
715 return ERROR_OK;
716 }
717
718 static int cortex_m_soft_reset_halt(struct target *target)
719 {
720 struct cortex_m_common *cortex_m = target_to_cm(target);
721 struct armv7m_common *armv7m = &cortex_m->armv7m;
722 uint32_t dcb_dhcsr = 0;
723 int retval, timeout = 0;
724
725 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
726 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
727 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
728 * core, not the peripherals */
729 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
730
731 /* Set C_DEBUGEN */
732 retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
733 if (retval != ERROR_OK)
734 return retval;
735
736 /* Enter debug state on reset; restore DEMCR in endreset_event() */
737 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
738 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
739 if (retval != ERROR_OK)
740 return retval;
741
742 /* Request a core-only reset */
743 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
744 AIRCR_VECTKEY | AIRCR_VECTRESET);
745 if (retval != ERROR_OK)
746 return retval;
747 target->state = TARGET_RESET;
748
749 /* registers are now invalid */
750 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
751
752 while (timeout < 100) {
753 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
754 if (retval == ERROR_OK) {
755 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
756 &cortex_m->nvic_dfsr);
757 if (retval != ERROR_OK)
758 return retval;
759 if ((dcb_dhcsr & S_HALT)
760 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
761 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
762 "DFSR 0x%08x",
763 (unsigned) dcb_dhcsr,
764 (unsigned) cortex_m->nvic_dfsr);
765 cortex_m_poll(target);
766 /* FIXME restore user's vector catch config */
767 return ERROR_OK;
768 } else
769 LOG_DEBUG("waiting for system reset-halt, "
770 "DHCSR 0x%08x, %d ms",
771 (unsigned) dcb_dhcsr, timeout);
772 }
773 timeout++;
774 alive_sleep(1);
775 }
776
777 return ERROR_OK;
778 }
779
780 void cortex_m_enable_breakpoints(struct target *target)
781 {
782 struct breakpoint *breakpoint = target->breakpoints;
783
784 /* set any pending breakpoints */
785 while (breakpoint) {
786 if (!breakpoint->set)
787 cortex_m_set_breakpoint(target, breakpoint);
788 breakpoint = breakpoint->next;
789 }
790 }
791
792 static int cortex_m_resume(struct target *target, int current,
793 target_addr_t address, int handle_breakpoints, int debug_execution)
794 {
795 struct armv7m_common *armv7m = target_to_armv7m(target);
796 struct breakpoint *breakpoint = NULL;
797 uint32_t resume_pc;
798 struct reg *r;
799
800 if (target->state != TARGET_HALTED) {
801 LOG_WARNING("target not halted");
802 return ERROR_TARGET_NOT_HALTED;
803 }
804
805 if (!debug_execution) {
806 target_free_all_working_areas(target);
807 cortex_m_enable_breakpoints(target);
808 cortex_m_enable_watchpoints(target);
809 }
810
811 if (debug_execution) {
812 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
813
814 /* Disable interrupts */
815 /* We disable interrupts in the PRIMASK register instead of
816 * masking with C_MASKINTS. This is probably the same issue
817 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
818 * in parallel with disabled interrupts can cause local faults
819 * to not be taken.
820 *
821 * This breaks non-debug (application) execution if not
822 * called from armv7m_start_algorithm() which saves registers.
823 */
824 buf_set_u32(r->value, 0, 1, 1);
825 r->dirty = true;
826 r->valid = true;
827
828 /* Make sure we are in Thumb mode, set xPSR.T bit */
829 /* armv7m_start_algorithm() initializes entire xPSR register.
830 * This duplicity handles the case when cortex_m_resume()
831 * is used with the debug_execution flag directly,
832 * not called through armv7m_start_algorithm().
833 */
834 r = armv7m->arm.cpsr;
835 buf_set_u32(r->value, 24, 1, 1);
836 r->dirty = true;
837 r->valid = true;
838 }
839
840 /* current = 1: continue on current pc, otherwise continue at <address> */
841 r = armv7m->arm.pc;
842 if (!current) {
843 buf_set_u32(r->value, 0, 32, address);
844 r->dirty = true;
845 r->valid = true;
846 }
847
848 /* if we halted last time due to a bkpt instruction
849 * then we have to manually step over it, otherwise
850 * the core will break again */
851
852 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
853 && !debug_execution)
854 armv7m_maybe_skip_bkpt_inst(target, NULL);
855
856 resume_pc = buf_get_u32(r->value, 0, 32);
857
858 armv7m_restore_context(target);
859
860 /* the front-end may request us not to handle breakpoints */
861 if (handle_breakpoints) {
862 /* Single step past breakpoint at current address */
863 breakpoint = breakpoint_find(target, resume_pc);
864 if (breakpoint) {
865 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
866 breakpoint->address,
867 breakpoint->unique_id);
868 cortex_m_unset_breakpoint(target, breakpoint);
869 cortex_m_single_step_core(target);
870 cortex_m_set_breakpoint(target, breakpoint);
871 }
872 }
873
874 /* Restart core */
875 cortex_m_set_maskints_for_run(target);
876 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
877
878 target->debug_reason = DBG_REASON_NOTHALTED;
879
880 /* registers are now invalid */
881 register_cache_invalidate(armv7m->arm.core_cache);
882
883 if (!debug_execution) {
884 target->state = TARGET_RUNNING;
885 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
886 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
887 } else {
888 target->state = TARGET_DEBUG_RUNNING;
889 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
890 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
891 }
892
893 return ERROR_OK;
894 }
895
896 /* int irqstepcount = 0; */
897 static int cortex_m_step(struct target *target, int current,
898 target_addr_t address, int handle_breakpoints)
899 {
900 struct cortex_m_common *cortex_m = target_to_cm(target);
901 struct armv7m_common *armv7m = &cortex_m->armv7m;
902 struct breakpoint *breakpoint = NULL;
903 struct reg *pc = armv7m->arm.pc;
904 bool bkpt_inst_found = false;
905 int retval;
906 bool isr_timed_out = false;
907
908 if (target->state != TARGET_HALTED) {
909 LOG_WARNING("target not halted");
910 return ERROR_TARGET_NOT_HALTED;
911 }
912
913 /* current = 1: continue on current pc, otherwise continue at <address> */
914 if (!current)
915 buf_set_u32(pc->value, 0, 32, address);
916
917 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
918
919 /* the front-end may request us not to handle breakpoints */
920 if (handle_breakpoints) {
921 breakpoint = breakpoint_find(target, pc_value);
922 if (breakpoint)
923 cortex_m_unset_breakpoint(target, breakpoint);
924 }
925
926 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
927
928 target->debug_reason = DBG_REASON_SINGLESTEP;
929
930 armv7m_restore_context(target);
931
932 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
933
934 /* if no bkpt instruction is found at pc then we can perform
935 * a normal step, otherwise we have to manually step over the bkpt
936 * instruction - as such simulate a step */
937 if (bkpt_inst_found == false) {
938 if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
939 /* Automatic ISR masking mode off: Just step over the next
940 * instruction, with interrupts on or off as appropriate. */
941 cortex_m_set_maskints_for_step(target);
942 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
943 } else {
944 /* Process interrupts during stepping in a way they don't interfere
945 * debugging.
946 *
947 * Principle:
948 *
949 * Set a temporary break point at the current pc and let the core run
950 * with interrupts enabled. Pending interrupts get served and we run
951 * into the breakpoint again afterwards. Then we step over the next
952 * instruction with interrupts disabled.
953 *
954 * If the pending interrupts don't complete within time, we leave the
955 * core running. This may happen if the interrupts trigger faster
956 * than the core can process them or the handler doesn't return.
957 *
958 * If no more breakpoints are available we simply do a step with
959 * interrupts enabled.
960 *
961 */
962
963 /* 2012-09-29 ph
964 *
965 * If a break point is already set on the lower half word then a break point on
966 * the upper half word will not break again when the core is restarted. So we
967 * just step over the instruction with interrupts disabled.
968 *
969 * The documentation has no information about this, it was found by observation
970 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
971 * suffer from this problem.
972 *
973 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
974 * address has it always cleared. The former is done to indicate thumb mode
975 * to gdb.
976 *
977 */
978 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
979 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
980 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
981 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
982 /* Re-enable interrupts if appropriate */
983 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
984 cortex_m_set_maskints_for_halt(target);
985 } else {
986
987 /* Set a temporary break point */
988 if (breakpoint) {
989 retval = cortex_m_set_breakpoint(target, breakpoint);
990 } else {
991 enum breakpoint_type type = BKPT_HARD;
992 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
993 /* FPB rev.1 cannot handle such addr, try BKPT instr */
994 type = BKPT_SOFT;
995 }
996 retval = breakpoint_add(target, pc_value, 2, type);
997 }
998
999 bool tmp_bp_set = (retval == ERROR_OK);
1000
1001 /* No more breakpoints left, just do a step */
1002 if (!tmp_bp_set) {
1003 cortex_m_set_maskints_for_step(target);
1004 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1005 /* Re-enable interrupts if appropriate */
1006 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1007 cortex_m_set_maskints_for_halt(target);
1008 } else {
1009 /* Start the core */
1010 LOG_DEBUG("Starting core to serve pending interrupts");
1011 int64_t t_start = timeval_ms();
1012 cortex_m_set_maskints_for_run(target);
1013 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
1014
1015 /* Wait for pending handlers to complete or timeout */
1016 do {
1017 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
1018 DCB_DHCSR,
1019 &cortex_m->dcb_dhcsr);
1020 if (retval != ERROR_OK) {
1021 target->state = TARGET_UNKNOWN;
1022 return retval;
1023 }
1024 isr_timed_out = ((timeval_ms() - t_start) > 500);
1025 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
1026
1027 /* only remove breakpoint if we created it */
1028 if (breakpoint)
1029 cortex_m_unset_breakpoint(target, breakpoint);
1030 else {
1031 /* Remove the temporary breakpoint */
1032 breakpoint_remove(target, pc_value);
1033 }
1034
1035 if (isr_timed_out) {
1036 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1037 "leaving target running");
1038 } else {
1039 /* Step over next instruction with interrupts disabled */
1040 cortex_m_set_maskints_for_step(target);
1041 cortex_m_write_debug_halt_mask(target,
1042 C_HALT | C_MASKINTS,
1043 0);
1044 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
1045 /* Re-enable interrupts if appropriate */
1046 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1047 cortex_m_set_maskints_for_halt(target);
1048 }
1049 }
1050 }
1051 }
1052 }
1053
1054 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1055 if (retval != ERROR_OK)
1056 return retval;
1057
1058 /* registers are now invalid */
1059 register_cache_invalidate(armv7m->arm.core_cache);
1060
1061 if (breakpoint)
1062 cortex_m_set_breakpoint(target, breakpoint);
1063
1064 if (isr_timed_out) {
1065 /* Leave the core running. The user has to stop execution manually. */
1066 target->debug_reason = DBG_REASON_NOTHALTED;
1067 target->state = TARGET_RUNNING;
1068 return ERROR_OK;
1069 }
1070
1071 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1072 " nvic_icsr = 0x%" PRIx32,
1073 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1074
1075 retval = cortex_m_debug_entry(target);
1076 if (retval != ERROR_OK)
1077 return retval;
1078 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1079
1080 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1081 " nvic_icsr = 0x%" PRIx32,
1082 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
1083
1084 return ERROR_OK;
1085 }
1086
1087 static int cortex_m_assert_reset(struct target *target)
1088 {
1089 struct cortex_m_common *cortex_m = target_to_cm(target);
1090 struct armv7m_common *armv7m = &cortex_m->armv7m;
1091 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
1092
1093 LOG_DEBUG("target->state: %s",
1094 target_state_name(target));
1095
1096 enum reset_types jtag_reset_config = jtag_get_reset_config();
1097
1098 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1099 /* allow scripts to override the reset event */
1100
1101 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1102 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1103 target->state = TARGET_RESET;
1104
1105 return ERROR_OK;
1106 }
1107
1108 /* some cores support connecting while srst is asserted
1109 * use that mode is it has been configured */
1110
1111 bool srst_asserted = false;
1112
1113 if (!target_was_examined(target)) {
1114 if (jtag_reset_config & RESET_HAS_SRST) {
1115 adapter_assert_reset();
1116 if (target->reset_halt)
1117 LOG_ERROR("Target not examined, will not halt after reset!");
1118 return ERROR_OK;
1119 } else {
1120 LOG_ERROR("Target not examined, reset NOT asserted!");
1121 return ERROR_FAIL;
1122 }
1123 }
1124
1125 if ((jtag_reset_config & RESET_HAS_SRST) &&
1126 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1127 adapter_assert_reset();
1128 srst_asserted = true;
1129 }
1130
1131 /* Enable debug requests */
1132 int retval;
1133 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1134 /* Store important errors instead of failing and proceed to reset assert */
1135
1136 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1137 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1138
1139 /* If the processor is sleeping in a WFI or WFE instruction, the
1140 * C_HALT bit must be asserted to regain control */
1141 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1142 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1143
1144 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1145 /* Ignore less important errors */
1146
1147 if (!target->reset_halt) {
1148 /* Set/Clear C_MASKINTS in a separate operation */
1149 cortex_m_set_maskints_for_run(target);
1150
1151 /* clear any debug flags before resuming */
1152 cortex_m_clear_halt(target);
1153
1154 /* clear C_HALT in dhcsr reg */
1155 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1156 } else {
1157 /* Halt in debug on reset; endreset_event() restores DEMCR.
1158 *
1159 * REVISIT catching BUSERR presumably helps to defend against
1160 * bad vector table entries. Should this include MMERR or
1161 * other flags too?
1162 */
1163 int retval2;
1164 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1165 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1166 if (retval != ERROR_OK || retval2 != ERROR_OK)
1167 LOG_INFO("AP write error, reset will not halt");
1168 }
1169
1170 if (jtag_reset_config & RESET_HAS_SRST) {
1171 /* default to asserting srst */
1172 if (!srst_asserted)
1173 adapter_assert_reset();
1174
1175 /* srst is asserted, ignore AP access errors */
1176 retval = ERROR_OK;
1177 } else {
1178 /* Use a standard Cortex-M3 software reset mechanism.
1179 * We default to using VECRESET as it is supported on all current cores
1180 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1181 * This has the disadvantage of not resetting the peripherals, so a
1182 * reset-init event handler is needed to perform any peripheral resets.
1183 */
1184 if (!cortex_m->vectreset_supported
1185 && reset_config == CORTEX_M_RESET_VECTRESET) {
1186 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1187 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1188 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1189 }
1190
1191 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1192 ? "SYSRESETREQ" : "VECTRESET");
1193
1194 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1195 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1196 "handler to reset any peripherals or configure hardware srst support.");
1197 }
1198
1199 int retval3;
1200 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1201 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1202 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1203 if (retval3 != ERROR_OK)
1204 LOG_DEBUG("Ignoring AP write error right after reset");
1205
1206 retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1207 if (retval3 != ERROR_OK) {
1208 LOG_ERROR("DP initialisation failed");
1209 /* The error return value must not be propagated in this case.
1210 * SYSRESETREQ or VECTRESET have been possibly triggered
1211 * so reset processing should continue */
1212 } else {
1213 /* I do not know why this is necessary, but it
1214 * fixes strange effects (step/resume cause NMI
1215 * after reset) on LM3S6918 -- Michael Schwingen
1216 */
1217 uint32_t tmp;
1218 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1219 }
1220 }
1221
1222 target->state = TARGET_RESET;
1223 jtag_sleep(50000);
1224
1225 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1226
1227 /* now return stored error code if any */
1228 if (retval != ERROR_OK)
1229 return retval;
1230
1231 if (target->reset_halt) {
1232 retval = target_halt(target);
1233 if (retval != ERROR_OK)
1234 return retval;
1235 }
1236
1237 return ERROR_OK;
1238 }
1239
1240 static int cortex_m_deassert_reset(struct target *target)
1241 {
1242 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1243
1244 LOG_DEBUG("target->state: %s",
1245 target_state_name(target));
1246
1247 /* deassert reset lines */
1248 adapter_deassert_reset();
1249
1250 enum reset_types jtag_reset_config = jtag_get_reset_config();
1251
1252 if ((jtag_reset_config & RESET_HAS_SRST) &&
1253 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1254 target_was_examined(target)) {
1255
1256 int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
1257 if (retval != ERROR_OK) {
1258 LOG_ERROR("DP initialisation failed");
1259 return retval;
1260 }
1261 }
1262
1263 return ERROR_OK;
1264 }
1265
1266 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1267 {
1268 int retval;
1269 int fp_num = 0;
1270 struct cortex_m_common *cortex_m = target_to_cm(target);
1271 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1272
1273 if (breakpoint->set) {
1274 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1275 return ERROR_OK;
1276 }
1277
1278 if (breakpoint->type == BKPT_HARD) {
1279 uint32_t fpcr_value;
1280 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1281 fp_num++;
1282 if (fp_num >= cortex_m->fp_num_code) {
1283 LOG_ERROR("Can not find free FPB Comparator!");
1284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1285 }
1286 breakpoint->set = fp_num + 1;
1287 fpcr_value = breakpoint->address | 1;
1288 if (cortex_m->fp_rev == 0) {
1289 if (breakpoint->address > 0x1FFFFFFF) {
1290 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1291 return ERROR_FAIL;
1292 }
1293 uint32_t hilo;
1294 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1295 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1296 } else if (cortex_m->fp_rev > 1) {
1297 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1298 return ERROR_FAIL;
1299 }
1300 comparator_list[fp_num].used = true;
1301 comparator_list[fp_num].fpcr_value = fpcr_value;
1302 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1303 comparator_list[fp_num].fpcr_value);
1304 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1305 fp_num,
1306 comparator_list[fp_num].fpcr_value);
1307 if (!cortex_m->fpb_enabled) {
1308 LOG_DEBUG("FPB wasn't enabled, do it now");
1309 retval = cortex_m_enable_fpb(target);
1310 if (retval != ERROR_OK) {
1311 LOG_ERROR("Failed to enable the FPB");
1312 return retval;
1313 }
1314
1315 cortex_m->fpb_enabled = true;
1316 }
1317 } else if (breakpoint->type == BKPT_SOFT) {
1318 uint8_t code[4];
1319
1320 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1321 * semihosting; don't use that. Otherwise the BKPT
1322 * parameter is arbitrary.
1323 */
1324 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1325 retval = target_read_memory(target,
1326 breakpoint->address & 0xFFFFFFFE,
1327 breakpoint->length, 1,
1328 breakpoint->orig_instr);
1329 if (retval != ERROR_OK)
1330 return retval;
1331 retval = target_write_memory(target,
1332 breakpoint->address & 0xFFFFFFFE,
1333 breakpoint->length, 1,
1334 code);
1335 if (retval != ERROR_OK)
1336 return retval;
1337 breakpoint->set = true;
1338 }
1339
1340 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1341 breakpoint->unique_id,
1342 (int)(breakpoint->type),
1343 breakpoint->address,
1344 breakpoint->length,
1345 breakpoint->set);
1346
1347 return ERROR_OK;
1348 }
1349
1350 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1351 {
1352 int retval;
1353 struct cortex_m_common *cortex_m = target_to_cm(target);
1354 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1355
1356 if (!breakpoint->set) {
1357 LOG_WARNING("breakpoint not set");
1358 return ERROR_OK;
1359 }
1360
1361 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1362 breakpoint->unique_id,
1363 (int)(breakpoint->type),
1364 breakpoint->address,
1365 breakpoint->length,
1366 breakpoint->set);
1367
1368 if (breakpoint->type == BKPT_HARD) {
1369 int fp_num = breakpoint->set - 1;
1370 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1371 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1372 return ERROR_OK;
1373 }
1374 comparator_list[fp_num].used = false;
1375 comparator_list[fp_num].fpcr_value = 0;
1376 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1377 comparator_list[fp_num].fpcr_value);
1378 } else {
1379 /* restore original instruction (kept in target endianness) */
1380 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
1381 breakpoint->length, 1,
1382 breakpoint->orig_instr);
1383 if (retval != ERROR_OK)
1384 return retval;
1385 }
1386 breakpoint->set = false;
1387
1388 return ERROR_OK;
1389 }
1390
1391 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1392 {
1393 if (breakpoint->length == 3) {
1394 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1395 breakpoint->length = 2;
1396 }
1397
1398 if ((breakpoint->length != 2)) {
1399 LOG_INFO("only breakpoints of two bytes length supported");
1400 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1401 }
1402
1403 return cortex_m_set_breakpoint(target, breakpoint);
1404 }
1405
1406 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1407 {
1408 if (!breakpoint->set)
1409 return ERROR_OK;
1410
1411 return cortex_m_unset_breakpoint(target, breakpoint);
1412 }
1413
1414 static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1415 {
1416 int dwt_num = 0;
1417 struct cortex_m_common *cortex_m = target_to_cm(target);
1418
1419 /* REVISIT Don't fully trust these "not used" records ... users
1420 * may set up breakpoints by hand, e.g. dual-address data value
1421 * watchpoint using comparator #1; comparator #0 matching cycle
1422 * count; send data trace info through ITM and TPIU; etc
1423 */
1424 struct cortex_m_dwt_comparator *comparator;
1425
1426 for (comparator = cortex_m->dwt_comparator_list;
1427 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1428 comparator++, dwt_num++)
1429 continue;
1430 if (dwt_num >= cortex_m->dwt_num_comp) {
1431 LOG_ERROR("Can not find free DWT Comparator");
1432 return ERROR_FAIL;
1433 }
1434 comparator->used = true;
1435 watchpoint->set = dwt_num + 1;
1436
1437 comparator->comp = watchpoint->address;
1438 target_write_u32(target, comparator->dwt_comparator_address + 0,
1439 comparator->comp);
1440
1441 if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
1442 uint32_t mask = 0, temp;
1443
1444 /* watchpoint params were validated earlier */
1445 temp = watchpoint->length;
1446 while (temp) {
1447 temp >>= 1;
1448 mask++;
1449 }
1450 mask--;
1451
1452 comparator->mask = mask;
1453 target_write_u32(target, comparator->dwt_comparator_address + 4,
1454 comparator->mask);
1455
1456 switch (watchpoint->rw) {
1457 case WPT_READ:
1458 comparator->function = 5;
1459 break;
1460 case WPT_WRITE:
1461 comparator->function = 6;
1462 break;
1463 case WPT_ACCESS:
1464 comparator->function = 7;
1465 break;
1466 }
1467 } else {
1468 uint32_t data_size = watchpoint->length >> 1;
1469 comparator->mask = (watchpoint->length >> 1) | 1;
1470
1471 switch (watchpoint->rw) {
1472 case WPT_ACCESS:
1473 comparator->function = 4;
1474 break;
1475 case WPT_WRITE:
1476 comparator->function = 5;
1477 break;
1478 case WPT_READ:
1479 comparator->function = 6;
1480 break;
1481 }
1482 comparator->function = comparator->function | (1 << 4) |
1483 (data_size << 10);
1484 }
1485
1486 target_write_u32(target, comparator->dwt_comparator_address + 8,
1487 comparator->function);
1488
1489 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1490 watchpoint->unique_id, dwt_num,
1491 (unsigned) comparator->comp,
1492 (unsigned) comparator->mask,
1493 (unsigned) comparator->function);
1494 return ERROR_OK;
1495 }
1496
1497 static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1498 {
1499 struct cortex_m_common *cortex_m = target_to_cm(target);
1500 struct cortex_m_dwt_comparator *comparator;
1501 int dwt_num;
1502
1503 if (!watchpoint->set) {
1504 LOG_WARNING("watchpoint (wpid: %d) not set",
1505 watchpoint->unique_id);
1506 return ERROR_OK;
1507 }
1508
1509 dwt_num = watchpoint->set - 1;
1510
1511 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1512 watchpoint->unique_id, dwt_num,
1513 (unsigned) watchpoint->address);
1514
1515 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1516 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1517 return ERROR_OK;
1518 }
1519
1520 comparator = cortex_m->dwt_comparator_list + dwt_num;
1521 comparator->used = false;
1522 comparator->function = 0;
1523 target_write_u32(target, comparator->dwt_comparator_address + 8,
1524 comparator->function);
1525
1526 watchpoint->set = false;
1527
1528 return ERROR_OK;
1529 }
1530
1531 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1532 {
1533 struct cortex_m_common *cortex_m = target_to_cm(target);
1534
1535 if (cortex_m->dwt_comp_available < 1) {
1536 LOG_DEBUG("no comparators?");
1537 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1538 }
1539
1540 /* hardware doesn't support data value masking */
1541 if (watchpoint->mask != ~(uint32_t)0) {
1542 LOG_DEBUG("watchpoint value masks not supported");
1543 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1544 }
1545
1546 /* hardware allows address masks of up to 32K */
1547 unsigned mask;
1548
1549 for (mask = 0; mask < 16; mask++) {
1550 if ((1u << mask) == watchpoint->length)
1551 break;
1552 }
1553 if (mask == 16) {
1554 LOG_DEBUG("unsupported watchpoint length");
1555 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1556 }
1557 if (watchpoint->address & ((1 << mask) - 1)) {
1558 LOG_DEBUG("watchpoint address is unaligned");
1559 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1560 }
1561
1562 /* Caller doesn't seem to be able to describe watching for data
1563 * values of zero; that flags "no value".
1564 *
1565 * REVISIT This DWT may well be able to watch for specific data
1566 * values. Requires comparator #1 to set DATAVMATCH and match
1567 * the data, and another comparator (DATAVADDR0) matching addr.
1568 */
1569 if (watchpoint->value) {
1570 LOG_DEBUG("data value watchpoint not YET supported");
1571 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1572 }
1573
1574 cortex_m->dwt_comp_available--;
1575 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1576
1577 return ERROR_OK;
1578 }
1579
1580 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1581 {
1582 struct cortex_m_common *cortex_m = target_to_cm(target);
1583
1584 /* REVISIT why check? DWT can be updated with core running ... */
1585 if (target->state != TARGET_HALTED) {
1586 LOG_WARNING("target not halted");
1587 return ERROR_TARGET_NOT_HALTED;
1588 }
1589
1590 if (watchpoint->set)
1591 cortex_m_unset_watchpoint(target, watchpoint);
1592
1593 cortex_m->dwt_comp_available++;
1594 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1595
1596 return ERROR_OK;
1597 }
1598
1599 void cortex_m_enable_watchpoints(struct target *target)
1600 {
1601 struct watchpoint *watchpoint = target->watchpoints;
1602
1603 /* set any pending watchpoints */
1604 while (watchpoint) {
1605 if (!watchpoint->set)
1606 cortex_m_set_watchpoint(target, watchpoint);
1607 watchpoint = watchpoint->next;
1608 }
1609 }
1610
1611 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1612 uint32_t size, uint32_t count, uint8_t *buffer)
1613 {
1614 struct armv7m_common *armv7m = target_to_armv7m(target);
1615
1616 if (armv7m->arm.is_armv6m) {
1617 /* armv6m does not handle unaligned memory access */
1618 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1619 return ERROR_TARGET_UNALIGNED_ACCESS;
1620 }
1621
1622 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1623 }
1624
1625 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1626 uint32_t size, uint32_t count, const uint8_t *buffer)
1627 {
1628 struct armv7m_common *armv7m = target_to_armv7m(target);
1629
1630 if (armv7m->arm.is_armv6m) {
1631 /* armv6m does not handle unaligned memory access */
1632 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1633 return ERROR_TARGET_UNALIGNED_ACCESS;
1634 }
1635
1636 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1637 }
1638
1639 static int cortex_m_init_target(struct command_context *cmd_ctx,
1640 struct target *target)
1641 {
1642 armv7m_build_reg_cache(target);
1643 arm_semihosting_init(target);
1644 return ERROR_OK;
1645 }
1646
1647 void cortex_m_deinit_target(struct target *target)
1648 {
1649 struct cortex_m_common *cortex_m = target_to_cm(target);
1650
1651 free(cortex_m->fp_comparator_list);
1652
1653 cortex_m_dwt_free(target);
1654 armv7m_free_reg_cache(target);
1655
1656 free(target->private_config);
1657 free(cortex_m);
1658 }
1659
1660 int cortex_m_profiling(struct target *target, uint32_t *samples,
1661 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1662 {
1663 struct timeval timeout, now;
1664 struct armv7m_common *armv7m = target_to_armv7m(target);
1665 uint32_t reg_value;
1666 int retval;
1667
1668 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1669 if (retval != ERROR_OK) {
1670 LOG_ERROR("Error while reading PCSR");
1671 return retval;
1672 }
1673 if (reg_value == 0) {
1674 LOG_INFO("PCSR sampling not supported on this processor.");
1675 return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
1676 }
1677
1678 gettimeofday(&timeout, NULL);
1679 timeval_add_time(&timeout, seconds, 0);
1680
1681 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1682
1683 /* Make sure the target is running */
1684 target_poll(target);
1685 if (target->state == TARGET_HALTED)
1686 retval = target_resume(target, 1, 0, 0, 0);
1687
1688 if (retval != ERROR_OK) {
1689 LOG_ERROR("Error while resuming target");
1690 return retval;
1691 }
1692
1693 uint32_t sample_count = 0;
1694
1695 for (;;) {
1696 if (armv7m && armv7m->debug_ap) {
1697 uint32_t read_count = max_num_samples - sample_count;
1698 if (read_count > 1024)
1699 read_count = 1024;
1700
1701 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1702 (void *)&samples[sample_count],
1703 4, read_count, DWT_PCSR);
1704 sample_count += read_count;
1705 } else {
1706 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1707 }
1708
1709 if (retval != ERROR_OK) {
1710 LOG_ERROR("Error while reading PCSR");
1711 return retval;
1712 }
1713
1714
1715 gettimeofday(&now, NULL);
1716 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1717 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1718 break;
1719 }
1720 }
1721
1722 *num_samples = sample_count;
1723 return retval;
1724 }
1725
1726
1727 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1728 * on r/w if the core is not running, and clear on resume or reset ... or
1729 * at least, in a post_restore_context() method.
1730 */
1731
1732 struct dwt_reg_state {
1733 struct target *target;
1734 uint32_t addr;
1735 uint8_t value[4]; /* scratch/cache */
1736 };
1737
1738 static int cortex_m_dwt_get_reg(struct reg *reg)
1739 {
1740 struct dwt_reg_state *state = reg->arch_info;
1741
1742 uint32_t tmp;
1743 int retval = target_read_u32(state->target, state->addr, &tmp);
1744 if (retval != ERROR_OK)
1745 return retval;
1746
1747 buf_set_u32(state->value, 0, 32, tmp);
1748 return ERROR_OK;
1749 }
1750
1751 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1752 {
1753 struct dwt_reg_state *state = reg->arch_info;
1754
1755 return target_write_u32(state->target, state->addr,
1756 buf_get_u32(buf, 0, reg->size));
1757 }
1758
1759 struct dwt_reg {
1760 uint32_t addr;
1761 const char *name;
1762 unsigned size;
1763 };
1764
1765 static const struct dwt_reg dwt_base_regs[] = {
1766 { DWT_CTRL, "dwt_ctrl", 32, },
1767 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1768 * increments while the core is asleep.
1769 */
1770 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1771 /* plus some 8 bit counters, useful for profiling with TPIU */
1772 };
1773
1774 static const struct dwt_reg dwt_comp[] = {
1775 #define DWT_COMPARATOR(i) \
1776 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1777 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1778 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1779 DWT_COMPARATOR(0),
1780 DWT_COMPARATOR(1),
1781 DWT_COMPARATOR(2),
1782 DWT_COMPARATOR(3),
1783 DWT_COMPARATOR(4),
1784 DWT_COMPARATOR(5),
1785 DWT_COMPARATOR(6),
1786 DWT_COMPARATOR(7),
1787 DWT_COMPARATOR(8),
1788 DWT_COMPARATOR(9),
1789 DWT_COMPARATOR(10),
1790 DWT_COMPARATOR(11),
1791 DWT_COMPARATOR(12),
1792 DWT_COMPARATOR(13),
1793 DWT_COMPARATOR(14),
1794 DWT_COMPARATOR(15),
1795 #undef DWT_COMPARATOR
1796 };
1797
1798 static const struct reg_arch_type dwt_reg_type = {
1799 .get = cortex_m_dwt_get_reg,
1800 .set = cortex_m_dwt_set_reg,
1801 };
1802
1803 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1804 {
1805 struct dwt_reg_state *state;
1806
1807 state = calloc(1, sizeof(*state));
1808 if (!state)
1809 return;
1810 state->addr = d->addr;
1811 state->target = t;
1812
1813 r->name = d->name;
1814 r->size = d->size;
1815 r->value = state->value;
1816 r->arch_info = state;
1817 r->type = &dwt_reg_type;
1818 }
1819
1820 static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1821 {
1822 uint32_t dwtcr;
1823 struct reg_cache *cache;
1824 struct cortex_m_dwt_comparator *comparator;
1825 int reg, i;
1826
1827 target_read_u32(target, DWT_CTRL, &dwtcr);
1828 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1829 if (!dwtcr) {
1830 LOG_DEBUG("no DWT");
1831 return;
1832 }
1833
1834 target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
1835 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
1836
1837 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1838 cm->dwt_comp_available = cm->dwt_num_comp;
1839 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1840 sizeof(struct cortex_m_dwt_comparator));
1841 if (!cm->dwt_comparator_list) {
1842 fail0:
1843 cm->dwt_num_comp = 0;
1844 LOG_ERROR("out of mem");
1845 return;
1846 }
1847
1848 cache = calloc(1, sizeof(*cache));
1849 if (!cache) {
1850 fail1:
1851 free(cm->dwt_comparator_list);
1852 goto fail0;
1853 }
1854 cache->name = "Cortex-M DWT registers";
1855 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1856 cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
1857 if (!cache->reg_list) {
1858 free(cache);
1859 goto fail1;
1860 }
1861
1862 for (reg = 0; reg < 2; reg++)
1863 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1864 dwt_base_regs + reg);
1865
1866 comparator = cm->dwt_comparator_list;
1867 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1868 int j;
1869
1870 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1871 for (j = 0; j < 3; j++, reg++)
1872 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1873 dwt_comp + 3 * i + j);
1874
1875 /* make sure we clear any watchpoints enabled on the target */
1876 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1877 }
1878
1879 *register_get_last_cache_p(&target->reg_cache) = cache;
1880 cm->dwt_cache = cache;
1881
1882 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1883 dwtcr, cm->dwt_num_comp,
1884 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1885
1886 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1887 * implement single-address data value watchpoints ... so we
1888 * won't need to check it later, when asked to set one up.
1889 */
1890 }
1891
1892 static void cortex_m_dwt_free(struct target *target)
1893 {
1894 struct cortex_m_common *cm = target_to_cm(target);
1895 struct reg_cache *cache = cm->dwt_cache;
1896
1897 free(cm->dwt_comparator_list);
1898 cm->dwt_comparator_list = NULL;
1899 cm->dwt_num_comp = 0;
1900
1901 if (cache) {
1902 register_unlink_cache(&target->reg_cache, cache);
1903
1904 if (cache->reg_list) {
1905 for (size_t i = 0; i < cache->num_regs; i++)
1906 free(cache->reg_list[i].arch_info);
1907 free(cache->reg_list);
1908 }
1909 free(cache);
1910 }
1911 cm->dwt_cache = NULL;
1912 }
1913
1914 #define MVFR0 0xe000ef40
1915 #define MVFR1 0xe000ef44
1916
1917 #define MVFR0_DEFAULT_M4 0x10110021
1918 #define MVFR1_DEFAULT_M4 0x11000011
1919
1920 #define MVFR0_DEFAULT_M7_SP 0x10110021
1921 #define MVFR0_DEFAULT_M7_DP 0x10110221
1922 #define MVFR1_DEFAULT_M7_SP 0x11000011
1923 #define MVFR1_DEFAULT_M7_DP 0x12000011
1924
1925 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
1926 struct adiv5_ap **debug_ap)
1927 {
1928 if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
1929 return ERROR_OK;
1930
1931 return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
1932 }
1933
1934 int cortex_m_examine(struct target *target)
1935 {
1936 int retval;
1937 uint32_t cpuid, fpcr, mvfr0, mvfr1;
1938 int i;
1939 struct cortex_m_common *cortex_m = target_to_cm(target);
1940 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
1941 struct armv7m_common *armv7m = target_to_armv7m(target);
1942
1943 /* stlink shares the examine handler but does not support
1944 * all its calls */
1945 if (!armv7m->stlink) {
1946 if (cortex_m->apsel == DP_APSEL_INVALID) {
1947 /* Search for the MEM-AP */
1948 retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
1949 if (retval != ERROR_OK) {
1950 LOG_ERROR("Could not find MEM-AP to control the core");
1951 return retval;
1952 }
1953 } else {
1954 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
1955 }
1956
1957 /* Leave (only) generic DAP stuff for debugport_init(); */
1958 armv7m->debug_ap->memaccess_tck = 8;
1959
1960 retval = mem_ap_init(armv7m->debug_ap);
1961 if (retval != ERROR_OK)
1962 return retval;
1963 }
1964
1965 if (!target_was_examined(target)) {
1966 target_set_examined(target);
1967
1968 /* Read from Device Identification Registers */
1969 retval = target_read_u32(target, CPUID, &cpuid);
1970 if (retval != ERROR_OK)
1971 return retval;
1972
1973 /* Get CPU Type */
1974 i = (cpuid >> 4) & 0xf;
1975
1976 /* Check if it is an ARMv8-M core */
1977 armv7m->arm.is_armv8m = true;
1978
1979 switch (cpuid & ARM_CPUID_PARTNO_MASK) {
1980 case CORTEX_M23_PARTNO:
1981 i = 23;
1982 break;
1983 case CORTEX_M33_PARTNO:
1984 i = 33;
1985 break;
1986 case CORTEX_M35P_PARTNO:
1987 i = 35;
1988 break;
1989 case CORTEX_M55_PARTNO:
1990 i = 55;
1991 break;
1992 default:
1993 armv7m->arm.is_armv8m = false;
1994 break;
1995 }
1996
1997
1998 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
1999 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2000 cortex_m->maskints_erratum = false;
2001 if (i == 7) {
2002 uint8_t rev, patch;
2003 rev = (cpuid >> 20) & 0xf;
2004 patch = (cpuid >> 0) & 0xf;
2005 if ((rev == 0) && (patch < 2)) {
2006 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2007 cortex_m->maskints_erratum = true;
2008 }
2009 }
2010 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2011
2012 /* VECTRESET is supported only on ARMv7-M cores */
2013 cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
2014
2015 if (i == 4) {
2016 target_read_u32(target, MVFR0, &mvfr0);
2017 target_read_u32(target, MVFR1, &mvfr1);
2018
2019 /* test for floating point feature on Cortex-M4 */
2020 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2021 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2022 armv7m->fp_feature = FPV4_SP;
2023 }
2024 } else if (i == 7 || i == 33 || i == 35 || i == 55) {
2025 target_read_u32(target, MVFR0, &mvfr0);
2026 target_read_u32(target, MVFR1, &mvfr1);
2027
2028 /* test for floating point features on Cortex-M7 */
2029 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2030 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2031 armv7m->fp_feature = FPV5_SP;
2032 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2033 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2034 armv7m->fp_feature = FPV5_DP;
2035 }
2036 } else if (i == 0) {
2037 /* Cortex-M0 does not support unaligned memory access */
2038 armv7m->arm.is_armv6m = true;
2039 }
2040
2041 /* Check for FPU, otherwise mark FPU register as non-existent */
2042 if (armv7m->fp_feature == FP_NONE)
2043 for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++)
2044 armv7m->arm.core_cache->reg_list[idx].exist = false;
2045
2046
2047 if (!armv7m->stlink) {
2048 if (i == 3 || i == 4)
2049 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2050 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2051 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2052 else if (i == 7)
2053 /* Cortex-M7 has only 1024 bytes autoincrement range */
2054 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2055 }
2056
2057 /* Enable debug requests */
2058 retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
2059 if (retval != ERROR_OK)
2060 return retval;
2061 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
2062 uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
2063
2064 retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
2065 if (retval != ERROR_OK)
2066 return retval;
2067 cortex_m->dcb_dhcsr = dhcsr;
2068 }
2069
2070 /* Configure trace modules */
2071 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2072 if (retval != ERROR_OK)
2073 return retval;
2074
2075 if (armv7m->trace_config.itm_deferred_config)
2076 armv7m_trace_itm_config(target);
2077
2078 /* NOTE: FPB and DWT are both optional. */
2079
2080 /* Setup FPB */
2081 target_read_u32(target, FP_CTRL, &fpcr);
2082 /* bits [14:12] and [7:4] */
2083 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2084 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2085 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2086 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2087 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2088 free(cortex_m->fp_comparator_list);
2089 cortex_m->fp_comparator_list = calloc(
2090 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2091 sizeof(struct cortex_m_fp_comparator));
2092 cortex_m->fpb_enabled = fpcr & 1;
2093 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2094 cortex_m->fp_comparator_list[i].type =
2095 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2096 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2097
2098 /* make sure we clear any breakpoints enabled on the target */
2099 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2100 }
2101 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2102 fpcr,
2103 cortex_m->fp_num_code,
2104 cortex_m->fp_num_lit);
2105
2106 /* Setup DWT */
2107 cortex_m_dwt_free(target);
2108 cortex_m_dwt_setup(cortex_m, target);
2109
2110 /* These hardware breakpoints only work for code in flash! */
2111 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2112 target_name(target),
2113 cortex_m->fp_num_code,
2114 cortex_m->dwt_num_comp);
2115 }
2116
2117 return ERROR_OK;
2118 }
2119
2120 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2121 {
2122 struct armv7m_common *armv7m = target_to_armv7m(target);
2123 uint16_t dcrdr;
2124 uint8_t buf[2];
2125 int retval;
2126
2127 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2128 if (retval != ERROR_OK)
2129 return retval;
2130
2131 dcrdr = target_buffer_get_u16(target, buf);
2132 *ctrl = (uint8_t)dcrdr;
2133 *value = (uint8_t)(dcrdr >> 8);
2134
2135 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2136
2137 /* write ack back to software dcc register
2138 * signify we have read data */
2139 if (dcrdr & (1 << 0)) {
2140 target_buffer_set_u16(target, buf, 0);
2141 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2142 if (retval != ERROR_OK)
2143 return retval;
2144 }
2145
2146 return ERROR_OK;
2147 }
2148
2149 static int cortex_m_target_request_data(struct target *target,
2150 uint32_t size, uint8_t *buffer)
2151 {
2152 uint8_t data;
2153 uint8_t ctrl;
2154 uint32_t i;
2155
2156 for (i = 0; i < (size * 4); i++) {
2157 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2158 if (retval != ERROR_OK)
2159 return retval;
2160 buffer[i] = data;
2161 }
2162
2163 return ERROR_OK;
2164 }
2165
2166 static int cortex_m_handle_target_request(void *priv)
2167 {
2168 struct target *target = priv;
2169 if (!target_was_examined(target))
2170 return ERROR_OK;
2171
2172 if (!target->dbg_msg_enabled)
2173 return ERROR_OK;
2174
2175 if (target->state == TARGET_RUNNING) {
2176 uint8_t data;
2177 uint8_t ctrl;
2178 int retval;
2179
2180 retval = cortex_m_dcc_read(target, &data, &ctrl);
2181 if (retval != ERROR_OK)
2182 return retval;
2183
2184 /* check if we have data */
2185 if (ctrl & (1 << 0)) {
2186 uint32_t request;
2187
2188 /* we assume target is quick enough */
2189 request = data;
2190 for (int i = 1; i <= 3; i++) {
2191 retval = cortex_m_dcc_read(target, &data, &ctrl);
2192 if (retval != ERROR_OK)
2193 return retval;
2194 request |= ((uint32_t)data << (i * 8));
2195 }
2196 target_request(target, request);
2197 }
2198 }
2199
2200 return ERROR_OK;
2201 }
2202
2203 static int cortex_m_init_arch_info(struct target *target,
2204 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2205 {
2206 struct armv7m_common *armv7m = &cortex_m->armv7m;
2207
2208 armv7m_init_arch_info(target, armv7m);
2209
2210 /* default reset mode is to use srst if fitted
2211 * if not it will use CORTEX_M3_RESET_VECTRESET */
2212 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2213
2214 armv7m->arm.dap = dap;
2215
2216 /* register arch-specific functions */
2217 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2218
2219 armv7m->post_debug_entry = NULL;
2220
2221 armv7m->pre_restore_context = NULL;
2222
2223 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2224 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2225
2226 target_register_timer_callback(cortex_m_handle_target_request, 1,
2227 TARGET_TIMER_TYPE_PERIODIC, target);
2228
2229 return ERROR_OK;
2230 }
2231
2232 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2233 {
2234 struct adiv5_private_config *pc;
2235
2236 pc = (struct adiv5_private_config *)target->private_config;
2237 if (adiv5_verify_config(pc) != ERROR_OK)
2238 return ERROR_FAIL;
2239
2240 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2241 if (cortex_m == NULL) {
2242 LOG_ERROR("No memory creating target");
2243 return ERROR_FAIL;
2244 }
2245
2246 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2247 cortex_m->apsel = pc->ap_num;
2248
2249 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2250
2251 return ERROR_OK;
2252 }
2253
2254 /*--------------------------------------------------------------------------*/
2255
2256 static int cortex_m_verify_pointer(struct command_invocation *cmd,
2257 struct cortex_m_common *cm)
2258 {
2259 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2260 command_print(cmd, "target is not a Cortex-M");
2261 return ERROR_TARGET_INVALID;
2262 }
2263 return ERROR_OK;
2264 }
2265
2266 /*
2267 * Only stuff below this line should need to verify that its target
2268 * is a Cortex-M3. Everything else should have indirected through the
2269 * cortexm3_target structure, which is only used with CM3 targets.
2270 */
2271
2272 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2273 {
2274 struct target *target = get_current_target(CMD_CTX);
2275 struct cortex_m_common *cortex_m = target_to_cm(target);
2276 struct armv7m_common *armv7m = &cortex_m->armv7m;
2277 uint32_t demcr = 0;
2278 int retval;
2279
2280 static const struct {
2281 char name[10];
2282 unsigned mask;
2283 } vec_ids[] = {
2284 { "hard_err", VC_HARDERR, },
2285 { "int_err", VC_INTERR, },
2286 { "bus_err", VC_BUSERR, },
2287 { "state_err", VC_STATERR, },
2288 { "chk_err", VC_CHKERR, },
2289 { "nocp_err", VC_NOCPERR, },
2290 { "mm_err", VC_MMERR, },
2291 { "reset", VC_CORERESET, },
2292 };
2293
2294 retval = cortex_m_verify_pointer(CMD, cortex_m);
2295 if (retval != ERROR_OK)
2296 return retval;
2297
2298 if (!target_was_examined(target)) {
2299 LOG_ERROR("Target not examined yet");
2300 return ERROR_FAIL;
2301 }
2302
2303 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2304 if (retval != ERROR_OK)
2305 return retval;
2306
2307 if (CMD_ARGC > 0) {
2308 unsigned catch = 0;
2309
2310 if (CMD_ARGC == 1) {
2311 if (strcmp(CMD_ARGV[0], "all") == 0) {
2312 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2313 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2314 | VC_MMERR | VC_CORERESET;
2315 goto write;
2316 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2317 goto write;
2318 }
2319 while (CMD_ARGC-- > 0) {
2320 unsigned i;
2321 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2322 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2323 continue;
2324 catch |= vec_ids[i].mask;
2325 break;
2326 }
2327 if (i == ARRAY_SIZE(vec_ids)) {
2328 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2329 return ERROR_COMMAND_SYNTAX_ERROR;
2330 }
2331 }
2332 write:
2333 /* For now, armv7m->demcr only stores vector catch flags. */
2334 armv7m->demcr = catch;
2335
2336 demcr &= ~0xffff;
2337 demcr |= catch;
2338
2339 /* write, but don't assume it stuck (why not??) */
2340 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2341 if (retval != ERROR_OK)
2342 return retval;
2343 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2344 if (retval != ERROR_OK)
2345 return retval;
2346
2347 /* FIXME be sure to clear DEMCR on clean server shutdown.
2348 * Otherwise the vector catch hardware could fire when there's
2349 * no debugger hooked up, causing much confusion...
2350 */
2351 }
2352
2353 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2354 command_print(CMD, "%9s: %s", vec_ids[i].name,
2355 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2356 }
2357
2358 return ERROR_OK;
2359 }
2360
2361 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2362 {
2363 struct target *target = get_current_target(CMD_CTX);
2364 struct cortex_m_common *cortex_m = target_to_cm(target);
2365 int retval;
2366
2367 static const Jim_Nvp nvp_maskisr_modes[] = {
2368 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2369 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2370 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2371 { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
2372 { .name = NULL, .value = -1 },
2373 };
2374 const Jim_Nvp *n;
2375
2376
2377 retval = cortex_m_verify_pointer(CMD, cortex_m);
2378 if (retval != ERROR_OK)
2379 return retval;
2380
2381 if (target->state != TARGET_HALTED) {
2382 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
2383 return ERROR_OK;
2384 }
2385
2386 if (CMD_ARGC > 0) {
2387 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2388 if (n->name == NULL)
2389 return ERROR_COMMAND_SYNTAX_ERROR;
2390 cortex_m->isrmasking_mode = n->value;
2391 cortex_m_set_maskints_for_halt(target);
2392 }
2393
2394 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2395 command_print(CMD, "cortex_m interrupt mask %s", n->name);
2396
2397 return ERROR_OK;
2398 }
2399
2400 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2401 {
2402 struct target *target = get_current_target(CMD_CTX);
2403 struct cortex_m_common *cortex_m = target_to_cm(target);
2404 int retval;
2405 char *reset_config;
2406
2407 retval = cortex_m_verify_pointer(CMD, cortex_m);
2408 if (retval != ERROR_OK)
2409 return retval;
2410
2411 if (CMD_ARGC > 0) {
2412 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2413 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2414
2415 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2416 if (target_was_examined(target)
2417 && !cortex_m->vectreset_supported)
2418 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2419 else
2420 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2421
2422 } else
2423 return ERROR_COMMAND_SYNTAX_ERROR;
2424 }
2425
2426 switch (cortex_m->soft_reset_config) {
2427 case CORTEX_M_RESET_SYSRESETREQ:
2428 reset_config = "sysresetreq";
2429 break;
2430
2431 case CORTEX_M_RESET_VECTRESET:
2432 reset_config = "vectreset";
2433 break;
2434
2435 default:
2436 reset_config = "unknown";
2437 break;
2438 }
2439
2440 command_print(CMD, "cortex_m reset_config %s", reset_config);
2441
2442 return ERROR_OK;
2443 }
2444
2445 static const struct command_registration cortex_m_exec_command_handlers[] = {
2446 {
2447 .name = "maskisr",
2448 .handler = handle_cortex_m_mask_interrupts_command,
2449 .mode = COMMAND_EXEC,
2450 .help = "mask cortex_m interrupts",
2451 .usage = "['auto'|'on'|'off'|'steponly']",
2452 },
2453 {
2454 .name = "vector_catch",
2455 .handler = handle_cortex_m_vector_catch_command,
2456 .mode = COMMAND_EXEC,
2457 .help = "configure hardware vectors to trigger debug entry",
2458 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2459 },
2460 {
2461 .name = "reset_config",
2462 .handler = handle_cortex_m_reset_config_command,
2463 .mode = COMMAND_ANY,
2464 .help = "configure software reset handling",
2465 .usage = "['sysresetreq'|'vectreset']",
2466 },
2467 COMMAND_REGISTRATION_DONE
2468 };
2469 static const struct command_registration cortex_m_command_handlers[] = {
2470 {
2471 .chain = armv7m_command_handlers,
2472 },
2473 {
2474 .chain = armv7m_trace_command_handlers,
2475 },
2476 /* START_DEPRECATED_TPIU */
2477 {
2478 .chain = arm_tpiu_deprecated_command_handlers,
2479 },
2480 /* END_DEPRECATED_TPIU */
2481 {
2482 .name = "cortex_m",
2483 .mode = COMMAND_EXEC,
2484 .help = "Cortex-M command group",
2485 .usage = "",
2486 .chain = cortex_m_exec_command_handlers,
2487 },
2488 {
2489 .chain = rtt_target_command_handlers,
2490 },
2491 COMMAND_REGISTRATION_DONE
2492 };
2493
2494 struct target_type cortexm_target = {
2495 .name = "cortex_m",
2496
2497 .poll = cortex_m_poll,
2498 .arch_state = armv7m_arch_state,
2499
2500 .target_request_data = cortex_m_target_request_data,
2501
2502 .halt = cortex_m_halt,
2503 .resume = cortex_m_resume,
2504 .step = cortex_m_step,
2505
2506 .assert_reset = cortex_m_assert_reset,
2507 .deassert_reset = cortex_m_deassert_reset,
2508 .soft_reset_halt = cortex_m_soft_reset_halt,
2509
2510 .get_gdb_arch = arm_get_gdb_arch,
2511 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2512
2513 .read_memory = cortex_m_read_memory,
2514 .write_memory = cortex_m_write_memory,
2515 .checksum_memory = armv7m_checksum_memory,
2516 .blank_check_memory = armv7m_blank_check_memory,
2517
2518 .run_algorithm = armv7m_run_algorithm,
2519 .start_algorithm = armv7m_start_algorithm,
2520 .wait_algorithm = armv7m_wait_algorithm,
2521
2522 .add_breakpoint = cortex_m_add_breakpoint,
2523 .remove_breakpoint = cortex_m_remove_breakpoint,
2524 .add_watchpoint = cortex_m_add_watchpoint,
2525 .remove_watchpoint = cortex_m_remove_watchpoint,
2526
2527 .commands = cortex_m_command_handlers,
2528 .target_create = cortex_m_target_create,
2529 .target_jim_configure = adiv5_jim_configure,
2530 .init_target = cortex_m_init_target,
2531 .examine = cortex_m_examine,
2532 .deinit_target = cortex_m_deinit_target,
2533
2534 .profiling = cortex_m_profiling,
2535 };
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