src/target/cortex_m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifndef OPENOCD_TARGET_CORTEX_M_H
  26 #define OPENOCD_TARGET_CORTEX_M_H
  27
  28 #include "armv7m.h"
  29 #include "helper/bits.h"
  30
  31 #define CORTEX_M_COMMON_MAGIC 0x1A451A45
  32
  33 #define SYSTEM_CONTROL_BASE 0x400FE000
  34
  35 #define ITM_TER0        0xE0000E00
  36 #define ITM_TPR         0xE0000E40
  37 #define ITM_TCR         0xE0000E80
  38 #define ITM_TCR_ITMENA_BIT      BIT(0)
  39 #define ITM_TCR_BUSY_BIT        BIT(23)
  40 #define ITM_LAR         0xE0000FB0
  41 #define ITM_LAR_KEY     0xC5ACCE55
  42
  43 #define CPUID           0xE000ED00
  44
  45 #define ARM_CPUID_PARTNO_POS    4
  46 #define ARM_CPUID_PARTNO_MASK   (0xFFF << ARM_CPUID_PARTNO_POS)
  47
  48 enum cortex_m_partno {
  49         CORTEX_M0_PARTNO   = 0xC20,
  50         CORTEX_M1_PARTNO   = 0xC21,
  51         CORTEX_M3_PARTNO   = 0xC23,
  52         CORTEX_M4_PARTNO   = 0xC24,
  53         CORTEX_M7_PARTNO   = 0xC27,
  54         CORTEX_M0P_PARTNO  = 0xC60,
  55         CORTEX_M23_PARTNO  = 0xD20,
  56         CORTEX_M33_PARTNO  = 0xD21,
  57         CORTEX_M35P_PARTNO = 0xD31,
  58         CORTEX_M55_PARTNO  = 0xD22,
  59 };
  60
  61 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
  62 #define CORTEX_M_F_HAS_FPV4               BIT(0)
  63 #define CORTEX_M_F_HAS_FPV5               BIT(1)
  64 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K  BIT(2)
  65
  66 struct cortex_m_part_info {
  67         enum cortex_m_partno partno;
  68         const char *name;
  69         enum arm_arch arch;
  70         uint32_t flags;
  71 };
  72
  73 /* Debug Control Block */
  74 #define DCB_DHCSR       0xE000EDF0
  75 #define DCB_DCRSR       0xE000EDF4
  76 #define DCB_DCRDR       0xE000EDF8
  77 #define DCB_DEMCR       0xE000EDFC
  78 #define DCB_DSCSR       0xE000EE08
  79
  80 #define DCRSR_WNR       BIT(16)
  81
  82 #define DWT_CTRL        0xE0001000
  83 #define DWT_CYCCNT      0xE0001004
  84 #define DWT_PCSR        0xE000101C
  85 #define DWT_COMP0       0xE0001020
  86 #define DWT_MASK0       0xE0001024
  87 #define DWT_FUNCTION0   0xE0001028
  88 #define DWT_DEVARCH             0xE0001FBC
  89
  90 #define DWT_DEVARCH_ARMV8M      0x101A02
  91
  92 #define FP_CTRL         0xE0002000
  93 #define FP_REMAP        0xE0002004
  94 #define FP_COMP0        0xE0002008
  95 #define FP_COMP1        0xE000200C
  96 #define FP_COMP2        0xE0002010
  97 #define FP_COMP3        0xE0002014
  98 #define FP_COMP4        0xE0002018
  99 #define FP_COMP5        0xE000201C
 100 #define FP_COMP6        0xE0002020
 101 #define FP_COMP7        0xE0002024
 102
 103 #define FPU_CPACR       0xE000ED88
 104 #define FPU_FPCCR       0xE000EF34
 105 #define FPU_FPCAR       0xE000EF38
 106 #define FPU_FPDSCR      0xE000EF3C
 107
 108 #define TPIU_SSPSR      0xE0040000
 109 #define TPIU_CSPSR      0xE0040004
 110 #define TPIU_ACPR       0xE0040010
 111 #define TPIU_SPPR       0xE00400F0
 112 #define TPIU_FFSR       0xE0040300
 113 #define TPIU_FFCR       0xE0040304
 114 #define TPIU_FSCR       0xE0040308
 115
 116 /* Maximum SWO prescaler value. */
 117 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
 118
 119 /* DCB_DHCSR bit and field definitions */
 120 #define DBGKEY          (0xA05Ful << 16)
 121 #define C_DEBUGEN       BIT(0)
 122 #define C_HALT          BIT(1)
 123 #define C_STEP          BIT(2)
 124 #define C_MASKINTS      BIT(3)
 125 #define S_REGRDY        BIT(16)
 126 #define S_HALT          BIT(17)
 127 #define S_SLEEP         BIT(18)
 128 #define S_LOCKUP        BIT(19)
 129 #define S_RETIRE_ST     BIT(24)
 130 #define S_RESET_ST      BIT(25)
 131
 132 /* DCB_DEMCR bit and field definitions */
 133 #define TRCENA                  BIT(24)
 134 #define VC_HARDERR              BIT(10)
 135 #define VC_INTERR               BIT(9)
 136 #define VC_BUSERR               BIT(8)
 137 #define VC_STATERR              BIT(7)
 138 #define VC_CHKERR               BIT(6)
 139 #define VC_NOCPERR              BIT(5)
 140 #define VC_MMERR                BIT(4)
 141 #define VC_CORERESET    BIT(0)
 142
 143 /* DCB_DSCSR bit and field definitions */
 144 #define DSCSR_CDS               BIT(16)
 145
 146 /* NVIC registers */
 147 #define NVIC_ICTR               0xE000E004
 148 #define NVIC_ISE0               0xE000E100
 149 #define NVIC_ICSR               0xE000ED04
 150 #define NVIC_AIRCR              0xE000ED0C
 151 #define NVIC_SHCSR              0xE000ED24
 152 #define NVIC_CFSR               0xE000ED28
 153 #define NVIC_MMFSRB             0xE000ED28
 154 #define NVIC_BFSRB              0xE000ED29
 155 #define NVIC_USFSRH             0xE000ED2A
 156 #define NVIC_HFSR               0xE000ED2C
 157 #define NVIC_DFSR               0xE000ED30
 158 #define NVIC_MMFAR              0xE000ED34
 159 #define NVIC_BFAR               0xE000ED38
 160 #define NVIC_SFSR               0xE000EDE4
 161 #define NVIC_SFAR               0xE000EDE8
 162
 163 /* NVIC_AIRCR bits */
 164 #define AIRCR_VECTKEY           (0x5FAul << 16)
 165 #define AIRCR_SYSRESETREQ       BIT(2)
 166 #define AIRCR_VECTCLRACTIVE     BIT(1)
 167 #define AIRCR_VECTRESET         BIT(0)
 168 /* NVIC_SHCSR bits */
 169 #define SHCSR_BUSFAULTENA       BIT(17)
 170 /* NVIC_DFSR bits */
 171 #define DFSR_HALTED                     1
 172 #define DFSR_BKPT                       2
 173 #define DFSR_DWTTRAP            4
 174 #define DFSR_VCATCH                     8
 175 #define DFSR_EXTERNAL           16
 176
 177 #define FPCR_CODE 0
 178 #define FPCR_LITERAL 1
 179 #define FPCR_REPLACE_REMAP  (0ul << 30)
 180 #define FPCR_REPLACE_BKPT_LOW  (1ul << 30)
 181 #define FPCR_REPLACE_BKPT_HIGH  (2ul << 30)
 182 #define FPCR_REPLACE_BKPT_BOTH  (3ul << 30)
 183
 184 struct cortex_m_fp_comparator {
 185         bool used;
 186         int type;
 187         uint32_t fpcr_value;
 188         uint32_t fpcr_address;
 189 };
 190
 191 struct cortex_m_dwt_comparator {
 192         bool used;
 193         uint32_t comp;
 194         uint32_t mask;
 195         uint32_t function;
 196         uint32_t dwt_comparator_address;
 197 };
 198
 199 enum cortex_m_soft_reset_config {
 200         CORTEX_M_RESET_SYSRESETREQ,
 201         CORTEX_M_RESET_VECTRESET,
 202 };
 203
 204 enum cortex_m_isrmasking_mode {
 205         CORTEX_M_ISRMASK_AUTO,
 206         CORTEX_M_ISRMASK_OFF,
 207         CORTEX_M_ISRMASK_ON,
 208         CORTEX_M_ISRMASK_STEPONLY,
 209 };
 210
 211 struct cortex_m_common {
 212         int common_magic;
 213
 214         /* Context information */
 215         uint32_t dcb_dhcsr;
 216         uint32_t dcb_dhcsr_cumulated_sticky;
 217         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 218         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 219
 220         /* Flash Patch and Breakpoint (FPB) */
 221         unsigned int fp_num_lit;
 222         unsigned int fp_num_code;
 223         int fp_rev;
 224         bool fpb_enabled;
 225         struct cortex_m_fp_comparator *fp_comparator_list;
 226
 227         /* Data Watchpoint and Trace (DWT) */
 228         unsigned int dwt_num_comp;
 229         unsigned int dwt_comp_available;
 230         uint32_t dwt_devarch;
 231         struct cortex_m_dwt_comparator *dwt_comparator_list;
 232         struct reg_cache *dwt_cache;
 233
 234         enum cortex_m_soft_reset_config soft_reset_config;
 235         bool vectreset_supported;
 236         enum cortex_m_isrmasking_mode isrmasking_mode;
 237
 238         const struct cortex_m_part_info *core_info;
 239         struct armv7m_common armv7m;
 240
 241         bool slow_register_read;        /* A register has not been ready, poll S_REGRDY */
 242
 243         int apsel;
 244
 245         /* Whether this target has the erratum that makes C_MASKINTS not apply to
 246          * already pending interrupts */
 247         bool maskints_erratum;
 248 };
 249
 250 static inline struct cortex_m_common *
 251 target_to_cm(struct target *target)
 252 {
 253         return container_of(target->arch_info,
 254                         struct cortex_m_common, armv7m);
 255 }
 256
 257 int cortex_m_examine(struct target *target);
 258 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
 259 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 260 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 261 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
 262 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 263 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 264 void cortex_m_enable_breakpoints(struct target *target);
 265 void cortex_m_enable_watchpoints(struct target *target);
 266 void cortex_m_deinit_target(struct target *target);
 267 int cortex_m_profiling(struct target *target, uint32_t *samples,
 268         uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 269
 270 #endif /* OPENOCD_TARGET_CORTEX_M_H */