src/target/cortex_m3.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2006 by Magnus Lundin                                   *
   5  *   lundin@mlu.mine.nu                                                    *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifndef CORTEX_M3_H
  23 #define CORTEX_M3_H
  24
  25 #include "register.h"
  26 #include "target.h"
  27 #include "armv7m.h"
  28 #include "cortex_swjdp.h"
  29
  30 extern char* cortex_m3_state_strings[];
  31
  32 #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
  33
  34 #define SYSTEM_CONTROL_BASE 0x400FE000
  35
  36 #define CPUID           0xE000ED00
  37 /* Debug Control Block */
  38 #define DCB_DHCSR       0xE000EDF0
  39 #define DCB_DCRSR       0xE000EDF4
  40 #define DCB_DCRDR       0xE000EDF8
  41 #define DCB_DEMCR       0xE000EDFC
  42
  43 #define DCRSR_WnR       (1<<16)
  44
  45 #define DWT_CTRL        0xE0001000
  46 #define DWT_COMP0       0xE0001020
  47 #define DWT_MASK0       0xE0001024
  48 #define DWT_FUNCTION0   0xE0001028
  49
  50 #define FP_CTRL         0xE0002000
  51 #define FP_REMAP        0xE0002004
  52 #define FP_COMP0        0xE0002008
  53 #define FP_COMP1        0xE000200C
  54 #define FP_COMP2        0xE0002010
  55 #define FP_COMP3        0xE0002014
  56 #define FP_COMP4        0xE0002018
  57 #define FP_COMP5        0xE000201C
  58 #define FP_COMP6        0xE0002020
  59 #define FP_COMP7        0xE0002024
  60
  61 #define DWT_CTRL        0xE0001000
  62
  63 /* DCB_DHCSR bit and field definitions */
  64 #define DBGKEY          (0xA05F<<16)
  65 #define C_DEBUGEN       (1<<0)
  66 #define C_HALT          (1<<1)
  67 #define C_STEP          (1<<2)
  68 #define C_MASKINTS      (1<<3)
  69 #define S_REGRDY        (1<<16)
  70 #define S_HALT          (1<<17)
  71 #define S_SLEEP         (1<<18)
  72 #define S_LOCKUP        (1<<19)
  73 #define S_RETIRE_ST     (1<<24)
  74 #define S_RESET_ST      (1<<25)
  75
  76 /* DCB_DEMCR bit and field definitions */
  77 #define TRCENA                  (1<<24)
  78 #define VC_HARDERR              (1<<10)
  79 #define VC_BUSERR               (1<<8)
  80 #define VC_CORERESET    (1<<0)
  81
  82 #define NVIC_ICTR               0xE000E004
  83 #define NVIC_ISE0               0xE000E100
  84 #define NVIC_ICSR               0xE000ED04
  85 #define NVIC_AIRCR              0xE000ED0C
  86 #define NVIC_SHCSR              0xE000ED24
  87 #define NVIC_CFSR               0xE000ED28
  88 #define NVIC_MMFSRb             0xE000ED28
  89 #define NVIC_BFSRb              0xE000ED29
  90 #define NVIC_USFSRh             0xE000ED2A
  91 #define NVIC_HFSR               0xE000ED2C
  92 #define NVIC_DFSR               0xE000ED30
  93 #define NVIC_MMFAR              0xE000ED34
  94 #define NVIC_BFAR               0xE000ED38
  95
  96 /* NVIC_AIRCR bits */
  97 #define AIRCR_VECTKEY           (0x5FA<<16)
  98 #define AIRCR_SYSRESETREQ       (1<<2)
  99 #define AIRCR_VECTCLRACTIVE     (1<<1)
 100 #define AIRCR_VECTRESET         (1<<0)
 101 /* NVIC_SHCSR bits */
 102 #define SHCSR_BUSFAULTENA       (1<<17)
 103 /* NVIC_DFSR bits */
 104 #define DFSR_HALTED     1
 105 #define DFSR_BKPT       2
 106 #define DFSR_DWTTRAP    4
 107 #define DFSR_VCATCH     8
 108
 109 #define FPCR_CODE 0
 110 #define FPCR_LITERAL 1
 111 #define FPCR_REPLACE_REMAP  (0<<30)
 112 #define FPCR_REPLACE_BKPT_LOW  (1<<30)
 113 #define FPCR_REPLACE_BKPT_HIGH  (2<<30)
 114 #define FPCR_REPLACE_BKPT_BOTH  (3<<30)
 115
 116 typedef struct  cortex_m3_fp_comparator_s
 117 {
 118         int used;
 119         int type;
 120         u32 fpcr_value;
 121         u32 fpcr_address;
 122 } cortex_m3_fp_comparator_t;
 123
 124 typedef struct  cortex_m3_dwt_comparator_s
 125 {
 126         int used;
 127         u32 comp;
 128         u32 mask;
 129         u32 function;
 130         u32 dwt_comparator_address;
 131 } cortex_m3_dwt_comparator_t;
 132
 133 typedef struct cortex_m3_common_s
 134 {
 135         int common_magic;
 136 //      int (*full_context)(struct target_s *target);
 137
 138         arm_jtag_t jtag_info;
 139
 140         /* Context information */
 141         u32 dcb_dhcsr;
 142         u32 nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 143         u32 nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 144
 145         /* Flash Patch and Breakpoint */
 146         int fp_num_lit;
 147         int fp_num_code;
 148         int fp_code_available;
 149         int auto_bp_type;
 150         cortex_m3_fp_comparator_t *fp_comparator_list;
 151
 152         /* DWT */
 153         int dwt_num_comp;
 154         int dwt_comp_available;
 155         cortex_m3_dwt_comparator_t *dwt_comparator_list;
 156
 157         /* Interrupts */
 158         int intlinesnum;
 159         u32 *intsetenable;
 160
 161 /*
 162         u32 arm_bkpt;
 163         u16 thumb_bkpt;
 164         int sw_bkpts_use_wp;
 165         int wp_available;
 166         int wp0_used;
 167         int wp1_used;
 168
 169         int force_hw_bkpts;
 170         int dbgreq_adjust_pc;
 171         int use_dbgrq;
 172         int has_etm;
 173
 174         int reinit_embeddedice;
 175
 176         struct working_area_s *dcc_working_area;
 177
 178         int fast_memory_access;
 179         int dcc_downloads;
 180 */
 181         /* breakpoint use map */
 182         int sw_bkpts_enabled;
 183
 184         armv7m_common_t armv7m;
 185         swjdp_common_t swjdp_info;
 186
 187         void *arch_info;
 188 } cortex_m3_common_t;
 189
 190 extern void cortex_m3_build_reg_cache(target_t *target);
 191
 192 enum target_state cortex_m3_poll(target_t *target);
 193 int cortex_m3_halt(target_t *target);
 194 int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
 195 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
 196
 197 int cortex_m3_assert_reset(target_t *target);
 198 int cortex_m3_deassert_reset(target_t *target);
 199 int cortex_m3_soft_reset_halt(struct target_s *target);
 200 int cortex_m3_prepare_reset_halt(struct target_s *target);
 201
 202 int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 203 int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 204 int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
 205
 206 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 207 int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 208 int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 209 int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 210 int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 211 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 212
 213 extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
 214 extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant);
 215
 216 #endif /* CORTEX_M3_H */