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target/dsp563xx: review scope of symbols
[openocd.git] / src / target / dsp563xx.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <helper/jim.h>
25
26 #include "target.h"
27 #include "target_type.h"
28 #include "register.h"
29 #include "dsp563xx.h"
30 #include "dsp563xx_once.h"
31
32 #define DSP563XX_JTAG_INS_LEN 4
33
34 #define JTAG_STATUS_NORMAL 0x01
35 #define JTAG_STATUS_STOPWAIT 0x05
36 #define JTAG_STATUS_BUSY 0x09
37 #define JTAG_STATUS_DEBUG 0x0d
38
39 #define JTAG_INSTR_EXTEST 0x00
40 #define JTAG_INSTR_SAMPLE_PRELOAD 0x01
41 #define JTAG_INSTR_IDCODE 0x02
42 #define JTAG_INSTR_CLAMP 0x03
43 #define JTAG_INSTR_HIZ 0x04
44 #define JTAG_INSTR_ENABLE_ONCE 0x06
45 #define JTAG_INSTR_DEBUG_REQUEST 0x07
46 #define JTAG_INSTR_BYPASS 0x0F
47
48 /* forward declarations */
49 static int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
50 int ir_len, int rti);
51
52 /* IR and DR functions */
53 static int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out);
54 int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
55 int len);
56
57 #define ASM_REG_R_R0 0x607000
58 #define ASM_REG_R_R1 0x617000
59 #define ASM_REG_R_R2 0x627000
60 #define ASM_REG_R_R3 0x637000
61 #define ASM_REG_R_R4 0x647000
62 #define ASM_REG_R_R5 0x657000
63 #define ASM_REG_R_R6 0x667000
64 #define ASM_REG_R_R7 0x677000
65
66 #define ASM_REG_W_R0 0x60F400
67 #define ASM_REG_W_R1 0x61F400
68 #define ASM_REG_W_R2 0x62F400
69 #define ASM_REG_W_R3 0x63F400
70 #define ASM_REG_W_R4 0x64F400
71 #define ASM_REG_W_R5 0x65F400
72 #define ASM_REG_W_R6 0x66F400
73 #define ASM_REG_W_R7 0x67F400
74
75 #define ASM_REG_R_N0 0x707000
76 #define ASM_REG_R_N1 0x717000
77 #define ASM_REG_R_N2 0x727000
78 #define ASM_REG_R_N3 0x737000
79 #define ASM_REG_R_N4 0x747000
80 #define ASM_REG_R_N5 0x757000
81 #define ASM_REG_R_N6 0x767000
82 #define ASM_REG_R_N7 0x777000
83
84 #define ASM_REG_W_N0 0x70F400
85 #define ASM_REG_W_N1 0x71F400
86 #define ASM_REG_W_N2 0x72F400
87 #define ASM_REG_W_N3 0x73F400
88 #define ASM_REG_W_N4 0x74F400
89 #define ASM_REG_W_N5 0x75F400
90 #define ASM_REG_W_N6 0x76F400
91 #define ASM_REG_W_N7 0x77F400
92
93 #define ASM_REG_R_M0 0x057020 /* control register m[0..7] */
94 #define ASM_REG_R_M1 0x057021
95 #define ASM_REG_R_M2 0x057022
96 #define ASM_REG_R_M3 0x057023
97 #define ASM_REG_R_M4 0x057024
98 #define ASM_REG_R_M5 0x057025
99 #define ASM_REG_R_M6 0x057026
100 #define ASM_REG_R_M7 0x057027
101
102 #define ASM_REG_W_M0 0x05F420
103 #define ASM_REG_W_M1 0x05F421
104 #define ASM_REG_W_M2 0x05F422
105 #define ASM_REG_W_M3 0x05F423
106 #define ASM_REG_W_M4 0x05F424
107 #define ASM_REG_W_M5 0x05F425
108 #define ASM_REG_W_M6 0x05F426
109 #define ASM_REG_W_M7 0x05F427
110
111 #define ASM_REG_R_X0 0x447000
112 #define ASM_REG_R_X1 0x457000
113
114 #define ASM_REG_W_X0 0x44F400
115 #define ASM_REG_W_X1 0x45F400
116
117 #define ASM_REG_R_Y0 0x467000
118 #define ASM_REG_R_Y1 0x477000
119
120 #define ASM_REG_W_Y0 0x46F400
121 #define ASM_REG_W_Y1 0x47F400
122
123 #define ASM_REG_R_A0 0x507000
124 #define ASM_REG_R_A1 0x547000
125 #define ASM_REG_R_A2 0x527000
126
127 #define ASM_REG_W_A0 0x50F400
128 #define ASM_REG_W_A1 0x54F400
129 #define ASM_REG_W_A2 0x52F400
130
131 #define ASM_REG_R_B0 0x517000
132 #define ASM_REG_R_B1 0x557000
133 #define ASM_REG_R_B2 0x537000
134
135 #define ASM_REG_W_B0 0x51F400
136 #define ASM_REG_W_B1 0x55F400
137 #define ASM_REG_W_B2 0x53F400
138
139 #define ASM_REG_R_VBA 0x057030 /* control register */
140 #define ASM_REG_W_VBA 0x05F430
141
142 #define ASM_REG_R_OMR 0x05703A /* control register */
143 #define ASM_REG_W_OMR 0x05F43A
144
145 #define ASM_REG_R_EP 0x05702A
146 #define ASM_REG_W_EP 0x05F42A
147
148 #define ASM_REG_R_SC 0x057031 /* stack counter */
149 #define ASM_REG_W_SC 0x05F431
150
151 #define ASM_REG_R_SZ 0x057038 /* stack size */
152 #define ASM_REG_W_SZ 0x05F438
153
154 #define ASM_REG_R_SR 0x057039 /* control register, status register */
155 #define ASM_REG_W_SR 0x05F439
156
157 #define ASM_REG_R_SP 0x05703B /* control register, stack pointer */
158 #define ASM_REG_W_SP 0x05F43B
159
160 #define ASM_REG_R_SSH 0x05703C /* control register, system stack high */
161 #define ASM_REG_W_SSH 0x05743C
162
163 #define ASM_REG_R_SSL 0x05703D /* control register, system stack low */
164 #define ASM_REG_W_SSL 0x05F43D
165
166 #define ASM_REG_R_LA 0x05703E /* control register, loop address */
167 #define ASM_REG_W_LA 0x05F43E
168
169 #define ASM_REG_R_LC 0x05703F /* control register, loop count */
170 #define ASM_REG_W_LC 0x05F43F
171
172 #define ASM_REG_R_PC 0x000000
173 #define ASM_REG_W_PC 0x000000
174
175 static const struct
176 {
177 unsigned id;
178 char *name;
179 unsigned bits;
180 uint32_t r_cmd;
181 uint32_t w_cmd;
182 } dsp563xx_regs[] =
183 {
184 /* *INDENT-OFF* */
185 {0, "r0", 24, ASM_REG_R_R0, ASM_REG_W_R0},
186 {1, "r1", 24, ASM_REG_R_R1, ASM_REG_W_R1},
187 {2, "r2", 24, ASM_REG_R_R2, ASM_REG_W_R2},
188 {3, "r3", 24, ASM_REG_R_R3, ASM_REG_W_R3},
189 {4, "r4", 24, ASM_REG_R_R4, ASM_REG_W_R4},
190 {5, "r5", 24, ASM_REG_R_R5, ASM_REG_W_R5},
191 {6, "r6", 24, ASM_REG_R_R6, ASM_REG_W_R6},
192 {7, "r7", 24, ASM_REG_R_R7, ASM_REG_W_R7},
193 {8, "n0", 24, ASM_REG_R_N0, ASM_REG_W_N0},
194 {9, "n1", 24, ASM_REG_R_N1, ASM_REG_W_N1},
195 {10, "n2", 24, ASM_REG_R_N2, ASM_REG_W_N2},
196 {11, "n3", 24, ASM_REG_R_N3, ASM_REG_W_N3},
197 {12, "n4", 24, ASM_REG_R_N4, ASM_REG_W_N4},
198 {13, "n5", 24, ASM_REG_R_N5, ASM_REG_W_N5},
199 {14, "n6", 24, ASM_REG_R_N6, ASM_REG_W_N6},
200 {15, "n7", 24, ASM_REG_R_N7, ASM_REG_W_N7},
201 {16, "m0", 24, ASM_REG_R_M0, ASM_REG_W_M0},
202 {17, "m1", 24, ASM_REG_R_M1, ASM_REG_W_M1},
203 {18, "m2", 24, ASM_REG_R_M2, ASM_REG_W_M2},
204 {19, "m3", 24, ASM_REG_R_M3, ASM_REG_W_M3},
205 {20, "m4", 24, ASM_REG_R_M4, ASM_REG_W_M4},
206 {21, "m5", 24, ASM_REG_R_M5, ASM_REG_W_M5},
207 {22, "m6", 24, ASM_REG_R_M6, ASM_REG_W_M6},
208 {23, "m7", 24, ASM_REG_R_M7, ASM_REG_W_M7},
209 {24, "x0", 24, ASM_REG_R_X0, ASM_REG_W_X0},
210 {25, "x1", 24, ASM_REG_R_X1, ASM_REG_W_X1},
211 {26, "y0", 24, ASM_REG_R_Y0, ASM_REG_W_Y0},
212 {27, "y1", 24, ASM_REG_R_Y1, ASM_REG_W_Y1},
213 {28, "a0", 24, ASM_REG_R_A0, ASM_REG_W_A0},
214 {29, "a1", 24, ASM_REG_R_A1, ASM_REG_W_A1},
215 {30, "a2", 8, ASM_REG_R_A2, ASM_REG_W_A2},
216 {31, "b0", 24, ASM_REG_R_B0, ASM_REG_W_B0},
217 {32, "b1", 24, ASM_REG_R_B1, ASM_REG_W_B1},
218 {33, "b2", 8, ASM_REG_R_B2, ASM_REG_W_B2},
219 {34, "omr", 24, ASM_REG_R_OMR, ASM_REG_W_OMR},
220 {35, "vba", 24, ASM_REG_R_VBA, ASM_REG_W_VBA},
221 {36, "ep", 24, ASM_REG_R_EP, ASM_REG_W_EP},
222 {37, "sc", 24, ASM_REG_R_SC, ASM_REG_W_SC},
223 {38, "sz", 24, ASM_REG_R_SZ, ASM_REG_W_SZ},
224 {39, "sr", 24, ASM_REG_R_SR, ASM_REG_W_SR},
225 {40, "sp", 24, ASM_REG_R_SP, ASM_REG_W_SP},
226 {41, "la", 24, ASM_REG_R_LA, ASM_REG_W_LA},
227 {42, "lc", 24, ASM_REG_R_LC, ASM_REG_W_LC},
228 {43, "pc", 24, ASM_REG_R_PC, ASM_REG_W_PC}
229 /* *INDENT-ON* */
230 };
231
232 static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
233 int *reg_list_size)
234 {
235 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
236 int i;
237
238 if (target->state != TARGET_HALTED)
239 {
240 return ERROR_TARGET_NOT_HALTED;
241 }
242
243 *reg_list_size = DSP563XX_NUMCOREREGS;
244 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
245
246 for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
247 {
248 (*reg_list)[i] = &dsp563xx->core_cache->reg_list[i];
249 }
250
251 return ERROR_OK;
252
253 }
254
255 static int dsp563xx_read_core_reg(struct target *target, int num)
256 {
257 uint32_t reg_value;
258 struct dsp563xx_core_reg *dsp563xx_core_reg;
259 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
260
261 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
262 return ERROR_INVALID_ARGUMENTS;
263
264 dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
265 reg_value = dsp563xx->core_regs[num];
266 buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
267 dsp563xx->core_cache->reg_list[num].valid = 1;
268 dsp563xx->core_cache->reg_list[num].dirty = 0;
269
270 return ERROR_OK;
271 }
272
273 static int dsp563xx_write_core_reg(struct target *target, int num)
274 {
275 uint32_t reg_value;
276 struct dsp563xx_core_reg *dsp563xx_core_reg;
277 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
278
279 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
280 return ERROR_INVALID_ARGUMENTS;
281
282 reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
283 dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info;
284 dsp563xx->core_regs[num] = reg_value;
285 dsp563xx->core_cache->reg_list[num].valid = 1;
286 dsp563xx->core_cache->reg_list[num].dirty = 0;
287
288 return ERROR_OK;
289 }
290
291 static int dsp563xx_target_create(struct target *target, Jim_Interp * interp)
292 {
293 struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
294
295 dsp563xx->jtag_info.tap = target->tap;
296 target->arch_info = dsp563xx;
297 dsp563xx->read_core_reg = dsp563xx_read_core_reg;
298 dsp563xx->write_core_reg = dsp563xx_write_core_reg;
299
300 return ERROR_OK;
301 }
302
303 static int dsp563xx_get_core_reg(struct reg *reg)
304 {
305 int retval = 0;
306
307 LOG_DEBUG("%s", __FUNCTION__);
308
309 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
310 struct target *target = dsp563xx_reg->target;
311 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
312
313 if (target->state != TARGET_HALTED)
314 {
315 return ERROR_TARGET_NOT_HALTED;
316 }
317
318 retval = dsp563xx->read_core_reg(target, dsp563xx_reg->num);
319
320 return retval;
321 }
322
323 static int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf)
324 {
325 LOG_DEBUG("%s", __FUNCTION__);
326
327 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
328 struct target *target = dsp563xx_reg->target;
329 uint32_t value = buf_get_u32(buf, 0, 32);
330
331 if (target->state != TARGET_HALTED)
332 {
333 return ERROR_TARGET_NOT_HALTED;
334 }
335
336 buf_set_u32(reg->value, 0, reg->size, value);
337 reg->dirty = 1;
338 reg->valid = 1;
339
340 return ERROR_OK;
341 }
342
343 static int dsp563xx_save_context(struct target *target)
344 {
345 int i;
346 uint32_t data = 0;
347 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
348 struct dsp563xx_core_reg *arch_info;
349
350 for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
351 {
352
353 // if (!dsp563xx->core_cache->reg_list[i].valid)
354 {
355 arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
356 dsp563xx_once_execute_dw_ir(target->tap, arch_info->r_cmd,
357 0xfffffc);
358 dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
359 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR,
360 &data);
361 dsp563xx->core_regs[i] = data;
362 dsp563xx->read_core_reg(target, i);
363 }
364 }
365
366 /* read pc */
367 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &data);
368 dsp563xx->core_regs[i] = data;
369 dsp563xx->read_core_reg(target, i);
370
371 return ERROR_OK;
372 }
373
374 static int dsp563xx_restore_context(struct target *target)
375 {
376 int i;
377 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
378 struct dsp563xx_core_reg *arch_info;
379
380 for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++)
381 {
382 if (dsp563xx->core_cache->reg_list[i].dirty)
383 {
384 arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
385
386 dsp563xx->write_core_reg(target, i);
387
388 dsp563xx_once_execute_dw_ir(target->tap, arch_info->w_cmd,
389 dsp563xx->core_regs[i]);
390 dsp563xx_once_execute_sw_ir(target->tap, 0x000000);
391 }
392 }
393
394 return ERROR_OK;
395 }
396
397 static const struct reg_arch_type dsp563xx_reg_type = {
398 .get = dsp563xx_get_core_reg,
399 .set = dsp563xx_set_core_reg,
400 };
401
402 static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
403 {
404 /* get pointers to arch-specific information */
405 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
406
407 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
408 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
409 struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS);
410 struct dsp563xx_core_reg *arch_info =
411 malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
412 int i;
413
414 LOG_DEBUG("%s", __FUNCTION__);
415
416 /* Build the process context cache */
417 cache->name = "dsp563xx registers";
418 cache->next = NULL;
419 cache->reg_list = reg_list;
420 cache->num_regs = DSP563XX_NUMCOREREGS;
421 (*cache_p) = cache;
422 dsp563xx->core_cache = cache;
423
424 for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
425 {
426 arch_info[i].num = dsp563xx_regs[i].id;
427 arch_info[i].name = dsp563xx_regs[i].name;
428 arch_info[i].size = dsp563xx_regs[i].bits;
429 arch_info[i].r_cmd = dsp563xx_regs[i].r_cmd;
430 arch_info[i].w_cmd = dsp563xx_regs[i].w_cmd;
431 arch_info[i].target = target;
432 arch_info[i].dsp563xx_common = dsp563xx;
433 reg_list[i].name = dsp563xx_regs[i].name;
434 reg_list[i].size = dsp563xx_regs[i].bits;
435 reg_list[i].value = calloc(1, 4);
436 reg_list[i].dirty = 0;
437 reg_list[i].valid = 0;
438 reg_list[i].type = &dsp563xx_reg_type;
439 reg_list[i].arch_info = &arch_info[i];
440 }
441
442 return ERROR_OK;
443 }
444
445 static int dsp563xx_arch_state(struct target *target)
446 {
447 LOG_DEBUG("%s", __FUNCTION__);
448 return ERROR_OK;
449 }
450
451 static int dsp563xx_jtag_status(struct target *target, uint8_t * status)
452 {
453 uint8_t ir_in;
454
455 ir_in = 0;
456
457 dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
458 dsp563xx_execute_queue();
459
460 *status = ir_in;
461
462 return ERROR_OK;
463 }
464
465 static int dsp563xx_jtag_debug_request(struct target *target)
466 {
467 uint8_t ir_in = 0;
468 uint32_t retry = 0;
469
470 while (ir_in != JTAG_STATUS_DEBUG)
471 {
472 dsp563xx_jtag_sendinstr(target->tap, &ir_in,
473 JTAG_INSTR_DEBUG_REQUEST);
474 dsp563xx_execute_queue();
475 LOG_DEBUG("JTAG CMD 7 res: %02X", ir_in);
476 dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE);
477 dsp563xx_execute_queue();
478 LOG_DEBUG("JTAG CMD 6 res: %02X", ir_in);
479
480 if (retry++ == 100)
481 return ERROR_TARGET_FAILURE;
482 }
483
484 if (ir_in != JTAG_STATUS_DEBUG)
485 {
486 return ERROR_TARGET_FAILURE;
487 }
488
489 return ERROR_OK;
490 }
491
492 static int dsp563xx_poll(struct target *target)
493 {
494 uint8_t jtag_status;
495 uint32_t once_status;
496
497 dsp563xx_jtag_status(target, &jtag_status);
498
499 if ((jtag_status & 1) != 1)
500 {
501 target->state = TARGET_UNKNOWN;
502 LOG_ERROR
503 ("jtag status contains invalid mode value - communication failure");
504 return ERROR_TARGET_FAILURE;
505 }
506
507 if (jtag_status != JTAG_STATUS_DEBUG)
508 {
509 target->state = TARGET_RUNNING;
510 }
511
512 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status);
513
514 if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M)
515 {
516 target->state = TARGET_HALTED;
517
518 }
519
520 return ERROR_OK;
521 }
522
523 static int dsp563xx_halt(struct target *target)
524 {
525 uint8_t jtag_status;
526 uint32_t once_status;
527 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
528
529 if (target->state == TARGET_HALTED)
530 {
531 LOG_DEBUG("target was already halted");
532 return ERROR_OK;
533 }
534
535 if (target->state == TARGET_UNKNOWN)
536 {
537 LOG_WARNING("target was in unknown state when halt was requested");
538 }
539
540 // if ( jtag_status != 0x0d )
541 {
542 dsp563xx_jtag_debug_request(target);
543
544 /* store pipeline register */
545 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
546 &dsp563xx->pipeline_context.once_opilr);
547 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
548 &dsp563xx->pipeline_context.once_opdbr);
549
550 dsp563xx_save_context(target);
551
552 dsp563xx_jtag_status(target, &jtag_status);
553 LOG_DEBUG("%02X", jtag_status);
554 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
555 &once_status);
556 LOG_DEBUG("%02X", (unsigned) once_status);
557 }
558
559 LOG_DEBUG("target->state: %s", target_state_name(target));
560
561 LOG_DEBUG("%s", __FUNCTION__);
562
563 return ERROR_OK;
564 }
565
566 #define DSP563XX_ASM_CMD_JUMP 0x0AF080
567
568 static int dsp563xx_resume(struct target *target, int current, uint32_t address,
569 int handle_breakpoints, int debug_execution)
570 {
571 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
572
573 LOG_DEBUG("%s", __FUNCTION__);
574
575 dsp563xx_restore_context(target);
576
577 if (current)
578 {
579 /* restore pipeline registers and go */
580 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
581 dsp563xx->pipeline_context.once_opilr);
582 dsp563xx_once_reg_write(target->tap,
583 DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
584 DSP563XX_ONCE_OCR_GO,
585 dsp563xx->pipeline_context.once_opdbr);
586 }
587 else
588 {
589 /* set to go register and jump */
590 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
591 DSP563XX_ASM_CMD_JUMP);
592 dsp563xx_once_reg_write(target->tap,
593 DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
594 | DSP563XX_ONCE_OCR_GO, address);
595 }
596
597 target->state = TARGET_RUNNING;
598
599 return ERROR_OK;
600 }
601
602 static int dsp563xx_step(struct target *target, int current, uint32_t address,
603 int handle_breakpoints)
604 {
605 uint32_t once_status;
606 uint32_t dr_in, cnt;
607 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
608
609 if (target->state != TARGET_HALTED)
610 {
611 LOG_DEBUG("target was not halted");
612 return ERROR_OK;
613 }
614
615 LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address);
616
617 dsp563xx_jtag_debug_request(target);
618
619 dsp563xx_restore_context(target);
620
621 /* reset trace mode */
622 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000);
623 /* enable trace mode */
624 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
625 DSP563XX_ONCE_OSCR_TME);
626
627 cnt = 0;
628
629 /* on JUMP we need one extra cycle */
630 if (!current)
631 cnt++;
632
633 /* load step counter with N-1 */
634 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OTC, cnt);
635
636 if (current)
637 {
638 /* restore pipeline registers and go */
639 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR,
640 dsp563xx->pipeline_context.once_opilr);
641 dsp563xx_once_reg_write(target->tap,
642 DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX |
643 DSP563XX_ONCE_OCR_GO,
644 dsp563xx->pipeline_context.once_opdbr);
645 }
646 else
647 {
648 /* set to go register and jump */
649 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR,
650 DSP563XX_ASM_CMD_JUMP);
651 dsp563xx_once_reg_write(target->tap,
652 DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX
653 | DSP563XX_ONCE_OCR_GO, address);
654 }
655
656 while (1)
657 {
658 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
659 &once_status);
660
661 if (once_status & DSP563XX_ONCE_OSCR_TO)
662 {
663 /* store pipeline register */
664 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR,
665 &dsp563xx->pipeline_context.
666 once_opilr);
667 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR,
668 &dsp563xx->pipeline_context.
669 once_opdbr);
670
671 dsp563xx_save_context(target);
672
673 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR,
674 &dr_in);
675 LOG_DEBUG("%08X", (unsigned) dr_in);
676 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR,
677 &dr_in);
678 LOG_DEBUG("%08X", (unsigned) dr_in);
679 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX,
680 &dr_in);
681 LOG_DEBUG("%08X", (unsigned) dr_in);
682
683 /* reset trace mode */
684 dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
685 0x000000);
686
687 break;
688 }
689 }
690
691 return ERROR_OK;
692 }
693
694 static int dsp563xx_assert_reset(struct target *target)
695 {
696 target->state = TARGET_RESET;
697
698 LOG_DEBUG("%s", __FUNCTION__);
699 return ERROR_OK;
700 }
701
702 static int dsp563xx_deassert_reset(struct target *target)
703 {
704 target->state = TARGET_RUNNING;
705
706 LOG_DEBUG("%s", __FUNCTION__);
707 return ERROR_OK;
708 }
709
710 static int dsp563xx_soft_reset_halt(struct target *target)
711 {
712 LOG_DEBUG("%s", __FUNCTION__);
713 return ERROR_OK;
714 }
715
716 /*
717 * 000000 nop
718 * 46F400 AABBCC move #$aabbcc,y0
719 * 60F400 AABBCC move #$aabbcc,r0
720 * 467000 AABBCC move y0,x:AABBCC
721 * 607000 AABBCC move r0,x:AABBCC
722
723 * 46E000 move x:(r0),y0
724 * 4EE000 move y:(r0),y0
725 * 07E086 move p:(r0),y0
726
727 * 0450B9 move sr,r0
728 * 0446BA move omr,y0
729 * 0446BC move ssh,y0
730 * 0446BD move ssl,y0
731 * 0446BE move la,y0
732 * 0446BF move lc,y0
733 *
734 * 61F000 AABBCC move x:AABBCC,r1
735 * 076190 movem r0,p:(r1)
736 *
737 */
738 static int dsp563xx_read_memory_p(struct target *target, uint32_t address,
739 uint32_t size, uint32_t count, uint8_t * buffer)
740 {
741 uint32_t i, x;
742 uint32_t data;
743 uint8_t *b;
744
745 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
746 PRIx32, address, size, count);
747
748 if (target->state != TARGET_HALTED)
749 {
750 LOG_WARNING("target not halted");
751 return ERROR_TARGET_NOT_HALTED;
752 }
753
754 x = count;
755
756 for (i = 0; i < x; i++)
757 {
758 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, address + i);
759 dsp563xx_once_execute_sw_ir_nq(target->tap, 0x07E086);
760 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x467000, 0xfffffc);
761 dsp563xx_execute_queue();
762
763 dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, &data);
764
765 b = buffer + 4 * i;
766 if (size > 0)
767 *b++ = data >> 0;
768 if (size > 1)
769 *b++ = data >> 8;
770 if (size > 2)
771 *b++ = data >> 16;
772 if (size > 3)
773 *b++ = 0x00;
774 }
775
776 return ERROR_OK;
777 }
778
779 static int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size,
780 uint32_t count, uint8_t * buffer)
781 {
782 uint32_t i, x;
783 uint32_t data;
784 uint8_t *b;
785
786 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8"
787 PRIx32 "", address, size, count);
788
789 if (target->state != TARGET_HALTED)
790 {
791 LOG_WARNING("target not halted");
792 return ERROR_TARGET_NOT_HALTED;
793 }
794
795 x = count;
796
797 for (i = 0; i < x; i++)
798 {
799 b = buffer + 4 * i;
800
801 data = 0;
802 if (size > 0)
803 data = *buffer++;
804 if (size > 1)
805 data |= (*buffer++) << 8;
806 if (size > 2)
807 data |= (*buffer++) << 16;
808 if (size > 3)
809 data |= (*buffer++) << 24;
810
811 // LOG_DEBUG("%08X", data);
812
813 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x61F400, address + i);
814 dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, data);
815 dsp563xx_once_execute_sw_ir_nq(target->tap, 0x076190);
816 dsp563xx_execute_queue();
817 }
818
819 return ERROR_OK;
820 }
821
822 int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
823 int len)
824 {
825 return dsp563xx_write_dr_u32(tap, dr_in, dr_out, len, 1);
826 }
827
828 static int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out)
829 {
830 return dsp563xx_write_ir_u8(tap, ir_in, ir_out, DSP563XX_JTAG_INS_LEN, 1);
831 }
832
833 /* IR and DR functions */
834 static int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out,
835 int ir_len, int rti)
836 {
837 if (NULL == tap)
838 {
839 LOG_ERROR("invalid tap");
840 return ERROR_FAIL;
841 }
842 if (ir_len != tap->ir_length)
843 {
844 LOG_ERROR("invalid ir_len");
845 return ERROR_FAIL;
846 }
847
848 {
849 jtag_add_plain_ir_scan(tap->ir_length, ir_out, ir_in, TAP_IDLE);
850 }
851
852 return ERROR_OK;
853 }
854
855 static int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out,
856 int dr_len, int rti)
857 {
858 if (NULL == tap)
859 {
860 LOG_ERROR("invalid tap");
861 return ERROR_FAIL;
862 }
863
864 {
865 jtag_add_plain_dr_scan(dr_len, dr_out, dr_in, TAP_IDLE);
866 }
867
868 return ERROR_OK;
869 }
870
871 static int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out,
872 int ir_len, int rti)
873 {
874 if (ir_len > 8)
875 {
876 LOG_ERROR("ir_len overflow, maxium is 8");
877 return ERROR_FAIL;
878 }
879
880 dsp563xx_write_ir(tap, ir_in, &ir_out, ir_len, rti);
881
882 return ERROR_OK;
883 }
884
885 int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * dr_in, uint8_t dr_out,
886 int dr_len, int rti)
887 {
888 if (dr_len > 8)
889 {
890 LOG_ERROR("dr_len overflow, maxium is 8");
891 return ERROR_FAIL;
892 }
893
894 dsp563xx_write_dr(tap, dr_in, &dr_out, dr_len, rti);
895
896 return ERROR_OK;
897 }
898
899 int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out,
900 int ir_len, int rti)
901 {
902 if (ir_len > 16)
903 {
904 LOG_ERROR("ir_len overflow, maxium is 16");
905 return ERROR_FAIL;
906 }
907
908 dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
909
910 return ERROR_OK;
911 }
912
913 int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * dr_in, uint16_t dr_out,
914 int dr_len, int rti)
915 {
916 if (dr_len > 16)
917 {
918 LOG_ERROR("dr_len overflow, maxium is 16");
919 return ERROR_FAIL;
920 }
921
922 dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
923
924 return ERROR_OK;
925 }
926
927 int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out,
928 int ir_len, int rti)
929 {
930 if (ir_len > 32)
931 {
932 LOG_ERROR("ir_len overflow, maxium is 32");
933 return ERROR_FAIL;
934 }
935
936 dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti);
937
938 return ERROR_OK;
939 }
940
941 int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out,
942 int dr_len, int rti)
943 {
944 if (dr_len > 32)
945 {
946 LOG_ERROR("dr_len overflow, maxium is 32");
947 return ERROR_FAIL;
948 }
949
950 dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti);
951
952 return ERROR_OK;
953 }
954
955 int dsp563xx_execute_queue(void)
956 {
957 return jtag_execute_queue();
958 }
959
960 /** Holds methods for DSP563XX targets. */
961 struct target_type dsp563xx_target = {
962 .name = "dsp563xx",
963
964 .poll = dsp563xx_poll,
965 .arch_state = dsp563xx_arch_state,
966
967 .target_request_data = NULL,
968
969 .get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
970
971 .halt = dsp563xx_halt,
972 .resume = dsp563xx_resume,
973 .step = dsp563xx_step,
974
975 .assert_reset = dsp563xx_assert_reset,
976 .deassert_reset = dsp563xx_deassert_reset,
977 .soft_reset_halt = dsp563xx_soft_reset_halt,
978
979 .read_memory = dsp563xx_read_memory_p,
980 .write_memory = dsp563xx_write_memory_p,
981
982 .target_create = dsp563xx_target_create,
983 .init_target = dsp563xx_init_target,
984 };
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