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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / dsp563xx.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2009-2011 by Mathias Kuester *
5 * mkdorg@users.sourceforge.net *
6 ***************************************************************************/
7
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11
12 #include <jim.h>
13
14 #include "target.h"
15 #include "breakpoints.h"
16 #include "target_type.h"
17 #include "algorithm.h"
18 #include "register.h"
19 #include "dsp563xx.h"
20 #include "dsp563xx_once.h"
21
22 #define ASM_REG_W_R0 0x60F400
23 #define ASM_REG_W_R1 0x61F400
24 #define ASM_REG_W_R2 0x62F400
25 #define ASM_REG_W_R3 0x63F400
26 #define ASM_REG_W_R4 0x64F400
27 #define ASM_REG_W_R5 0x65F400
28 #define ASM_REG_W_R6 0x66F400
29 #define ASM_REG_W_R7 0x67F400
30
31 #define ASM_REG_W_N0 0x70F400
32 #define ASM_REG_W_N1 0x71F400
33 #define ASM_REG_W_N2 0x72F400
34 #define ASM_REG_W_N3 0x73F400
35 #define ASM_REG_W_N4 0x74F400
36 #define ASM_REG_W_N5 0x75F400
37 #define ASM_REG_W_N6 0x76F400
38 #define ASM_REG_W_N7 0x77F400
39
40 #define ASM_REG_W_M0 0x05F420
41 #define ASM_REG_W_M1 0x05F421
42 #define ASM_REG_W_M2 0x05F422
43 #define ASM_REG_W_M3 0x05F423
44 #define ASM_REG_W_M4 0x05F424
45 #define ASM_REG_W_M5 0x05F425
46 #define ASM_REG_W_M6 0x05F426
47 #define ASM_REG_W_M7 0x05F427
48
49 #define ASM_REG_W_X0 0x44F400
50 #define ASM_REG_W_X1 0x45F400
51
52 #define ASM_REG_W_Y0 0x46F400
53 #define ASM_REG_W_Y1 0x47F400
54
55 #define ASM_REG_W_A0 0x50F400
56 #define ASM_REG_W_A1 0x54F400
57 #define ASM_REG_W_A2 0x52F400
58
59 #define ASM_REG_W_B0 0x51F400
60 #define ASM_REG_W_B1 0x55F400
61 #define ASM_REG_W_B2 0x53F400
62
63 #define ASM_REG_W_VBA 0x05F430
64 #define ASM_REG_W_OMR 0x05F43A
65 #define ASM_REG_W_EP 0x05F42A
66 #define ASM_REG_W_SC 0x05F431
67 #define ASM_REG_W_SZ 0x05F438
68 #define ASM_REG_W_SR 0x05F439
69 #define ASM_REG_W_SP 0x05F43B
70 #define ASM_REG_W_SSH 0x05F43C
71 #define ASM_REG_W_SSL 0x05F43D
72 #define ASM_REG_W_LA 0x05F43E
73 #define ASM_REG_W_LC 0x05F43F
74 #define ASM_REG_W_PC 0x000000
75 #define ASM_REG_W_IPRC 0xFFFFFF
76 #define ASM_REG_W_IPRP 0xFFFFFE
77
78 #define ASM_REG_W_BCR 0xFFFFFB
79 #define ASM_REG_W_DCR 0xFFFFFA
80 #define ASM_REG_W_AAR0 0xFFFFF9
81 #define ASM_REG_W_AAR1 0xFFFFF8
82 #define ASM_REG_W_AAR2 0xFFFFF7
83 #define ASM_REG_W_AAR3 0xFFFFF6
84
85 /*
86 * OBCR Register bit definitions
87 */
88 #define OBCR_B0_AND_B1 ((0x0) << 10)
89 #define OBCR_B0_OR_B1 ((0x1) << 10)
90 #define OBCR_B1_AFTER_B0 ((0x2) << 10)
91 #define OBCR_B0_AFTER_B1 ((0x3) << 10)
92
93 #define OBCR_BP_DISABLED (0x0)
94 #define OBCR_BP_MEM_P (0x1)
95 #define OBCR_BP_MEM_X (0x2)
96 #define OBCR_BP_MEM_Y (0x3)
97 #define OBCR_BP_ON_READ ((0x2) << 0)
98 #define OBCR_BP_ON_WRITE ((0x1) << 0)
99 #define OBCR_BP_CC_NOT_EQUAL ((0x0) << 2)
100 #define OBCR_BP_CC_EQUAL ((0x1) << 2)
101 #define OBCR_BP_CC_LESS_THAN ((0x2) << 2)
102 #define OBCR_BP_CC_GREATER_THAN ((0x3) << 2)
103
104 #define OBCR_BP_0(x) ((x)<<2)
105 #define OBCR_BP_1(x) ((x)<<6)
106
107
108 enum once_reg_idx {
109 ONCE_REG_IDX_OSCR = 0,
110 ONCE_REG_IDX_OMBC = 1,
111 ONCE_REG_IDX_OBCR = 2,
112 ONCE_REG_IDX_OMLR0 = 3,
113 ONCE_REG_IDX_OMLR1 = 4,
114 ONCE_REG_IDX_OGDBR = 5,
115 ONCE_REG_IDX_OPDBR = 6,
116 ONCE_REG_IDX_OPILR = 7,
117 ONCE_REG_IDX_PDB = 8,
118 ONCE_REG_IDX_OTC = 9,
119 ONCE_REG_IDX_OPABFR = 10,
120 ONCE_REG_IDX_OPABDR = 11,
121 ONCE_REG_IDX_OPABEX = 12,
122 ONCE_REG_IDX_OPABF0 = 13,
123 ONCE_REG_IDX_OPABF1 = 14,
124 ONCE_REG_IDX_OPABF2 = 15,
125 ONCE_REG_IDX_OPABF3 = 16,
126 ONCE_REG_IDX_OPABF4 = 17,
127 ONCE_REG_IDX_OPABF5 = 18,
128 ONCE_REG_IDX_OPABF6 = 19,
129 ONCE_REG_IDX_OPABF7 = 20,
130 ONCE_REG_IDX_OPABF8 = 21,
131 ONCE_REG_IDX_OPABF9 = 22,
132 ONCE_REG_IDX_OPABF10 = 23,
133 ONCE_REG_IDX_OPABF11 = 24,
134 };
135
136 static struct once_reg once_regs[] = {
137 {ONCE_REG_IDX_OSCR, DSP563XX_ONCE_OSCR, 24, "OSCR", 0},
138 {ONCE_REG_IDX_OMBC, DSP563XX_ONCE_OMBC, 24, "OMBC", 0},
139 {ONCE_REG_IDX_OBCR, DSP563XX_ONCE_OBCR, 24, "OBCR", 0},
140 {ONCE_REG_IDX_OMLR0, DSP563XX_ONCE_OMLR0, 24, "OMLR0", 0},
141 {ONCE_REG_IDX_OMLR1, DSP563XX_ONCE_OMLR1, 24, "OMLR1", 0},
142 {ONCE_REG_IDX_OGDBR, DSP563XX_ONCE_OGDBR, 24, "OGDBR", 0},
143 {ONCE_REG_IDX_OPDBR, DSP563XX_ONCE_OPDBR, 24, "OPDBR", 0},
144 {ONCE_REG_IDX_OPILR, DSP563XX_ONCE_OPILR, 24, "OPILR", 0},
145 {ONCE_REG_IDX_PDB, DSP563XX_ONCE_PDBGOTO, 24, "PDB", 0},
146 {ONCE_REG_IDX_OTC, DSP563XX_ONCE_OTC, 24, "OTC", 0},
147 {ONCE_REG_IDX_OPABFR, DSP563XX_ONCE_OPABFR, 24, "OPABFR", 0},
148 {ONCE_REG_IDX_OPABDR, DSP563XX_ONCE_OPABDR, 24, "OPABDR", 0},
149 {ONCE_REG_IDX_OPABEX, DSP563XX_ONCE_OPABEX, 24, "OPABEX", 0},
150 {ONCE_REG_IDX_OPABF0, DSP563XX_ONCE_OPABF11, 25, "OPABF0", 0},
151 {ONCE_REG_IDX_OPABF1, DSP563XX_ONCE_OPABF11, 25, "OPABF1", 0},
152 {ONCE_REG_IDX_OPABF2, DSP563XX_ONCE_OPABF11, 25, "OPABF2", 0},
153 {ONCE_REG_IDX_OPABF3, DSP563XX_ONCE_OPABF11, 25, "OPABF3", 0},
154 {ONCE_REG_IDX_OPABF4, DSP563XX_ONCE_OPABF11, 25, "OPABF4", 0},
155 {ONCE_REG_IDX_OPABF5, DSP563XX_ONCE_OPABF11, 25, "OPABF5", 0},
156 {ONCE_REG_IDX_OPABF6, DSP563XX_ONCE_OPABF11, 25, "OPABF6", 0},
157 {ONCE_REG_IDX_OPABF7, DSP563XX_ONCE_OPABF11, 25, "OPABF7", 0},
158 {ONCE_REG_IDX_OPABF8, DSP563XX_ONCE_OPABF11, 25, "OPABF8", 0},
159 {ONCE_REG_IDX_OPABF9, DSP563XX_ONCE_OPABF11, 25, "OPABF9", 0},
160 {ONCE_REG_IDX_OPABF10, DSP563XX_ONCE_OPABF11, 25, "OPABF10", 0},
161 {ONCE_REG_IDX_OPABF11, DSP563XX_ONCE_OPABF11, 25, "OPABF11", 0},
162 /* {25,0x1f,24,"NRSEL",0}, */
163 };
164
165 enum dsp563xx_reg_idx {
166 DSP563XX_REG_IDX_R0 = 0,
167 DSP563XX_REG_IDX_R1 = 1,
168 DSP563XX_REG_IDX_R2 = 2,
169 DSP563XX_REG_IDX_R3 = 3,
170 DSP563XX_REG_IDX_R4 = 4,
171 DSP563XX_REG_IDX_R5 = 5,
172 DSP563XX_REG_IDX_R6 = 6,
173 DSP563XX_REG_IDX_R7 = 7,
174 DSP563XX_REG_IDX_N0 = 8,
175 DSP563XX_REG_IDX_N1 = 9,
176 DSP563XX_REG_IDX_N2 = 10,
177 DSP563XX_REG_IDX_N3 = 11,
178 DSP563XX_REG_IDX_N4 = 12,
179 DSP563XX_REG_IDX_N5 = 13,
180 DSP563XX_REG_IDX_N6 = 14,
181 DSP563XX_REG_IDX_N7 = 15,
182 DSP563XX_REG_IDX_M0 = 16,
183 DSP563XX_REG_IDX_M1 = 17,
184 DSP563XX_REG_IDX_M2 = 18,
185 DSP563XX_REG_IDX_M3 = 19,
186 DSP563XX_REG_IDX_M4 = 20,
187 DSP563XX_REG_IDX_M5 = 21,
188 DSP563XX_REG_IDX_M6 = 22,
189 DSP563XX_REG_IDX_M7 = 23,
190 DSP563XX_REG_IDX_X0 = 24,
191 DSP563XX_REG_IDX_X1 = 25,
192 DSP563XX_REG_IDX_Y0 = 26,
193 DSP563XX_REG_IDX_Y1 = 27,
194 DSP563XX_REG_IDX_A0 = 28,
195 DSP563XX_REG_IDX_A1 = 29,
196 DSP563XX_REG_IDX_A2 = 30,
197 DSP563XX_REG_IDX_B0 = 31,
198 DSP563XX_REG_IDX_B1 = 32,
199 DSP563XX_REG_IDX_B2 = 33,
200 DSP563XX_REG_IDX_SSH = 34,
201 DSP563XX_REG_IDX_SSL = 35,
202 DSP563XX_REG_IDX_SP = 36,
203 DSP563XX_REG_IDX_EP = 37,
204 DSP563XX_REG_IDX_SZ = 38,
205 DSP563XX_REG_IDX_SC = 39,
206 DSP563XX_REG_IDX_PC = 40,
207 DSP563XX_REG_IDX_SR = 41,
208 DSP563XX_REG_IDX_OMR = 42,
209 DSP563XX_REG_IDX_LA = 43,
210 DSP563XX_REG_IDX_LC = 44,
211 DSP563XX_REG_IDX_VBA = 45,
212 DSP563XX_REG_IDX_IPRC = 46,
213 DSP563XX_REG_IDX_IPRP = 47,
214 DSP563XX_REG_IDX_BCR = 48,
215 DSP563XX_REG_IDX_DCR = 49,
216 DSP563XX_REG_IDX_AAR0 = 50,
217 DSP563XX_REG_IDX_AAR1 = 51,
218 DSP563XX_REG_IDX_AAR2 = 52,
219 DSP563XX_REG_IDX_AAR3 = 53,
220 };
221
222 static const struct {
223 unsigned id;
224 const char *name;
225 unsigned bits;
226 /* effective addressing mode encoding */
227 uint8_t eame;
228 uint32_t instr_mask;
229 } dsp563xx_regs[] = {
230 /* *INDENT-OFF* */
231 /* address registers */
232 {DSP563XX_REG_IDX_R0, "r0", 24, 0x10, ASM_REG_W_R0},
233 {DSP563XX_REG_IDX_R1, "r1", 24, 0x11, ASM_REG_W_R1},
234 {DSP563XX_REG_IDX_R2, "r2", 24, 0x12, ASM_REG_W_R2},
235 {DSP563XX_REG_IDX_R3, "r3", 24, 0x13, ASM_REG_W_R3},
236 {DSP563XX_REG_IDX_R4, "r4", 24, 0x14, ASM_REG_W_R4},
237 {DSP563XX_REG_IDX_R5, "r5", 24, 0x15, ASM_REG_W_R5},
238 {DSP563XX_REG_IDX_R6, "r6", 24, 0x16, ASM_REG_W_R6},
239 {DSP563XX_REG_IDX_R7, "r7", 24, 0x17, ASM_REG_W_R7},
240 /* offset registers */
241 {DSP563XX_REG_IDX_N0, "n0", 24, 0x18, ASM_REG_W_N0},
242 {DSP563XX_REG_IDX_N1, "n1", 24, 0x19, ASM_REG_W_N1},
243 {DSP563XX_REG_IDX_N2, "n2", 24, 0x1a, ASM_REG_W_N2},
244 {DSP563XX_REG_IDX_N3, "n3", 24, 0x1b, ASM_REG_W_N3},
245 {DSP563XX_REG_IDX_N4, "n4", 24, 0x1c, ASM_REG_W_N4},
246 {DSP563XX_REG_IDX_N5, "n5", 24, 0x1d, ASM_REG_W_N5},
247 {DSP563XX_REG_IDX_N6, "n6", 24, 0x1e, ASM_REG_W_N6},
248 {DSP563XX_REG_IDX_N7, "n7", 24, 0x1f, ASM_REG_W_N7},
249 /* modifier registers */
250 {DSP563XX_REG_IDX_M0, "m0", 24, 0x20, ASM_REG_W_M0},
251 {DSP563XX_REG_IDX_M1, "m1", 24, 0x21, ASM_REG_W_M1},
252 {DSP563XX_REG_IDX_M2, "m2", 24, 0x22, ASM_REG_W_M2},
253 {DSP563XX_REG_IDX_M3, "m3", 24, 0x23, ASM_REG_W_M3},
254 {DSP563XX_REG_IDX_M4, "m4", 24, 0x24, ASM_REG_W_M4},
255 {DSP563XX_REG_IDX_M5, "m5", 24, 0x25, ASM_REG_W_M5},
256 {DSP563XX_REG_IDX_M6, "m6", 24, 0x26, ASM_REG_W_M6},
257 {DSP563XX_REG_IDX_M7, "m7", 24, 0x27, ASM_REG_W_M7},
258 /* data alu input register */
259 {DSP563XX_REG_IDX_X0, "x0", 24, 0x04, ASM_REG_W_X0},
260 {DSP563XX_REG_IDX_X1, "x1", 24, 0x05, ASM_REG_W_X1},
261 {DSP563XX_REG_IDX_Y0, "y0", 24, 0x06, ASM_REG_W_Y0},
262 {DSP563XX_REG_IDX_Y1, "y1", 24, 0x07, ASM_REG_W_Y1},
263 /* data alu accumulator register */
264 {DSP563XX_REG_IDX_A0, "a0", 24, 0x08, ASM_REG_W_A0},
265 {DSP563XX_REG_IDX_A1, "a1", 24, 0x0c, ASM_REG_W_A1},
266 {DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2},
267 {DSP563XX_REG_IDX_B0, "b0", 24, 0x09, ASM_REG_W_B0},
268 {DSP563XX_REG_IDX_B1, "b1", 24, 0x0d, ASM_REG_W_B1},
269 {DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2},
270 /* stack */
271 {DSP563XX_REG_IDX_SSH, "ssh", 24, 0x3c, ASM_REG_W_SSH},
272 {DSP563XX_REG_IDX_SSL, "ssl", 24, 0x3d, ASM_REG_W_SSL},
273 {DSP563XX_REG_IDX_SP, "sp", 24, 0x3b, ASM_REG_W_SP},
274 {DSP563XX_REG_IDX_EP, "ep", 24, 0x2a, ASM_REG_W_EP},
275 {DSP563XX_REG_IDX_SZ, "sz", 24, 0x38, ASM_REG_W_SZ},
276 {DSP563XX_REG_IDX_SC, "sc", 24, 0x31, ASM_REG_W_SC},
277 /* system */
278 {DSP563XX_REG_IDX_PC, "pc", 24, 0x00, ASM_REG_W_PC},
279 {DSP563XX_REG_IDX_SR, "sr", 24, 0x39, ASM_REG_W_SR},
280 {DSP563XX_REG_IDX_OMR, "omr", 24, 0x3a, ASM_REG_W_OMR},
281 {DSP563XX_REG_IDX_LA, "la", 24, 0x3e, ASM_REG_W_LA},
282 {DSP563XX_REG_IDX_LC, "lc", 24, 0x3f, ASM_REG_W_LC},
283 /* interrupt */
284 {DSP563XX_REG_IDX_VBA, "vba", 24, 0x30, ASM_REG_W_VBA},
285 {DSP563XX_REG_IDX_IPRC, "iprc", 24, 0x00, ASM_REG_W_IPRC},
286 {DSP563XX_REG_IDX_IPRP, "iprp", 24, 0x00, ASM_REG_W_IPRP},
287 /* port a */
288 {DSP563XX_REG_IDX_BCR, "bcr", 24, 0x00, ASM_REG_W_BCR},
289 {DSP563XX_REG_IDX_DCR, "dcr", 24, 0x00, ASM_REG_W_DCR},
290 {DSP563XX_REG_IDX_AAR0, "aar0", 24, 0x00, ASM_REG_W_AAR0},
291 {DSP563XX_REG_IDX_AAR1, "aar1", 24, 0x00, ASM_REG_W_AAR1},
292 {DSP563XX_REG_IDX_AAR2, "aar2", 24, 0x00, ASM_REG_W_AAR2},
293 {DSP563XX_REG_IDX_AAR3, "aar3", 24, 0x00, ASM_REG_W_AAR3},
294 /* *INDENT-ON* */
295 };
296
297 enum memory_type {
298 MEM_X = 0,
299 MEM_Y = 1,
300 MEM_P = 2,
301 MEM_L = 3,
302 };
303
304 enum watchpoint_condition {
305 EQUAL,
306 NOT_EQUAL,
307 GREATER,
308 LESS_THAN
309 };
310
311 #define INSTR_JUMP 0x0AF080
312 /* Effective Addressing Mode Encoding */
313 #define EAME_R0 0x10
314 /* instruction encoder */
315 /* movep
316 * s - peripheral space X/Y (X=0,Y=1)
317 * w - write/read
318 * d - source/destination register
319 * p - IO short address
320 */
321 #define INSTR_MOVEP_REG_HIO(s, w, d, p) (0x084000 | \
322 ((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f))
323
324 /* the gdb register list is send in this order */
325 static const uint8_t gdb_reg_list_idx[] = {
326 DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0,
327 DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2,
328 DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR,
329 DSP563XX_REG_IDX_OMR, DSP563XX_REG_IDX_LA, DSP563XX_REG_IDX_LC, DSP563XX_REG_IDX_SSH,
330 DSP563XX_REG_IDX_SSL, DSP563XX_REG_IDX_SP, DSP563XX_REG_IDX_EP, DSP563XX_REG_IDX_SZ,
331 DSP563XX_REG_IDX_SC, DSP563XX_REG_IDX_VBA, DSP563XX_REG_IDX_IPRC, DSP563XX_REG_IDX_IPRP,
332 DSP563XX_REG_IDX_BCR, DSP563XX_REG_IDX_DCR, DSP563XX_REG_IDX_AAR0, DSP563XX_REG_IDX_AAR1,
333 DSP563XX_REG_IDX_AAR2, DSP563XX_REG_IDX_AAR3, DSP563XX_REG_IDX_R0, DSP563XX_REG_IDX_R1,
334 DSP563XX_REG_IDX_R2, DSP563XX_REG_IDX_R3, DSP563XX_REG_IDX_R4, DSP563XX_REG_IDX_R5,
335 DSP563XX_REG_IDX_R6, DSP563XX_REG_IDX_R7, DSP563XX_REG_IDX_N0, DSP563XX_REG_IDX_N1,
336 DSP563XX_REG_IDX_N2, DSP563XX_REG_IDX_N3, DSP563XX_REG_IDX_N4, DSP563XX_REG_IDX_N5,
337 DSP563XX_REG_IDX_N6, DSP563XX_REG_IDX_N7, DSP563XX_REG_IDX_M0, DSP563XX_REG_IDX_M1,
338 DSP563XX_REG_IDX_M2, DSP563XX_REG_IDX_M3, DSP563XX_REG_IDX_M4, DSP563XX_REG_IDX_M5,
339 DSP563XX_REG_IDX_M6, DSP563XX_REG_IDX_M7,
340 };
341
342 static int dsp563xx_get_gdb_reg_list(struct target *target,
343 struct reg **reg_list[],
344 int *reg_list_size,
345 enum target_register_class reg_class)
346 {
347 int i;
348 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
349
350 if (target->state != TARGET_HALTED)
351 return ERROR_TARGET_NOT_HALTED;
352
353 *reg_list_size = DSP563XX_NUMCOREREGS;
354 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
355
356 if (!*reg_list)
357 return ERROR_COMMAND_SYNTAX_ERROR;
358
359 for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
360 (*reg_list)[i] = &dsp563xx->core_cache->reg_list[gdb_reg_list_idx[i]];
361
362 return ERROR_OK;
363
364 }
365
366 static int dsp563xx_read_core_reg(struct target *target, int num)
367 {
368 uint32_t reg_value;
369 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
370
371 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
372 return ERROR_COMMAND_SYNTAX_ERROR;
373
374 reg_value = dsp563xx->core_regs[num];
375 buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
376 dsp563xx->core_cache->reg_list[num].valid = true;
377 dsp563xx->core_cache->reg_list[num].dirty = false;
378
379 return ERROR_OK;
380 }
381
382 static int dsp563xx_write_core_reg(struct target *target, int num)
383 {
384 uint32_t reg_value;
385 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
386
387 if ((num < 0) || (num >= DSP563XX_NUMCOREREGS))
388 return ERROR_COMMAND_SYNTAX_ERROR;
389
390 reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
391 dsp563xx->core_regs[num] = reg_value;
392 dsp563xx->core_cache->reg_list[num].valid = true;
393 dsp563xx->core_cache->reg_list[num].dirty = false;
394
395 return ERROR_OK;
396 }
397
398 static int dsp563xx_get_core_reg(struct reg *reg)
399 {
400 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
401 struct target *target = dsp563xx_reg->target;
402 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
403
404 LOG_DEBUG("%s", __func__);
405
406 if (target->state != TARGET_HALTED)
407 return ERROR_TARGET_NOT_HALTED;
408
409 return dsp563xx->read_core_reg(target, dsp563xx_reg->num);
410 }
411
412 static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
413 {
414 LOG_DEBUG("%s", __func__);
415
416 struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info;
417 struct target *target = dsp563xx_reg->target;
418 uint32_t value = buf_get_u32(buf, 0, 32);
419
420 if (target->state != TARGET_HALTED)
421 return ERROR_TARGET_NOT_HALTED;
422
423 buf_set_u32(reg->value, 0, reg->size, value);
424 reg->dirty = true;
425 reg->valid = true;
426
427 return ERROR_OK;
428 }
429
430 static const struct reg_arch_type dsp563xx_reg_type = {
431 .get = dsp563xx_get_core_reg,
432 .set = dsp563xx_set_core_reg,
433 };
434
435 static void dsp563xx_build_reg_cache(struct target *target)
436 {
437 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
438
439 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
440 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
441 struct reg *reg_list = calloc(DSP563XX_NUMCOREREGS, sizeof(struct reg));
442 struct dsp563xx_core_reg *arch_info = malloc(
443 sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS);
444 int i;
445
446 /* Build the process context cache */
447 cache->name = "dsp563xx registers";
448 cache->next = NULL;
449 cache->reg_list = reg_list;
450 cache->num_regs = DSP563XX_NUMCOREREGS;
451 (*cache_p) = cache;
452 dsp563xx->core_cache = cache;
453
454 for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
455 arch_info[i].num = dsp563xx_regs[i].id;
456 arch_info[i].name = dsp563xx_regs[i].name;
457 arch_info[i].size = dsp563xx_regs[i].bits;
458 arch_info[i].eame = dsp563xx_regs[i].eame;
459 arch_info[i].instr_mask = dsp563xx_regs[i].instr_mask;
460 arch_info[i].target = target;
461 arch_info[i].dsp563xx_common = dsp563xx;
462 reg_list[i].name = dsp563xx_regs[i].name;
463 reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */
464 reg_list[i].value = calloc(1, 4);
465 reg_list[i].dirty = false;
466 reg_list[i].valid = false;
467 reg_list[i].exist = true;
468 reg_list[i].type = &dsp563xx_reg_type;
469 reg_list[i].arch_info = &arch_info[i];
470 }
471 }
472
473 static int dsp563xx_read_register(struct target *target, int num, int force);
474 static int dsp563xx_write_register(struct target *target, int num, int force);
475
476 static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t *data)
477 {
478 int err;
479 uint32_t instr;
480 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
481
482 /* we use r0 to store temporary data */
483 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
484 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
485
486 /* move source memory to r0 */
487 instr = INSTR_MOVEP_REG_HIO(MEM_X, 0, EAME_R0, instr_mask);
488 err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr);
489 if (err != ERROR_OK)
490 return err;
491 /* move r0 to debug register */
492 instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, 0xfffffc);
493 err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr);
494 if (err != ERROR_OK)
495 return err;
496 /* read debug register */
497 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data);
498 if (err != ERROR_OK)
499 return err;
500 /* r0 is no longer valid on target */
501 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
502
503 return ERROR_OK;
504 }
505
506 static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask, uint32_t data)
507 {
508 int err;
509 uint32_t instr;
510 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
511
512 /* we use r0 to store temporary data */
513 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
514 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
515
516 /* move data to r0 */
517 err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x60F400, data);
518 if (err != ERROR_OK)
519 return err;
520 /* move r0 to destination memory */
521 instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, instr_mask);
522 err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr);
523 if (err != ERROR_OK)
524 return err;
525
526 /* r0 is no longer valid on target */
527 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
528
529 return ERROR_OK;
530 }
531
532 static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t *data)
533 {
534 int err;
535 uint32_t instr;
536
537 instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, eame, 0xfffffc);
538 err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr);
539 if (err != ERROR_OK)
540 return err;
541 /* nop */
542 err = dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000);
543 if (err != ERROR_OK)
544 return err;
545 /* read debug register */
546 return dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data);
547 }
548
549 static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32_t data)
550 {
551 int err;
552
553 err = dsp563xx_once_execute_dw_ir(target->tap, 0, instr_mask, data);
554 if (err != ERROR_OK)
555 return err;
556 /* nop */
557 return dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000);
558 }
559
560 static int dsp563xx_reg_pc_read(struct target *target)
561 {
562 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
563
564 /* pc was changed, nothing todo */
565 if (dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty)
566 return ERROR_OK;
567
568 /* conditional branch check */
569 if (once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg) {
570 if ((once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0) {
571 LOG_DEBUG("%s conditional branch not supported yet (0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 ")",
572 __func__,
573 (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1),
574 once_regs[ONCE_REG_IDX_OPABDR].reg,
575 once_regs[ONCE_REG_IDX_OPABEX].reg);
576
577 /* TODO: use disassembly to set correct pc offset
578 * read 2 words from OPABF11 and disasm the instruction
579 */
580 dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
581 (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1) & 0x00FFFFFF;
582 } else {
583 if (once_regs[ONCE_REG_IDX_OPABEX].reg ==
584 once_regs[ONCE_REG_IDX_OPABFR].reg)
585 dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
586 once_regs[ONCE_REG_IDX_OPABEX].reg;
587 else
588 dsp563xx->core_regs[DSP563XX_REG_IDX_PC] =
589 once_regs[ONCE_REG_IDX_OPABEX].reg - 1;
590 }
591 } else
592 dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg;
593
594 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_PC);
595
596 return ERROR_OK;
597 }
598
599 static int dsp563xx_reg_ssh_read(struct target *target)
600 {
601 int err;
602 uint32_t sp;
603 struct dsp563xx_core_reg *arch_info;
604 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
605
606 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
607
608 /* get a valid stack pointer */
609 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
610 if (err != ERROR_OK)
611 return err;
612 sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
613 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 0);
614 if (err != ERROR_OK)
615 return err;
616
617 /* get a valid stack count */
618 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SC, 0);
619 if (err != ERROR_OK)
620 return err;
621
622 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 0);
623 if (err != ERROR_OK)
624 return err;
625
626 /* get a valid extended pointer */
627 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_EP, 0);
628 if (err != ERROR_OK)
629 return err;
630
631 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 0);
632 if (err != ERROR_OK)
633 return err;
634
635 if (!sp)
636 sp = 0x00FFFFFF;
637 else {
638 err = dsp563xx_reg_read(target, arch_info->eame, &sp);
639 if (err != ERROR_OK)
640 return err;
641
642 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 1);
643 if (err != ERROR_OK)
644 return err;
645 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1);
646 if (err != ERROR_OK)
647 return err;
648 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 1);
649 if (err != ERROR_OK)
650 return err;
651 }
652
653 dsp563xx->core_regs[DSP563XX_REG_IDX_SSH] = sp;
654 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSH);
655
656 return ERROR_OK;
657 }
658
659 static int dsp563xx_reg_ssh_write(struct target *target)
660 {
661 int err;
662 uint32_t sp;
663 struct dsp563xx_core_reg *arch_info;
664 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
665
666 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info;
667
668 /* get a valid stack pointer */
669 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
670 if (err != ERROR_OK)
671 return err;
672 sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
673
674 if (sp) {
675 sp--;
676 /* write new stackpointer */
677 dsp563xx->core_regs[DSP563XX_REG_IDX_SP] = sp;
678 err = dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SP);
679 if (err != ERROR_OK)
680 return err;
681 err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1);
682 if (err != ERROR_OK)
683 return err;
684
685 err = dsp563xx_reg_write(target, arch_info->instr_mask,
686 dsp563xx->core_regs[DSP563XX_REG_IDX_SSH]);
687 if (err != ERROR_OK)
688 return err;
689
690 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 1);
691 if (err != ERROR_OK)
692 return err;
693 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SSH, 1);
694 if (err != ERROR_OK)
695 return err;
696 }
697
698 return ERROR_OK;
699 }
700
701 static int dsp563xx_reg_ssl_read(struct target *target)
702 {
703 int err;
704 uint32_t sp;
705 struct dsp563xx_core_reg *arch_info;
706 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
707
708 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info;
709
710 /* get a valid stack pointer */
711 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0);
712 if (err != ERROR_OK)
713 return err;
714 sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP];
715
716 if (!sp)
717 sp = 0x00FFFFFF;
718 else {
719 err = dsp563xx_reg_read(target, arch_info->eame, &sp);
720 if (err != ERROR_OK)
721 return err;
722 }
723
724 dsp563xx->core_regs[DSP563XX_REG_IDX_SSL] = sp;
725 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SSL);
726
727 return ERROR_OK;
728 }
729
730 static int dsp563xx_read_register(struct target *target, int num, int force)
731 {
732 int err = ERROR_OK;
733 uint32_t data = 0;
734 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
735 struct dsp563xx_core_reg *arch_info;
736
737 if (force)
738 dsp563xx->core_cache->reg_list[num].valid = false;
739
740 if (!dsp563xx->core_cache->reg_list[num].valid) {
741 arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
742
743 switch (arch_info->num) {
744 case DSP563XX_REG_IDX_SSH:
745 err = dsp563xx_reg_ssh_read(target);
746 break;
747 case DSP563XX_REG_IDX_SSL:
748 err = dsp563xx_reg_ssl_read(target);
749 break;
750 case DSP563XX_REG_IDX_PC:
751 err = dsp563xx_reg_pc_read(target);
752 break;
753 case DSP563XX_REG_IDX_IPRC:
754 case DSP563XX_REG_IDX_IPRP:
755 case DSP563XX_REG_IDX_BCR:
756 case DSP563XX_REG_IDX_DCR:
757 case DSP563XX_REG_IDX_AAR0:
758 case DSP563XX_REG_IDX_AAR1:
759 case DSP563XX_REG_IDX_AAR2:
760 case DSP563XX_REG_IDX_AAR3:
761 err = dsp563xx_reg_read_high_io(target,
762 arch_info->instr_mask, &data);
763 if (err == ERROR_OK) {
764 dsp563xx->core_regs[num] = data;
765 dsp563xx->read_core_reg(target, num);
766 }
767 break;
768 default:
769 err = dsp563xx_reg_read(target, arch_info->eame, &data);
770 if (err == ERROR_OK) {
771 dsp563xx->core_regs[num] = data;
772 dsp563xx->read_core_reg(target, num);
773 }
774 break;
775 }
776 }
777
778 return err;
779 }
780
781 static int dsp563xx_write_register(struct target *target, int num, int force)
782 {
783 int err = ERROR_OK;
784 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
785 struct dsp563xx_core_reg *arch_info;
786
787 if (force)
788 dsp563xx->core_cache->reg_list[num].dirty = true;
789
790 if (dsp563xx->core_cache->reg_list[num].dirty) {
791 arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
792
793 dsp563xx->write_core_reg(target, num);
794
795 switch (arch_info->num) {
796 case DSP563XX_REG_IDX_SSH:
797 err = dsp563xx_reg_ssh_write(target);
798 break;
799 case DSP563XX_REG_IDX_PC:
800 /* pc is updated on resume, no need to write it here */
801 break;
802 case DSP563XX_REG_IDX_IPRC:
803 case DSP563XX_REG_IDX_IPRP:
804 case DSP563XX_REG_IDX_BCR:
805 case DSP563XX_REG_IDX_DCR:
806 case DSP563XX_REG_IDX_AAR0:
807 case DSP563XX_REG_IDX_AAR1:
808 case DSP563XX_REG_IDX_AAR2:
809 case DSP563XX_REG_IDX_AAR3:
810 err = dsp563xx_reg_write_high_io(target,
811 arch_info->instr_mask,
812 dsp563xx->core_regs[num]);
813 break;
814 default:
815 err = dsp563xx_reg_write(target,
816 arch_info->instr_mask,
817 dsp563xx->core_regs[num]);
818
819 if ((err == ERROR_OK) && (arch_info->num == DSP563XX_REG_IDX_SP)) {
820 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid =
821 0;
822 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid =
823 0;
824 }
825
826 break;
827 }
828 }
829
830 return err;
831 }
832
833 static int dsp563xx_save_context(struct target *target)
834 {
835 int i, err = ERROR_OK;
836
837 for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
838 err = dsp563xx_read_register(target, i, 0);
839 if (err != ERROR_OK)
840 break;
841 }
842
843 return err;
844 }
845
846 static int dsp563xx_restore_context(struct target *target)
847 {
848 int i, err = ERROR_OK;
849
850 for (i = 0; i < DSP563XX_NUMCOREREGS; i++) {
851 err = dsp563xx_write_register(target, i, 0);
852 if (err != ERROR_OK)
853 break;
854 }
855
856 return err;
857 }
858
859 static void dsp563xx_invalidate_x_context(struct target *target,
860 uint32_t addr_start,
861 uint32_t addr_end)
862 {
863 int i;
864 struct dsp563xx_core_reg *arch_info;
865 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
866
867 if (addr_start > ASM_REG_W_IPRC)
868 return;
869 if (addr_start < ASM_REG_W_AAR3)
870 return;
871
872 for (i = DSP563XX_REG_IDX_IPRC; i < DSP563XX_NUMCOREREGS; i++) {
873 arch_info = dsp563xx->core_cache->reg_list[i].arch_info;
874
875 if ((arch_info->instr_mask >= addr_start) &&
876 (arch_info->instr_mask <= addr_end)) {
877 dsp563xx->core_cache->reg_list[i].valid = false;
878 dsp563xx->core_cache->reg_list[i].dirty = false;
879 }
880 }
881 }
882
883 static int dsp563xx_target_create(struct target *target, Jim_Interp *interp)
884 {
885 struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common));
886
887 if (!dsp563xx)
888 return ERROR_COMMAND_SYNTAX_ERROR;
889
890 dsp563xx->jtag_info.tap = target->tap;
891 target->arch_info = dsp563xx;
892 dsp563xx->read_core_reg = dsp563xx_read_core_reg;
893 dsp563xx->write_core_reg = dsp563xx_write_core_reg;
894
895 return ERROR_OK;
896 }
897
898 static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target)
899 {
900 LOG_DEBUG("%s", __func__);
901
902 dsp563xx_build_reg_cache(target);
903 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
904
905 dsp563xx->hardware_breakpoints_cleared = false;
906 dsp563xx->hardware_breakpoint[0].used = BPU_NONE;
907
908 return ERROR_OK;
909 }
910
911 static int dsp563xx_examine(struct target *target)
912 {
913 uint32_t chip;
914
915 if (!target->tap->has_idcode) {
916 LOG_ERROR("no IDCODE present on device");
917 return ERROR_COMMAND_SYNTAX_ERROR;
918 }
919
920 if (!target_was_examined(target)) {
921 target_set_examined(target);
922
923 /* examine core and chip derivate number */
924 chip = (target->tap->idcode>>12) & 0x3ff;
925 /* core number 0 means DSP563XX */
926 if (((chip>>5)&0x1f) == 0)
927 chip += 300;
928
929 LOG_INFO("DSP56%03" PRIu32 " device found", chip);
930
931 /* Clear all breakpoints */
932 dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
933 }
934
935 return ERROR_OK;
936 }
937
938 static int dsp563xx_arch_state(struct target *target)
939 {
940 LOG_DEBUG("%s", __func__);
941 return ERROR_OK;
942 }
943
944 #define DSP563XX_SR_SA (1<<17)
945 #define DSP563XX_SR_SC (1<<13)
946
947 static int dsp563xx_debug_once_init(struct target *target)
948 {
949 return dsp563xx_once_read_register(target->tap, 1, once_regs, DSP563XX_NUMONCEREGS);
950 }
951
952 static int dsp563xx_debug_init(struct target *target)
953 {
954 int err;
955 uint32_t sr;
956 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
957 struct dsp563xx_core_reg *arch_info;
958
959 err = dsp563xx_debug_once_init(target);
960 if (err != ERROR_OK)
961 return err;
962
963 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info;
964
965 /* check 24bit mode */
966 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SR, 0);
967 if (err != ERROR_OK)
968 return err;
969
970 sr = dsp563xx->core_regs[DSP563XX_REG_IDX_SR];
971
972 if (sr & (DSP563XX_SR_SA | DSP563XX_SR_SC)) {
973 sr &= ~(DSP563XX_SR_SA | DSP563XX_SR_SC);
974
975 err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr);
976 if (err != ERROR_OK)
977 return err;
978 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
979 }
980
981 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0);
982 if (err != ERROR_OK)
983 return err;
984 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N1, 0);
985 if (err != ERROR_OK)
986 return err;
987 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M0, 0);
988 if (err != ERROR_OK)
989 return err;
990 err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M1, 0);
991 if (err != ERROR_OK)
992 return err;
993
994 if (dsp563xx->core_regs[DSP563XX_REG_IDX_N0] != 0x000000) {
995 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info;
996 err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000);
997 if (err != ERROR_OK)
998 return err;
999 }
1000 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
1001
1002 if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) {
1003 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
1004 err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000);
1005 if (err != ERROR_OK)
1006 return err;
1007 }
1008 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
1009
1010 if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) {
1011 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
1012 err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff);
1013 if (err != ERROR_OK)
1014 return err;
1015 }
1016 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
1017
1018 if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) {
1019 arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
1020 err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff);
1021 if (err != ERROR_OK)
1022 return err;
1023 }
1024 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
1025
1026 err = dsp563xx_save_context(target);
1027 if (err != ERROR_OK)
1028 return err;
1029
1030 return ERROR_OK;
1031 }
1032
1033 static int dsp563xx_jtag_debug_request(struct target *target)
1034 {
1035 return dsp563xx_once_request_debug(target->tap, target->state == TARGET_RESET);
1036 }
1037
1038 static int dsp563xx_poll(struct target *target)
1039 {
1040 int err;
1041 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1042 uint32_t once_status = 0;
1043 int state;
1044
1045 state = dsp563xx_once_target_status(target->tap);
1046
1047 if (state == TARGET_UNKNOWN) {
1048 target->state = state;
1049 LOG_ERROR("jtag status contains invalid mode value - communication failure");
1050 return ERROR_TARGET_FAILURE;
1051 }
1052
1053 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status);
1054 if (err != ERROR_OK)
1055 return err;
1056
1057 if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) {
1058 if (target->state != TARGET_HALTED) {
1059 target->state = TARGET_HALTED;
1060
1061 err = dsp563xx_debug_init(target);
1062 if (err != ERROR_OK)
1063 return err;
1064
1065 if (once_status & (DSP563XX_ONCE_OSCR_MBO|DSP563XX_ONCE_OSCR_SWO))
1066 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1067 else
1068 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1069
1070 LOG_DEBUG("target->state: %s (%" PRIx32 ")", target_state_name(target), once_status);
1071 LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
1072 }
1073 }
1074
1075 if (!dsp563xx->hardware_breakpoints_cleared) {
1076 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
1077 if (err != ERROR_OK)
1078 return err;
1079
1080 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR0, 0);
1081 if (err != ERROR_OK)
1082 return err;
1083
1084 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR1, 0);
1085 if (err != ERROR_OK)
1086 return err;
1087
1088 dsp563xx->hardware_breakpoints_cleared = true;
1089 }
1090
1091 return ERROR_OK;
1092 }
1093
1094 static int dsp563xx_halt(struct target *target)
1095 {
1096 int err;
1097
1098 LOG_DEBUG("%s", __func__);
1099
1100 if (target->state == TARGET_HALTED) {
1101 LOG_DEBUG("target was already halted");
1102 return ERROR_OK;
1103 }
1104
1105 if (target->state == TARGET_UNKNOWN)
1106 LOG_WARNING("target was in unknown state when halt was requested");
1107
1108 err = dsp563xx_jtag_debug_request(target);
1109 if (err != ERROR_OK)
1110 return err;
1111
1112 target->debug_reason = DBG_REASON_DBGRQ;
1113
1114 return ERROR_OK;
1115 }
1116
1117 static int dsp563xx_resume(struct target *target,
1118 int current,
1119 target_addr_t address,
1120 int handle_breakpoints,
1121 int debug_execution)
1122 {
1123 int err;
1124 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1125
1126 /* check if pc was changed and resume want to execute the next address
1127 * if pc was changed from gdb or other interface we will
1128 * jump to this address and don't execute the next address
1129 * this will not affect the resume command with an address argument
1130 * because current is set to zero then
1131 */
1132 if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
1133 dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
1134 address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
1135 current = 0;
1136 }
1137
1138 LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
1139
1140 err = dsp563xx_restore_context(target);
1141 if (err != ERROR_OK)
1142 return err;
1143 register_cache_invalidate(dsp563xx->core_cache);
1144
1145 if (current) {
1146 /* restore pipeline registers and go */
1147 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR,
1148 once_regs[ONCE_REG_IDX_OPILR].reg);
1149 if (err != ERROR_OK)
1150 return err;
1151 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR |
1152 DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1153 once_regs[ONCE_REG_IDX_OPDBR].reg);
1154 if (err != ERROR_OK)
1155 return err;
1156 } else {
1157 /* set to go register and jump */
1158 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP);
1159 if (err != ERROR_OK)
1160 return err;
1161 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO |
1162 DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address);
1163 if (err != ERROR_OK)
1164 return err;
1165 }
1166
1167 target->state = TARGET_RUNNING;
1168
1169 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1170
1171 return ERROR_OK;
1172 }
1173
1174 static int dsp563xx_step_ex(struct target *target,
1175 int current,
1176 uint32_t address,
1177 int handle_breakpoints,
1178 int steps)
1179 {
1180 int err;
1181 uint32_t once_status;
1182 uint32_t dr_in, cnt;
1183 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1184
1185 if (target->state != TARGET_HALTED) {
1186 LOG_DEBUG("target was not halted");
1187 return ERROR_OK;
1188 }
1189
1190 /* check if pc was changed and step want to execute the next address
1191 * if pc was changed from gdb or other interface we will
1192 * jump to this address and don't execute the next address
1193 * this will not affect the step command with an address argument
1194 * because current is set to zero then
1195 */
1196 if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
1197 dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
1198 address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
1199 current = 0;
1200 }
1201
1202 LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
1203
1204 err = dsp563xx_jtag_debug_request(target);
1205 if (err != ERROR_OK)
1206 return err;
1207 err = dsp563xx_restore_context(target);
1208 if (err != ERROR_OK)
1209 return err;
1210
1211 /* reset trace mode */
1212 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000);
1213 if (err != ERROR_OK)
1214 return err;
1215 /* enable trace mode */
1216 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME);
1217 if (err != ERROR_OK)
1218 return err;
1219
1220 cnt = steps;
1221
1222 /* on JUMP we need one extra cycle */
1223 if (!current)
1224 cnt++;
1225
1226 /* load step counter with N-1 */
1227 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, cnt);
1228 if (err != ERROR_OK)
1229 return err;
1230
1231 if (current) {
1232 /* restore pipeline registers and go */
1233 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR,
1234 once_regs[ONCE_REG_IDX_OPILR].reg);
1235 if (err != ERROR_OK)
1236 return err;
1237 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR |
1238 DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1239 once_regs[ONCE_REG_IDX_OPDBR].reg);
1240 if (err != ERROR_OK)
1241 return err;
1242 } else {
1243 /* set to go register and jump */
1244 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP);
1245 if (err != ERROR_OK)
1246 return err;
1247 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO |
1248 DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO,
1249 address);
1250 if (err != ERROR_OK)
1251 return err;
1252 }
1253
1254 while (1) {
1255 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status);
1256 if (err != ERROR_OK)
1257 return err;
1258
1259 if (once_status & DSP563XX_ONCE_OSCR_TO) {
1260 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in);
1261 if (err != ERROR_OK)
1262 return err;
1263 LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff);
1264 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in);
1265 if (err != ERROR_OK)
1266 return err;
1267 LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff);
1268 err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in);
1269 if (err != ERROR_OK)
1270 return err;
1271 LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff);
1272
1273 /* reset trace mode */
1274 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000);
1275 if (err != ERROR_OK)
1276 return err;
1277
1278 register_cache_invalidate(dsp563xx->core_cache);
1279 err = dsp563xx_debug_init(target);
1280 if (err != ERROR_OK)
1281 return err;
1282
1283 break;
1284 }
1285 }
1286
1287 return ERROR_OK;
1288 }
1289
1290 static int dsp563xx_step(struct target *target,
1291 int current,
1292 target_addr_t address,
1293 int handle_breakpoints)
1294 {
1295 int err;
1296 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1297
1298 if (target->state != TARGET_HALTED) {
1299 LOG_TARGET_ERROR(target, "not halted");
1300 return ERROR_TARGET_NOT_HALTED;
1301 }
1302
1303 err = dsp563xx_step_ex(target, current, address, handle_breakpoints, 0);
1304 if (err != ERROR_OK)
1305 return err;
1306
1307 target->debug_reason = DBG_REASON_SINGLESTEP;
1308 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1309
1310 LOG_INFO("halted: PC: 0x%" PRIx32, dsp563xx->core_regs[DSP563XX_REG_IDX_PC]);
1311
1312 return err;
1313 }
1314
1315 static int dsp563xx_assert_reset(struct target *target)
1316 {
1317 int retval = 0;
1318 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1319 enum reset_types jtag_reset_config = jtag_get_reset_config();
1320
1321 if (jtag_reset_config & RESET_HAS_SRST) {
1322 /* default to asserting srst */
1323 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1324 jtag_add_reset(1, 1);
1325 else
1326 jtag_add_reset(0, 1);
1327 }
1328
1329 target->state = TARGET_RESET;
1330 jtag_add_sleep(5000);
1331
1332 /* registers are now invalid */
1333 register_cache_invalidate(dsp563xx->core_cache);
1334
1335 if (target->reset_halt) {
1336 retval = target_halt(target);
1337 if (retval != ERROR_OK)
1338 return retval;
1339 }
1340
1341 LOG_DEBUG("%s", __func__);
1342 return ERROR_OK;
1343 }
1344
1345 static int dsp563xx_deassert_reset(struct target *target)
1346 {
1347 int err;
1348
1349 /* deassert reset lines */
1350 jtag_add_reset(0, 0);
1351
1352 err = dsp563xx_poll(target);
1353 if (err != ERROR_OK)
1354 return err;
1355
1356 if (target->reset_halt) {
1357 if (target->state == TARGET_HALTED) {
1358 /* after a reset the cpu jmp to the
1359 * reset vector and need 2 cycles to fill
1360 * the cache (fetch,decode,execute)
1361 */
1362 err = dsp563xx_step_ex(target, 1, 0, 1, 1);
1363 if (err != ERROR_OK)
1364 return err;
1365 }
1366 } else
1367 target->state = TARGET_RUNNING;
1368
1369 LOG_DEBUG("%s", __func__);
1370 return ERROR_OK;
1371 }
1372
1373 static int dsp563xx_run_algorithm(struct target *target,
1374 int num_mem_params, struct mem_param *mem_params,
1375 int num_reg_params, struct reg_param *reg_params,
1376 target_addr_t entry_point, target_addr_t exit_point,
1377 unsigned int timeout_ms, void *arch_info)
1378 {
1379 int i;
1380 int retval = ERROR_OK;
1381 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1382
1383 if (target->state != TARGET_HALTED) {
1384 LOG_TARGET_ERROR(target, "not halted (run target algo)");
1385 return ERROR_TARGET_NOT_HALTED;
1386 }
1387
1388 for (i = 0; i < num_mem_params; i++) {
1389 if (mem_params[i].direction == PARAM_IN)
1390 continue;
1391 retval = target_write_buffer(target, mem_params[i].address,
1392 mem_params[i].size, mem_params[i].value);
1393 if (retval != ERROR_OK)
1394 return retval;
1395 }
1396
1397 for (i = 0; i < num_reg_params; i++) {
1398 if (reg_params[i].direction == PARAM_IN)
1399 continue;
1400
1401 struct reg *reg = register_get_by_name(dsp563xx->core_cache,
1402 reg_params[i].reg_name,
1403 false);
1404
1405 if (!reg) {
1406 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1407 continue;
1408 }
1409
1410 if (reg->size != reg_params[i].size) {
1411 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1412 reg_params[i].reg_name);
1413 continue;
1414 }
1415
1416 retval = dsp563xx_set_core_reg(reg, reg_params[i].value);
1417 if (retval != ERROR_OK)
1418 return retval;
1419 }
1420
1421 /* exec */
1422 retval = target_resume(target, 0, entry_point, 1, 1);
1423 if (retval != ERROR_OK)
1424 return retval;
1425
1426 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1427 if (retval != ERROR_OK)
1428 return retval;
1429
1430 for (i = 0; i < num_mem_params; i++) {
1431 if (mem_params[i].direction != PARAM_OUT)
1432 retval = target_read_buffer(target,
1433 mem_params[i].address,
1434 mem_params[i].size,
1435 mem_params[i].value);
1436 if (retval != ERROR_OK)
1437 return retval;
1438 }
1439
1440 for (i = 0; i < num_reg_params; i++) {
1441 if (reg_params[i].direction != PARAM_OUT) {
1442
1443 struct reg *reg = register_get_by_name(dsp563xx->core_cache,
1444 reg_params[i].reg_name,
1445 false);
1446 if (!reg) {
1447 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1448 continue;
1449 }
1450
1451 if (reg->size != reg_params[i].size) {
1452 LOG_ERROR(
1453 "BUG: register '%s' size doesn't match reg_params[i].size",
1454 reg_params[i].reg_name);
1455 continue;
1456 }
1457
1458 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1459 }
1460 }
1461
1462 return ERROR_OK;
1463 }
1464
1465 /* global command context from openocd.c */
1466 extern struct command_context *global_cmd_ctx;
1467
1468 static int dsp563xx_get_default_memory(void)
1469 {
1470 Jim_Interp *interp;
1471 Jim_Obj *memspace;
1472 char *c;
1473
1474 if (!global_cmd_ctx)
1475 return MEM_P;
1476
1477 interp = global_cmd_ctx->interp;
1478
1479 if (!interp)
1480 return MEM_P;
1481
1482 memspace = Jim_GetGlobalVariableStr(interp, "memspace", JIM_NONE);
1483
1484 if (!memspace)
1485 return MEM_P;
1486
1487 c = (char *)Jim_GetString(memspace, NULL);
1488
1489 if (!c)
1490 return MEM_P;
1491
1492 switch (c[0]) {
1493 case '1':
1494 return MEM_X;
1495 case '2':
1496 return MEM_Y;
1497 case '3':
1498 return MEM_L;
1499 default:
1500 break;
1501 }
1502
1503 return MEM_P;
1504 }
1505
1506 static int dsp563xx_read_memory_core(struct target *target,
1507 int mem_type,
1508 uint32_t address,
1509 uint32_t size,
1510 uint32_t count,
1511 uint8_t *buffer)
1512 {
1513 int err;
1514 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1515 uint32_t i, x;
1516 uint32_t data, move_cmd = 0;
1517 uint8_t *b;
1518
1519 LOG_DEBUG(
1520 "memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1521 mem_type,
1522 address,
1523 size,
1524 count);
1525
1526 if (target->state != TARGET_HALTED) {
1527 LOG_WARNING("target not halted");
1528 return ERROR_TARGET_NOT_HALTED;
1529 }
1530
1531 switch (mem_type) {
1532 case MEM_X:
1533 /* TODO: mark effected queued registers */
1534 move_cmd = 0x61d800;
1535 break;
1536 case MEM_Y:
1537 move_cmd = 0x69d800;
1538 break;
1539 case MEM_P:
1540 move_cmd = 0x07d891;
1541 break;
1542 default:
1543 return ERROR_COMMAND_SYNTAX_ERROR;
1544 }
1545
1546 /* we use r0 to store temporary data */
1547 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
1548 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
1549 /* we use r1 to store temporary data */
1550 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
1551 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
1552
1553 /* r0 is no longer valid on target */
1554 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
1555 /* r1 is no longer valid on target */
1556 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
1557
1558 x = count;
1559 b = buffer;
1560
1561 err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address);
1562 if (err != ERROR_OK)
1563 return err;
1564
1565 for (i = 0; i < x; i++) {
1566 err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd);
1567 if (err != ERROR_OK)
1568 return err;
1569 err = dsp563xx_once_execute_sw_ir(target->tap, 0, 0x08D13C);
1570 if (err != ERROR_OK)
1571 return err;
1572 err = dsp563xx_once_reg_read(target->tap, 0,
1573 DSP563XX_ONCE_OGDBR, (uint32_t *)(void *)b);
1574 if (err != ERROR_OK)
1575 return err;
1576 b += 4;
1577 }
1578
1579 /* flush the jtag queue */
1580 err = jtag_execute_queue();
1581 if (err != ERROR_OK)
1582 return err;
1583
1584 /* walk over the buffer and fix target endianness */
1585 b = buffer;
1586
1587 for (i = 0; i < x; i++) {
1588 data = buf_get_u32(b, 0, 32) & 0x00FFFFFF;
1589 /* LOG_DEBUG("R: %08X", *((uint32_t*)b)); */
1590 target_buffer_set_u32(target, b, data);
1591 b += 4;
1592 }
1593
1594 return ERROR_OK;
1595 }
1596
1597 static int dsp563xx_read_memory(struct target *target,
1598 int mem_type,
1599 target_addr_t address,
1600 uint32_t size,
1601 uint32_t count,
1602 uint8_t *buffer)
1603 {
1604 int err;
1605 uint32_t i, i1;
1606 uint8_t *buffer_y, *buffer_x;
1607
1608 /* if size equals zero we are called from target read memory
1609 * and have to handle the parameter here */
1610 if ((size == 0) && (count != 0)) {
1611 size = count % 4;
1612
1613 if (size)
1614 LOG_DEBUG("size is not aligned to 4 byte");
1615
1616 count = (count - size) / 4;
1617 size = 4;
1618 }
1619
1620 /* we only support 4 byte aligned data */
1621 if ((size != 4) || (!count))
1622 return ERROR_COMMAND_SYNTAX_ERROR;
1623
1624 if (mem_type != MEM_L)
1625 return dsp563xx_read_memory_core(target, mem_type, address, size, count, buffer);
1626
1627 buffer_y = malloc(size * count);
1628 if (!buffer_y)
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630
1631 buffer_x = malloc(size * count);
1632 if (!buffer_x) {
1633 free(buffer_y);
1634 return ERROR_COMMAND_SYNTAX_ERROR;
1635 }
1636
1637 err = dsp563xx_read_memory_core(target, MEM_Y, address, size, count / 2, buffer_y);
1638
1639 if (err != ERROR_OK) {
1640 free(buffer_y);
1641 free(buffer_x);
1642 return err;
1643 }
1644
1645 err = dsp563xx_read_memory_core(target, MEM_X, address, size, count / 2, buffer_x);
1646
1647 if (err != ERROR_OK) {
1648 free(buffer_y);
1649 free(buffer_x);
1650 return err;
1651 }
1652
1653 for (i = 0, i1 = 0; i < count; i += 2, i1++) {
1654 buf_set_u32(buffer + i*sizeof(uint32_t), 0, 32,
1655 buf_get_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32));
1656 buf_set_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32,
1657 buf_get_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32));
1658 }
1659
1660 free(buffer_y);
1661 free(buffer_x);
1662
1663 return ERROR_OK;
1664 }
1665
1666 static int dsp563xx_read_memory_default(struct target *target,
1667 target_addr_t address,
1668 uint32_t size,
1669 uint32_t count,
1670 uint8_t *buffer)
1671 {
1672
1673 return dsp563xx_read_memory(target,
1674 dsp563xx_get_default_memory(), address, size, count, buffer);
1675 }
1676
1677 static int dsp563xx_read_buffer_default(struct target *target,
1678 target_addr_t address,
1679 uint32_t size,
1680 uint8_t *buffer)
1681 {
1682
1683 return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, 0,
1684 buffer);
1685 }
1686
1687 static int dsp563xx_write_memory_core(struct target *target,
1688 int mem_type,
1689 target_addr_t address,
1690 uint32_t size,
1691 uint32_t count,
1692 const uint8_t *buffer)
1693 {
1694 int err;
1695 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1696 uint32_t i, x;
1697 uint32_t data, move_cmd = 0;
1698 const uint8_t *b;
1699
1700 LOG_DEBUG(
1701 "memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1702 mem_type,
1703 address,
1704 size,
1705 count);
1706
1707 if (target->state != TARGET_HALTED) {
1708 LOG_TARGET_ERROR(target, "not halted");
1709 return ERROR_TARGET_NOT_HALTED;
1710 }
1711
1712 switch (mem_type) {
1713 case MEM_X:
1714 /* invalidate affected x registers */
1715 dsp563xx_invalidate_x_context(target, address, address + count - 1);
1716 move_cmd = 0x615800;
1717 break;
1718 case MEM_Y:
1719 move_cmd = 0x695800;
1720 break;
1721 case MEM_P:
1722 move_cmd = 0x075891;
1723 break;
1724 default:
1725 return ERROR_COMMAND_SYNTAX_ERROR;
1726 }
1727
1728 /* we use r0 to store temporary data */
1729 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].valid)
1730 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0);
1731 /* we use r1 to store temporary data */
1732 if (!dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].valid)
1733 dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
1734
1735 /* r0 is no longer valid on target */
1736 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
1737 /* r1 is no longer valid on target */
1738 dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
1739
1740 x = count;
1741 b = buffer;
1742
1743 err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address);
1744 if (err != ERROR_OK)
1745 return err;
1746
1747 for (i = 0; i < x; i++) {
1748 data = target_buffer_get_u32(target, b);
1749
1750 /* LOG_DEBUG("W: %08X", data); */
1751
1752 data &= 0x00ffffff;
1753
1754 err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x61F400, data);
1755 if (err != ERROR_OK)
1756 return err;
1757 err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd);
1758 if (err != ERROR_OK)
1759 return err;
1760 b += 4;
1761 }
1762
1763 /* flush the jtag queue */
1764 err = jtag_execute_queue();
1765 if (err != ERROR_OK)
1766 return err;
1767
1768 return ERROR_OK;
1769 }
1770
1771 static int dsp563xx_write_memory(struct target *target,
1772 int mem_type,
1773 target_addr_t address,
1774 uint32_t size,
1775 uint32_t count,
1776 const uint8_t *buffer)
1777 {
1778 int err;
1779 uint32_t i, i1;
1780 uint8_t *buffer_y, *buffer_x;
1781
1782 /* if size equals zero we are called from target write memory
1783 * and have to handle the parameter here */
1784 if ((size == 0) && (count != 0)) {
1785 size = count % 4;
1786
1787 if (size)
1788 LOG_DEBUG("size is not aligned to 4 byte");
1789
1790 count = (count - size) / 4;
1791 size = 4;
1792 }
1793
1794 /* we only support 4 byte aligned data */
1795 if ((size != 4) || (!count))
1796 return ERROR_COMMAND_SYNTAX_ERROR;
1797
1798 if (mem_type != MEM_L)
1799 return dsp563xx_write_memory_core(target, mem_type, address, size, count, buffer);
1800
1801 buffer_y = malloc(size * count);
1802 if (!buffer_y)
1803 return ERROR_COMMAND_SYNTAX_ERROR;
1804
1805 buffer_x = malloc(size * count);
1806 if (!buffer_x) {
1807 free(buffer_y);
1808 return ERROR_COMMAND_SYNTAX_ERROR;
1809 }
1810
1811 for (i = 0, i1 = 0; i < count; i += 2, i1++) {
1812 buf_set_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32,
1813 buf_get_u32(buffer + i * sizeof(uint32_t), 0, 32));
1814 buf_set_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32,
1815 buf_get_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32));
1816 }
1817
1818 err = dsp563xx_write_memory_core(target, MEM_Y, address, size, count / 2, buffer_y);
1819
1820 if (err != ERROR_OK) {
1821 free(buffer_y);
1822 free(buffer_x);
1823 return err;
1824 }
1825
1826 err = dsp563xx_write_memory_core(target, MEM_X, address, size, count / 2, buffer_x);
1827
1828 if (err != ERROR_OK) {
1829 free(buffer_y);
1830 free(buffer_x);
1831 return err;
1832 }
1833
1834 free(buffer_y);
1835 free(buffer_x);
1836
1837 return ERROR_OK;
1838 }
1839
1840 static int dsp563xx_write_memory_default(struct target *target,
1841 target_addr_t address,
1842 uint32_t size,
1843 uint32_t count,
1844 const uint8_t *buffer)
1845 {
1846 return dsp563xx_write_memory(target,
1847 dsp563xx_get_default_memory(), address, size, count, buffer);
1848 }
1849
1850 static int dsp563xx_write_buffer_default(struct target *target,
1851 target_addr_t address,
1852 uint32_t size,
1853 const uint8_t *buffer)
1854 {
1855 return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, 0,
1856 buffer);
1857 }
1858
1859 /*
1860 * Exit with error here, because we support watchpoints over a custom command.
1861 * This is because the DSP has separate X,Y,P memspace which is not compatible to the
1862 * traditional watchpoint logic.
1863 */
1864 static int dsp563xx_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1865 {
1866 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1867 }
1868
1869 /*
1870 * @see dsp563xx_add_watchpoint
1871 */
1872 static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1873 {
1874 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1875 }
1876
1877 static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t mem_type,
1878 enum watchpoint_rw rw, enum watchpoint_condition cond)
1879 {
1880 int err = ERROR_OK;
1881 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1882
1883 bool was_running = false;
1884 /* Only set breakpoint when halted */
1885 if (target->state != TARGET_HALTED) {
1886 dsp563xx_halt(target);
1887 was_running = true;
1888 }
1889
1890 if (dsp563xx->hardware_breakpoint[0].used) {
1891 LOG_ERROR("Cannot add watchpoint. Hardware resource already used.");
1892 err = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1893 }
1894
1895 uint32_t obcr_value = 0;
1896 if (err == ERROR_OK) {
1897 obcr_value |= OBCR_B0_OR_B1;
1898 switch (mem_type) {
1899 case MEM_X:
1900 obcr_value |= OBCR_BP_MEM_X;
1901 break;
1902 case MEM_Y:
1903 obcr_value |= OBCR_BP_MEM_Y;
1904 break;
1905 case MEM_P:
1906 obcr_value |= OBCR_BP_MEM_P;
1907 break;
1908 default:
1909 LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type);
1910 err = ERROR_TARGET_INVALID;
1911 }
1912 }
1913
1914 if (err == ERROR_OK) {
1915 switch (rw) {
1916 case WPT_READ:
1917 obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ);
1918 break;
1919 case WPT_WRITE:
1920 obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE);
1921 break;
1922 case WPT_ACCESS:
1923 obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ|OBCR_BP_ON_WRITE);
1924 break;
1925 default:
1926 LOG_ERROR("Unsupported write mode (%d)", rw);
1927 err = ERROR_TARGET_INVALID;
1928 }
1929 }
1930
1931 if (err == ERROR_OK) {
1932 switch (cond) {
1933 case EQUAL:
1934 obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL);
1935 break;
1936 case NOT_EQUAL:
1937 obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL);
1938 break;
1939 case LESS_THAN:
1940 obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN);
1941 break;
1942 case GREATER:
1943 obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN);
1944 break;
1945 default:
1946 LOG_ERROR("Unsupported condition code (%d)", cond);
1947 err = ERROR_TARGET_INVALID;
1948 }
1949 }
1950
1951 if (err == ERROR_OK)
1952 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR0, address);
1953
1954 if (err == ERROR_OK)
1955 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMLR1, 0x0);
1956
1957 if (err == ERROR_OK)
1958 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, obcr_value);
1959
1960 if (err == ERROR_OK) {
1961 /* You should write the memory breakpoint counter to 0 */
1962 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OMBC, 0);
1963 }
1964
1965 if (err == ERROR_OK) {
1966 /* You should write the memory breakpoint counter to 0 */
1967 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, 0);
1968 }
1969
1970 if (err == ERROR_OK)
1971 dsp563xx->hardware_breakpoint[0].used = BPU_WATCHPOINT;
1972
1973 if (err == ERROR_OK && was_running) {
1974 /* Resume from current PC */
1975 err = dsp563xx_resume(target, 1, 0x0, 0, 0);
1976 }
1977
1978 return err;
1979 }
1980
1981 static int dsp563xx_remove_custom_watchpoint(struct target *target)
1982 {
1983 int err = ERROR_OK;
1984 struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
1985
1986 if (dsp563xx->hardware_breakpoint[0].used != BPU_WATCHPOINT) {
1987 LOG_ERROR("Cannot remove watchpoint, as no watchpoint is currently configured!");
1988 err = ERROR_TARGET_INVALID;
1989 }
1990
1991 if (err == ERROR_OK) {
1992 /* Clear watchpoint by clearing OBCR. */
1993 err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
1994 }
1995
1996 if (err == ERROR_OK)
1997 dsp563xx->hardware_breakpoint[0].used = BPU_NONE;
1998
1999 return err;
2000 }
2001
2002 COMMAND_HANDLER(dsp563xx_add_watchpoint_command)
2003 {
2004 int err = ERROR_OK;
2005 struct target *target = get_current_target(CMD_CTX);
2006
2007 uint32_t mem_type = 0;
2008 switch (CMD_NAME[2]) {
2009 case 'x':
2010 mem_type = MEM_X;
2011 break;
2012 case 'y':
2013 mem_type = MEM_Y;
2014 break;
2015 case 'p':
2016 mem_type = MEM_P;
2017 break;
2018 default:
2019 return ERROR_COMMAND_SYNTAX_ERROR;
2020 }
2021
2022 if (CMD_ARGC < 2)
2023 return ERROR_COMMAND_SYNTAX_ERROR;
2024
2025 uint32_t address = 0;
2026 if (CMD_ARGC > 2)
2027 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
2028
2029 enum watchpoint_condition cond;
2030 switch (CMD_ARGV[0][0]) {
2031 case '>':
2032 cond = GREATER;
2033 break;
2034 case '<':
2035 cond = LESS_THAN;
2036 break;
2037 case '=':
2038 cond = EQUAL;
2039 break;
2040 case '!':
2041 cond = NOT_EQUAL;
2042 break;
2043 default:
2044 return ERROR_COMMAND_SYNTAX_ERROR;
2045 }
2046
2047 enum watchpoint_rw rw;
2048 switch (CMD_ARGV[1][0]) {
2049 case 'r':
2050 rw = WPT_READ;
2051 break;
2052 case 'w':
2053 rw = WPT_WRITE;
2054 break;
2055 case 'a':
2056 rw = WPT_ACCESS;
2057 break;
2058 default:
2059 return ERROR_COMMAND_SYNTAX_ERROR;
2060 }
2061
2062 err = dsp563xx_add_custom_watchpoint(target, address, mem_type, rw, cond);
2063
2064 return err;
2065 }
2066
2067 /* Adding a breakpoint using the once breakpoint logic.
2068 * Note that this mechanism is a true hw breakpoint and is share between the watchpoint logic.
2069 * This means, you can only have one breakpoint/watchpoint at any time.
2070 */
2071 static int dsp563xx_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
2072 {
2073 return dsp563xx_add_custom_watchpoint(target, breakpoint->address, MEM_P, WPT_READ, EQUAL);
2074 }
2075
2076 static int dsp563xx_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2077 {
2078 return dsp563xx_remove_custom_watchpoint(target);
2079 }
2080
2081 COMMAND_HANDLER(dsp563xx_remove_watchpoint_command)
2082 {
2083 struct target *target = get_current_target(CMD_CTX);
2084
2085 return dsp563xx_remove_custom_watchpoint(target);
2086 }
2087
2088 COMMAND_HANDLER(dsp563xx_mem_command)
2089 {
2090 struct target *target = get_current_target(CMD_CTX);
2091 int err = ERROR_OK;
2092 int read_mem;
2093 uint32_t address = 0;
2094 uint32_t count = 1, i;
2095 uint32_t pattern = 0;
2096 uint32_t mem_type;
2097 uint8_t *buffer, *b;
2098
2099 switch (CMD_NAME[1]) {
2100 case 'w':
2101 read_mem = 0;
2102 break;
2103 case 'd':
2104 read_mem = 1;
2105 break;
2106 default:
2107 return ERROR_COMMAND_SYNTAX_ERROR;
2108 }
2109
2110 switch (CMD_NAME[3]) {
2111 case 'x':
2112 mem_type = MEM_X;
2113 break;
2114 case 'y':
2115 mem_type = MEM_Y;
2116 break;
2117 case 'p':
2118 mem_type = MEM_P;
2119 break;
2120 default:
2121 return ERROR_COMMAND_SYNTAX_ERROR;
2122 }
2123
2124 if (CMD_ARGC > 0)
2125 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2126
2127 if (read_mem == 0) {
2128 if (CMD_ARGC < 2)
2129 return ERROR_COMMAND_SYNTAX_ERROR;
2130 if (CMD_ARGC > 1)
2131 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern);
2132 if (CMD_ARGC > 2)
2133 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
2134 }
2135
2136 if (read_mem == 1) {
2137 if (CMD_ARGC < 1)
2138 return ERROR_COMMAND_SYNTAX_ERROR;
2139 if (CMD_ARGC > 1)
2140 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count);
2141 }
2142
2143 buffer = calloc(count, 4);
2144
2145 if (read_mem == 1) {
2146 err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),
2147 count, buffer);
2148 if (err == ERROR_OK)
2149 target_handle_md_output(CMD, target, address, sizeof(uint32_t), count, buffer);
2150
2151 } else {
2152 b = buffer;
2153
2154 for (i = 0; i < count; i++) {
2155 target_buffer_set_u32(target, b, pattern);
2156 b += 4;
2157 }
2158
2159 err = dsp563xx_write_memory(target,
2160 mem_type,
2161 address,
2162 sizeof(uint32_t),
2163 count,
2164 buffer);
2165 }
2166
2167 free(buffer);
2168
2169 return err;
2170 }
2171
2172 static const struct command_registration dsp563xx_command_handlers[] = {
2173 {
2174 .name = "mwwx",
2175 .handler = dsp563xx_mem_command,
2176 .mode = COMMAND_EXEC,
2177 .help = "write x memory words",
2178 .usage = "address value [count]",
2179 },
2180 {
2181 .name = "mwwy",
2182 .handler = dsp563xx_mem_command,
2183 .mode = COMMAND_EXEC,
2184 .help = "write y memory words",
2185 .usage = "address value [count]",
2186 },
2187 {
2188 .name = "mwwp",
2189 .handler = dsp563xx_mem_command,
2190 .mode = COMMAND_EXEC,
2191 .help = "write p memory words",
2192 .usage = "address value [count]",
2193 },
2194 {
2195 .name = "mdwx",
2196 .handler = dsp563xx_mem_command,
2197 .mode = COMMAND_EXEC,
2198 .help = "display x memory words",
2199 .usage = "address [count]",
2200 },
2201 {
2202 .name = "mdwy",
2203 .handler = dsp563xx_mem_command,
2204 .mode = COMMAND_EXEC,
2205 .help = "display y memory words",
2206 .usage = "address [count]",
2207 },
2208 {
2209 .name = "mdwp",
2210 .handler = dsp563xx_mem_command,
2211 .mode = COMMAND_EXEC,
2212 .help = "display p memory words",
2213 .usage = "address [count]",
2214 },
2215 /*
2216 * Watchpoint commands
2217 */
2218 {
2219 .name = "wpp",
2220 .handler = dsp563xx_add_watchpoint_command,
2221 .mode = COMMAND_EXEC,
2222 .help = "Create p memspace watchpoint",
2223 .usage = "(>|<|=|!) (r|w|a) address",
2224 },
2225 {
2226 .name = "wpx",
2227 .handler = dsp563xx_add_watchpoint_command,
2228 .mode = COMMAND_EXEC,
2229 .help = "Create x memspace watchpoint",
2230 .usage = "(>|<|=|!) (r|w|a) address",
2231 },
2232 {
2233 .name = "wpy",
2234 .handler = dsp563xx_add_watchpoint_command,
2235 .mode = COMMAND_EXEC,
2236 .help = "Create y memspace watchpoint",
2237 .usage = "(>|<|=|!) (r|w|a) address",
2238 },
2239 {
2240 .name = "rwpc",
2241 .handler = dsp563xx_remove_watchpoint_command,
2242 .mode = COMMAND_EXEC,
2243 .help = "remove watchpoint custom",
2244 .usage = "",
2245 },
2246 COMMAND_REGISTRATION_DONE
2247 };
2248
2249 /** Holds methods for DSP563XX targets. */
2250 struct target_type dsp563xx_target = {
2251 .name = "dsp563xx",
2252
2253 .poll = dsp563xx_poll,
2254 .arch_state = dsp563xx_arch_state,
2255
2256 .get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
2257
2258 .halt = dsp563xx_halt,
2259 .resume = dsp563xx_resume,
2260 .step = dsp563xx_step,
2261
2262 .assert_reset = dsp563xx_assert_reset,
2263 .deassert_reset = dsp563xx_deassert_reset,
2264
2265 .read_memory = dsp563xx_read_memory_default,
2266 .write_memory = dsp563xx_write_memory_default,
2267
2268 .read_buffer = dsp563xx_read_buffer_default,
2269 .write_buffer = dsp563xx_write_buffer_default,
2270
2271 .run_algorithm = dsp563xx_run_algorithm,
2272
2273 .add_breakpoint = dsp563xx_add_breakpoint,
2274 .remove_breakpoint = dsp563xx_remove_breakpoint,
2275 .add_watchpoint = dsp563xx_add_watchpoint,
2276 .remove_watchpoint = dsp563xx_remove_watchpoint,
2277
2278 .commands = dsp563xx_command_handlers,
2279 .target_create = dsp563xx_target_create,
2280 .init_target = dsp563xx_init_target,
2281 .examine = dsp563xx_examine,
2282 };
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