1 /***************************************************************************
2 * Copyright (C) 2009-2011 by Mathias Kuester *
3 * mkdorg@users.sourceforge.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "target_type.h"
30 #include "dsp563xx_once.h"
32 #define ASM_REG_W_R0 0x60F400
33 #define ASM_REG_W_R1 0x61F400
34 #define ASM_REG_W_R2 0x62F400
35 #define ASM_REG_W_R3 0x63F400
36 #define ASM_REG_W_R4 0x64F400
37 #define ASM_REG_W_R5 0x65F400
38 #define ASM_REG_W_R6 0x66F400
39 #define ASM_REG_W_R7 0x67F400
41 #define ASM_REG_W_N0 0x70F400
42 #define ASM_REG_W_N1 0x71F400
43 #define ASM_REG_W_N2 0x72F400
44 #define ASM_REG_W_N3 0x73F400
45 #define ASM_REG_W_N4 0x74F400
46 #define ASM_REG_W_N5 0x75F400
47 #define ASM_REG_W_N6 0x76F400
48 #define ASM_REG_W_N7 0x77F400
50 #define ASM_REG_W_M0 0x05F420
51 #define ASM_REG_W_M1 0x05F421
52 #define ASM_REG_W_M2 0x05F422
53 #define ASM_REG_W_M3 0x05F423
54 #define ASM_REG_W_M4 0x05F424
55 #define ASM_REG_W_M5 0x05F425
56 #define ASM_REG_W_M6 0x05F426
57 #define ASM_REG_W_M7 0x05F427
59 #define ASM_REG_W_X0 0x44F400
60 #define ASM_REG_W_X1 0x45F400
62 #define ASM_REG_W_Y0 0x46F400
63 #define ASM_REG_W_Y1 0x47F400
65 #define ASM_REG_W_A0 0x50F400
66 #define ASM_REG_W_A1 0x54F400
67 #define ASM_REG_W_A2 0x52F400
69 #define ASM_REG_W_B0 0x51F400
70 #define ASM_REG_W_B1 0x55F400
71 #define ASM_REG_W_B2 0x53F400
73 #define ASM_REG_W_VBA 0x05F430
74 #define ASM_REG_W_OMR 0x05F43A
75 #define ASM_REG_W_EP 0x05F42A
76 #define ASM_REG_W_SC 0x05F431
77 #define ASM_REG_W_SZ 0x05F438
78 #define ASM_REG_W_SR 0x05F439
79 #define ASM_REG_W_SP 0x05F43B
80 #define ASM_REG_W_SSH 0x05F43C
81 #define ASM_REG_W_SSL 0x05F43D
82 #define ASM_REG_W_LA 0x05F43E
83 #define ASM_REG_W_LC 0x05F43F
84 #define ASM_REG_W_PC 0x000000
85 #define ASM_REG_W_IPRC 0xFFFFFF
86 #define ASM_REG_W_IPRP 0xFFFFFE
88 #define ASM_REG_W_BCR 0xFFFFFB
89 #define ASM_REG_W_DCR 0xFFFFFA
90 #define ASM_REG_W_AAR0 0xFFFFF9
91 #define ASM_REG_W_AAR1 0xFFFFF8
92 #define ASM_REG_W_AAR2 0xFFFFF7
93 #define ASM_REG_W_AAR3 0xFFFFF6
95 static struct once_reg once_regs
[] = {
96 {0, 0x00, 24, "OSCR", 0},
97 {1, 0x01, 24, "OMBC", 0},
98 {2, 0x02, 24, "OBCR", 0},
99 {3, 0x05, 24, "OMLR0", 0},
100 {4, 0x06, 24, "OMLR1", 0},
101 {5, 0x09, 24, "OGDBR", 0},
102 {6, 0x0a, 24, "OPDBR", 0},
103 {7, 0x0b, 24, "OPILR", 0},
104 {8, 0x0c, 24, "PDB", 0},
105 {9, 0x0d, 24, "OTC", 0},
106 {10, 0x0f, 24, "OPABFR", 0},
107 {11, 0x10, 24, "OPABDR", 0},
108 {12, 0x11, 24, "OPABEX", 0},
109 {13, 0x12, 25, "OPABF0", 0},
110 {14, 0x12, 25, "OPABF1", 0},
111 {15, 0x12, 25, "OPABF2", 0},
112 {16, 0x12, 25, "OPABF3", 0},
113 {17, 0x12, 25, "OPABF4", 0},
114 {18, 0x12, 25, "OPABF5", 0},
115 {19, 0x12, 25, "OPABF6", 0},
116 {20, 0x12, 25, "OPABF7", 0},
117 {21, 0x12, 25, "OPABF8", 0},
118 {22, 0x12, 25, "OPABF9", 0},
119 {23, 0x12, 25, "OPABF10", 0},
120 {24, 0x12, 25, "OPABF11", 0},
121 // {25,0x1f,24,"NRSEL",0},
129 /* effective addressing mode encoding */
135 /* address registers */
136 { 0, "r0", 24, 0x10, ASM_REG_W_R0
},
137 { 1, "r1", 24, 0x11, ASM_REG_W_R1
},
138 { 2, "r2", 24, 0x12, ASM_REG_W_R2
},
139 { 3, "r3", 24, 0x13, ASM_REG_W_R3
},
140 { 4, "r4", 24, 0x14, ASM_REG_W_R4
},
141 { 5, "r5", 24, 0x15, ASM_REG_W_R5
},
142 { 6, "r6", 24, 0x16, ASM_REG_W_R6
},
143 { 7, "r7", 24, 0x17, ASM_REG_W_R7
},
144 /* offset registers */
145 { 8, "n0", 24, 0x18, ASM_REG_W_N0
},
146 { 9, "n1", 24, 0x19, ASM_REG_W_N1
},
147 {10, "n2", 24, 0x1a, ASM_REG_W_N2
},
148 {11, "n3", 24, 0x1b, ASM_REG_W_N3
},
149 {12, "n4", 24, 0x1c, ASM_REG_W_N4
},
150 {13, "n5", 24, 0x1d, ASM_REG_W_N5
},
151 {14, "n6", 24, 0x1e, ASM_REG_W_N6
},
152 {15, "n7", 24, 0x1f, ASM_REG_W_N7
},
153 /* modifier registers */
154 {16, "m0", 24, 0x20, ASM_REG_W_M0
},
155 {17, "m1", 24, 0x21, ASM_REG_W_M1
},
156 {18, "m2", 24, 0x22, ASM_REG_W_M2
},
157 {19, "m3", 24, 0x23, ASM_REG_W_M3
},
158 {20, "m4", 24, 0x24, ASM_REG_W_M4
},
159 {21, "m5", 24, 0x25, ASM_REG_W_M5
},
160 {22, "m6", 24, 0x26, ASM_REG_W_M6
},
161 {23, "m7", 24, 0x27, ASM_REG_W_M7
},
162 /* data alu input register */
163 {24, "x0", 24, 0x04, ASM_REG_W_X0
},
164 {25, "x1", 24, 0x05, ASM_REG_W_X1
},
165 {26, "y0", 24, 0x06, ASM_REG_W_Y0
},
166 {27, "y1", 24, 0x07, ASM_REG_W_Y1
},
167 /* data alu accumulator register */
168 {28, "a0", 24, 0x08, ASM_REG_W_A0
},
169 {29, "a1", 24, 0x0c, ASM_REG_W_A1
},
170 {30, "a2", 8, 0x0a, ASM_REG_W_A2
},
171 {31, "b0", 24, 0x09, ASM_REG_W_B0
},
172 {32, "b1", 24, 0x0d, ASM_REG_W_B1
},
173 {33, "b2", 8, 0x0b, ASM_REG_W_B2
},
175 {34, "ssh",24, 0x3c, ASM_REG_W_SSH
},
176 {35, "ssl",24, 0x3d, ASM_REG_W_SSL
},
177 {36, "sp", 24, 0x3b, ASM_REG_W_SP
},
178 {37, "ep", 24, 0x2a, ASM_REG_W_EP
},
179 {38, "sz", 24, 0x38, ASM_REG_W_SZ
},
180 {39, "sc", 24, 0x31, ASM_REG_W_SC
},
182 {40, "pc", 24, 0x00, ASM_REG_W_PC
},
183 {41, "sr", 24, 0x39, ASM_REG_W_SR
},
184 {42, "omr",24, 0x3a, ASM_REG_W_OMR
},
185 {43, "la", 24, 0x3e, ASM_REG_W_LA
},
186 {44, "lc", 24, 0x3f, ASM_REG_W_LC
},
188 {45, "vba", 24, 0x30, ASM_REG_W_VBA
},
189 {46, "iprc",24, 0x00, ASM_REG_W_IPRC
},
190 {47, "iprp",24, 0x00, ASM_REG_W_IPRP
},
192 {48, "bcr", 24, 0x00, ASM_REG_W_BCR
},
193 {49, "dcr", 24, 0x00, ASM_REG_W_DCR
},
194 {50, "aar0",24, 0x00, ASM_REG_W_AAR0
},
195 {51, "aar1",24, 0x00, ASM_REG_W_AAR1
},
196 {52, "aar2",24, 0x00, ASM_REG_W_AAR2
},
197 {53, "aar3",24, 0x00, ASM_REG_W_AAR3
},
205 #define REG_NUM_M0 16
206 #define REG_NUM_M1 17
207 #define REG_NUM_SSH 34
208 #define REG_NUM_SSL 35
209 #define REG_NUM_SP 36
210 #define REG_NUM_EP 37
211 #define REG_NUM_SC 39
212 #define REG_NUM_PC 40
213 #define REG_NUM_SR 41
214 #define REG_NUM_IPRC 46
215 #define REG_NUM_IPRP 47
216 #define REG_NUM_BCR 48
217 #define REG_NUM_DCR 49
218 #define REG_NUM_AAR0 50
219 #define REG_NUM_AAR1 51
220 #define REG_NUM_AAR2 52
221 #define REG_NUM_AAR3 53
230 #define INSTR_JUMP 0x0AF080
231 /* Effective Addressing Mode Encoding */
233 /* instrcution encoder */
235 * s - peripheral space X/Y (X=0,Y=1)
237 * d - source/destination register
238 * p - IO short address
240 #define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f))
242 static int dsp563xx_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
245 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
247 if (target
->state
!= TARGET_HALTED
)
249 return ERROR_TARGET_NOT_HALTED
;
252 *reg_list_size
= DSP563XX_NUMCOREREGS
;
253 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
256 return ERROR_INVALID_ARGUMENTS
;
258 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
260 (*reg_list
)[i
] = &dsp563xx
->core_cache
->reg_list
[i
];
267 static int dsp563xx_read_core_reg(struct target
*target
, int num
)
270 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
271 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
273 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
274 return ERROR_INVALID_ARGUMENTS
;
276 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
277 reg_value
= dsp563xx
->core_regs
[num
];
278 buf_set_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
279 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
280 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
285 static int dsp563xx_write_core_reg(struct target
*target
, int num
)
288 struct dsp563xx_core_reg
*dsp563xx_core_reg
;
289 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
291 if ((num
< 0) || (num
>= DSP563XX_NUMCOREREGS
))
292 return ERROR_INVALID_ARGUMENTS
;
294 reg_value
= buf_get_u32(dsp563xx
->core_cache
->reg_list
[num
].value
, 0, 32);
295 dsp563xx_core_reg
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
296 dsp563xx
->core_regs
[num
] = reg_value
;
297 dsp563xx
->core_cache
->reg_list
[num
].valid
= 1;
298 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 0;
303 static int dsp563xx_target_create(struct target
*target
, Jim_Interp
* interp
)
305 struct dsp563xx_common
*dsp563xx
= calloc(1, sizeof(struct dsp563xx_common
));
308 return ERROR_INVALID_ARGUMENTS
;
310 dsp563xx
->jtag_info
.tap
= target
->tap
;
311 target
->arch_info
= dsp563xx
;
312 dsp563xx
->read_core_reg
= dsp563xx_read_core_reg
;
313 dsp563xx
->write_core_reg
= dsp563xx_write_core_reg
;
318 static int dsp563xx_get_core_reg(struct reg
*reg
)
320 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
321 struct target
*target
= dsp563xx_reg
->target
;
322 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
324 LOG_DEBUG("%s", __FUNCTION__
);
326 if (target
->state
!= TARGET_HALTED
)
328 return ERROR_TARGET_NOT_HALTED
;
331 return dsp563xx
->read_core_reg(target
, dsp563xx_reg
->num
);
334 static int dsp563xx_set_core_reg(struct reg
*reg
, uint8_t * buf
)
336 LOG_DEBUG("%s", __FUNCTION__
);
338 struct dsp563xx_core_reg
*dsp563xx_reg
= reg
->arch_info
;
339 struct target
*target
= dsp563xx_reg
->target
;
340 uint32_t value
= buf_get_u32(buf
, 0, 32);
342 if (target
->state
!= TARGET_HALTED
)
344 return ERROR_TARGET_NOT_HALTED
;
347 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
354 static int dsp563xx_read_register(struct target
*target
, int num
, int force
);
355 static int dsp563xx_write_register(struct target
*target
, int num
, int force
);
357 static int dsp563xx_reg_read_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t * data
)
361 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
363 /* we use r0 to store temporary data */
364 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
365 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
367 /* move source memory to r0 */
368 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 0, EAME_R0
, instr_mask
);
369 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, instr
)) != ERROR_OK
)
371 /* move r0 to debug register */
372 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, 0xfffffc);
373 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, instr
)) != ERROR_OK
)
375 /* read debug register */
376 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, data
)) != ERROR_OK
)
378 /* r0 is no longer valid on target */
379 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
384 static int dsp563xx_reg_write_high_io(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
388 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
390 /* we use r0 to store temporary data */
391 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
392 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
394 /* move data to r0 */
395 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x60F400, data
)) != ERROR_OK
)
397 /* move r0 to destination memory */
398 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, EAME_R0
, instr_mask
);
399 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, instr
)) != ERROR_OK
)
402 /* r0 is no longer valid on target */
403 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
408 static int dsp563xx_reg_read(struct target
*target
, uint32_t eame
, uint32_t * data
)
413 instr
= INSTR_MOVEP_REG_HIO(MEM_X
, 1, eame
, 0xfffffc);
414 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, instr
)) != ERROR_OK
)
417 if ((err
= dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000)) != ERROR_OK
)
419 /* read debug register */
420 return dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OGDBR
, data
);
423 static int dsp563xx_reg_write(struct target
*target
, uint32_t instr_mask
, uint32_t data
)
427 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, instr_mask
, data
)) != ERROR_OK
)
430 return dsp563xx_once_execute_sw_ir(target
->tap
, 0x000000);
433 static int dsp563xx_reg_pc_read(struct target
*target
)
436 uint32_t opabdr
, opabex
;
437 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
439 /* pc was changed, nothing todo */
440 if (dsp563xx
->core_cache
->reg_list
[REG_NUM_PC
].dirty
)
443 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABDR
, &opabdr
)) != ERROR_OK
)
445 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
, &opabex
)) != ERROR_OK
)
448 /* conditional branch check */
449 if (opabdr
== opabex
)
451 /* TODO: check the trace buffer and if a
452 * conditional branch is detected then decode
453 * the branch command and add the relative
454 * address to the current pc
456 LOG_DEBUG("%s conditional branch not supported yet", __FUNCTION__
);
460 dsp563xx
->core_regs
[REG_NUM_PC
] = opabex
;
461 dsp563xx
->read_core_reg(target
, REG_NUM_PC
);
467 static int dsp563xx_reg_ssh_read(struct target
*target
)
471 struct dsp563xx_core_reg
*arch_info
;
472 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
474 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
476 /* get a valid stack pointer */
477 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
479 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
480 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
483 /* get a valid stack count */
484 if ((err
= dsp563xx_read_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
486 sc
= dsp563xx
->core_regs
[REG_NUM_SC
];
487 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 0)) != ERROR_OK
)
490 /* get a valid extended pointer */
491 if ((err
= dsp563xx_read_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
493 ep
= dsp563xx
->core_regs
[REG_NUM_EP
];
494 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 0)) != ERROR_OK
)
503 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
506 if ((err
= dsp563xx_write_register(target
, REG_NUM_SC
, 1)) != ERROR_OK
)
508 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
510 if ((err
= dsp563xx_write_register(target
, REG_NUM_EP
, 1)) != ERROR_OK
)
514 dsp563xx
->core_regs
[REG_NUM_SSH
] = sp
;
515 dsp563xx
->read_core_reg(target
, REG_NUM_SSH
);
520 static int dsp563xx_reg_ssh_write(struct target
*target
)
524 struct dsp563xx_core_reg
*arch_info
;
525 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
527 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].arch_info
;
529 /* get a valid stack pointer */
530 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
532 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
537 /* write new stackpointer */
538 dsp563xx
->core_regs
[REG_NUM_SP
] = sp
;
539 if ((err
= dsp563xx
->read_core_reg(target
, REG_NUM_SP
)) != ERROR_OK
)
541 if ((err
= dsp563xx_write_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
544 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[REG_NUM_SSH
])) != ERROR_OK
)
547 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 1)) != ERROR_OK
)
549 if ((err
= dsp563xx_read_register(target
, REG_NUM_SSH
, 1)) != ERROR_OK
)
556 static int dsp563xx_reg_ssl_read(struct target
*target
)
560 struct dsp563xx_core_reg
*arch_info
;
561 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
563 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].arch_info
;
565 /* get a valid stack pointer */
566 if ((err
= dsp563xx_read_register(target
, REG_NUM_SP
, 0)) != ERROR_OK
)
568 sp
= dsp563xx
->core_regs
[REG_NUM_SP
];
576 if ((err
= dsp563xx_reg_read(target
, arch_info
->eame
, &sp
)) != ERROR_OK
)
580 dsp563xx
->core_regs
[REG_NUM_SSL
] = sp
;
581 dsp563xx
->read_core_reg(target
, REG_NUM_SSL
);
586 static int dsp563xx_read_register(struct target
*target
, int num
, int force
)
590 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
591 struct dsp563xx_core_reg
*arch_info
;
594 dsp563xx
->core_cache
->reg_list
[num
].valid
= 0;
596 if (!dsp563xx
->core_cache
->reg_list
[num
].valid
)
598 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
600 switch (arch_info
->num
)
603 err
= dsp563xx_reg_ssh_read(target
);
606 err
= dsp563xx_reg_ssl_read(target
);
609 err
= dsp563xx_reg_pc_read(target
);
619 err
= dsp563xx_reg_read_high_io(target
, arch_info
->instr_mask
, &data
);
622 dsp563xx
->core_regs
[num
] = data
;
623 dsp563xx
->read_core_reg(target
, num
);
627 err
= dsp563xx_reg_read(target
, arch_info
->eame
, &data
);
630 dsp563xx
->core_regs
[num
] = data
;
631 dsp563xx
->read_core_reg(target
, num
);
641 static int dsp563xx_write_register(struct target
*target
, int num
, int force
)
644 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
645 struct dsp563xx_core_reg
*arch_info
;
648 dsp563xx
->core_cache
->reg_list
[num
].dirty
= 1;
650 if (dsp563xx
->core_cache
->reg_list
[num
].dirty
)
652 arch_info
= dsp563xx
->core_cache
->reg_list
[num
].arch_info
;
654 dsp563xx
->write_core_reg(target
, num
);
656 switch (arch_info
->num
)
659 err
= dsp563xx_reg_ssh_write(target
);
662 /* pc is updated on resume, no need to write it here */
672 err
= dsp563xx_reg_write_high_io(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
675 err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, dsp563xx
->core_regs
[num
]);
677 if ((err
== ERROR_OK
) && (arch_info
->num
== REG_NUM_SP
))
679 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSH
].valid
= 0;
680 dsp563xx
->core_cache
->reg_list
[REG_NUM_SSL
].valid
= 0;
690 static int dsp563xx_save_context(struct target
*target
)
692 int i
, err
= ERROR_OK
;
694 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
696 if ((err
= dsp563xx_read_register(target
, i
, 0)) != ERROR_OK
)
703 static int dsp563xx_restore_context(struct target
*target
)
705 int i
, err
= ERROR_OK
;
707 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
709 if ((err
= dsp563xx_write_register(target
, i
, 0)) != ERROR_OK
)
716 static const struct reg_arch_type dsp563xx_reg_type
= {
717 .get
= dsp563xx_get_core_reg
,
718 .set
= dsp563xx_set_core_reg
,
721 static int dsp563xx_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
723 /* get pointers to arch-specific information */
724 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
726 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
727 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
728 struct reg
*reg_list
= malloc(sizeof(struct reg
) * DSP563XX_NUMCOREREGS
);
729 struct dsp563xx_core_reg
*arch_info
= malloc(sizeof(struct dsp563xx_core_reg
) * DSP563XX_NUMCOREREGS
);
732 LOG_DEBUG("%s", __FUNCTION__
);
734 /* Build the process context cache */
735 cache
->name
= "dsp563xx registers";
737 cache
->reg_list
= reg_list
;
738 cache
->num_regs
= DSP563XX_NUMCOREREGS
;
740 dsp563xx
->core_cache
= cache
;
742 for (i
= 0; i
< DSP563XX_NUMCOREREGS
; i
++)
744 arch_info
[i
].num
= dsp563xx_regs
[i
].id
;
745 arch_info
[i
].name
= dsp563xx_regs
[i
].name
;
746 arch_info
[i
].size
= dsp563xx_regs
[i
].bits
;
747 arch_info
[i
].eame
= dsp563xx_regs
[i
].eame
;
748 arch_info
[i
].instr_mask
= dsp563xx_regs
[i
].instr_mask
;
749 arch_info
[i
].target
= target
;
750 arch_info
[i
].dsp563xx_common
= dsp563xx
;
751 reg_list
[i
].name
= dsp563xx_regs
[i
].name
;
752 reg_list
[i
].size
= dsp563xx_regs
[i
].bits
;
753 reg_list
[i
].value
= calloc(1, 4);
754 reg_list
[i
].dirty
= 0;
755 reg_list
[i
].valid
= 0;
756 reg_list
[i
].type
= &dsp563xx_reg_type
;
757 reg_list
[i
].arch_info
= &arch_info
[i
];
763 static int dsp563xx_arch_state(struct target
*target
)
765 LOG_DEBUG("%s", __FUNCTION__
);
769 #define DSP563XX_SR_SA (1<<17)
770 #define DSP563XX_SR_SC (1<<13)
772 static int dsp563xx_debug_once_init(struct target
*target
)
774 return dsp563xx_once_read_register(target
->tap
, once_regs
, DSP563XX_NUMONCEREGS
);
777 static int dsp563xx_debug_init(struct target
*target
)
781 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
782 struct dsp563xx_core_reg
*arch_info
;
784 if ((err
= dsp563xx_debug_once_init(target
)) != ERROR_OK
)
787 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].arch_info
;
789 /* check 24bit mode */
790 if ((err
= dsp563xx_read_register(target
, REG_NUM_SR
, 0)) != ERROR_OK
)
793 sr
= dsp563xx
->core_regs
[REG_NUM_SR
];
795 if (sr
& (DSP563XX_SR_SA
| DSP563XX_SR_SC
))
797 sr
&= ~(DSP563XX_SR_SA
| DSP563XX_SR_SC
);
799 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, arch_info
->instr_mask
, sr
)) != ERROR_OK
)
801 dsp563xx
->core_cache
->reg_list
[REG_NUM_SR
].dirty
= 1;
804 if ((err
= dsp563xx_read_register(target
, REG_NUM_N0
, 0)) != ERROR_OK
)
806 if ((err
= dsp563xx_read_register(target
, REG_NUM_N1
, 0)) != ERROR_OK
)
808 if ((err
= dsp563xx_read_register(target
, REG_NUM_M0
, 0)) != ERROR_OK
)
810 if ((err
= dsp563xx_read_register(target
, REG_NUM_M1
, 0)) != ERROR_OK
)
813 if (dsp563xx
->core_regs
[REG_NUM_N0
] != 0x000000)
815 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].arch_info
;
816 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
819 dsp563xx
->core_cache
->reg_list
[REG_NUM_N0
].dirty
= 1;
821 if (dsp563xx
->core_regs
[REG_NUM_N1
] != 0x000000)
823 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].arch_info
;
824 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0x000000)) != ERROR_OK
)
827 dsp563xx
->core_cache
->reg_list
[REG_NUM_N1
].dirty
= 1;
829 if (dsp563xx
->core_regs
[REG_NUM_M0
] != 0xffffff)
831 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].arch_info
;
832 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
835 dsp563xx
->core_cache
->reg_list
[REG_NUM_M0
].dirty
= 1;
837 if (dsp563xx
->core_regs
[REG_NUM_M1
] != 0xffffff)
839 arch_info
= dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].arch_info
;
840 if ((err
= dsp563xx_reg_write(target
, arch_info
->instr_mask
, 0xffffff)) != ERROR_OK
)
843 dsp563xx
->core_cache
->reg_list
[REG_NUM_M1
].dirty
= 1;
845 if ((err
= dsp563xx_save_context(target
)) != ERROR_OK
)
851 static int dsp563xx_jtag_debug_request(struct target
*target
)
853 return dsp563xx_once_request_debug(target
->tap
, target
->state
== TARGET_RESET
);
856 static int dsp563xx_poll(struct target
*target
)
859 uint32_t once_status
;
862 state
= dsp563xx_once_target_status(target
->tap
);
864 if (state
== TARGET_UNKNOWN
)
866 target
->state
= state
;
867 LOG_ERROR("jtag status contains invalid mode value - communication failure");
868 return ERROR_TARGET_FAILURE
;
871 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
874 if ((once_status
& DSP563XX_ONCE_OSCR_DEBUG_M
) == DSP563XX_ONCE_OSCR_DEBUG_M
)
876 if (target
->state
!= TARGET_HALTED
)
878 target
->state
= TARGET_HALTED
;
879 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
882 LOG_DEBUG("target->state: %s", target_state_name(target
));
889 static int dsp563xx_halt(struct target
*target
)
892 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
894 if (target
->state
== TARGET_HALTED
)
896 LOG_DEBUG("target was already halted");
900 if (target
->state
== TARGET_UNKNOWN
)
902 LOG_WARNING("target was in unknown state when halt was requested");
905 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
908 /* store pipeline register */
909 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
, &dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
911 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
, &dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
914 LOG_DEBUG("%s", __FUNCTION__
);
919 static int dsp563xx_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
922 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
924 LOG_DEBUG("%s", __FUNCTION__
);
926 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
928 register_cache_invalidate(dsp563xx
->core_cache
);
932 /* restore pipeline registers and go */
933 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
, dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
936 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
937 dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
942 /* set to go register and jump */
943 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
945 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
949 target
->state
= TARGET_RUNNING
;
954 static int dsp563xx_step_ex(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int steps
)
957 uint32_t once_status
;
959 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
961 if (target
->state
!= TARGET_HALTED
)
963 LOG_DEBUG("target was not halted");
967 LOG_DEBUG("%s %08X %08X", __FUNCTION__
, current
, (unsigned) address
);
969 if ((err
= dsp563xx_jtag_debug_request(target
)) != ERROR_OK
)
971 if ((err
= dsp563xx_restore_context(target
)) != ERROR_OK
)
974 /* reset trace mode */
975 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
977 /* enable trace mode */
978 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, DSP563XX_ONCE_OSCR_TME
)) != ERROR_OK
)
983 /* on JUMP we need one extra cycle */
987 /* load step counter with N-1 */
988 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OTC
, cnt
)) != ERROR_OK
)
993 /* restore pipeline registers and go */
994 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPILR
, dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
997 dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
,
998 dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
1003 /* set to go register and jump */
1004 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OPDBR
, INSTR_JUMP
)) != ERROR_OK
)
1006 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_PDBGOTO
| DSP563XX_ONCE_OCR_EX
| DSP563XX_ONCE_OCR_GO
, address
)) != ERROR_OK
)
1012 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OSCR
, &once_status
)) != ERROR_OK
)
1015 if (once_status
& DSP563XX_ONCE_OSCR_TO
)
1017 /* store pipeline register */
1018 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPILR
, &dsp563xx
->pipeline_context
.once_opilr
)) != ERROR_OK
)
1020 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPDBR
, &dsp563xx
->pipeline_context
.once_opdbr
)) != ERROR_OK
)
1023 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABFR
, &dr_in
)) != ERROR_OK
)
1025 LOG_DEBUG("fetch: %08X", (unsigned) dr_in
);
1026 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABDR
, &dr_in
)) != ERROR_OK
)
1028 LOG_DEBUG("decode: %08X", (unsigned) dr_in
);
1029 if ((err
= dsp563xx_once_reg_read(target
->tap
, DSP563XX_ONCE_OPABEX
, &dr_in
)) != ERROR_OK
)
1031 LOG_DEBUG("execute: %08X", (unsigned) dr_in
);
1033 /* reset trace mode */
1034 if ((err
= dsp563xx_once_reg_write(target
->tap
, DSP563XX_ONCE_OSCR
, 0x000000)) != ERROR_OK
)
1037 register_cache_invalidate(dsp563xx
->core_cache
);
1038 if ((err
= dsp563xx_debug_init(target
)) != ERROR_OK
)
1048 static int dsp563xx_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
1050 return dsp563xx_step_ex(target
, current
, address
, handle_breakpoints
, 0);
1053 static int dsp563xx_assert_reset(struct target
*target
)
1056 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1057 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1059 if (jtag_reset_config
& RESET_HAS_SRST
)
1061 /* default to asserting srst */
1062 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1064 jtag_add_reset(1, 1);
1068 jtag_add_reset(0, 1);
1072 target
->state
= TARGET_RESET
;
1073 jtag_add_sleep(5000);
1075 /* registers are now invalid */
1076 register_cache_invalidate(dsp563xx
->core_cache
);
1078 if (target
->reset_halt
)
1080 if ((retval
= target_halt(target
)) != ERROR_OK
)
1084 LOG_DEBUG("%s", __FUNCTION__
);
1088 static int dsp563xx_deassert_reset(struct target
*target
)
1092 /* deassert reset lines */
1093 jtag_add_reset(0, 0);
1095 if ((err
= dsp563xx_poll(target
)) != ERROR_OK
)
1098 if (target
->reset_halt
)
1100 if (target
->state
== TARGET_HALTED
)
1102 /* after a reset the cpu jmp to the
1103 * reset vector and need 2 cycles to fill
1104 * the cache (fetch,decode,excecute)
1106 if ((err
= dsp563xx_step_ex(target
, 1, 0, 1, 1)) != ERROR_OK
)
1111 // target->state = TARGET_RUNNING;
1113 LOG_DEBUG("%s", __FUNCTION__
);
1117 static int dsp563xx_soft_reset_halt(struct target
*target
)
1119 LOG_DEBUG("%s", __FUNCTION__
);
1123 static int dsp563xx_read_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1126 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1128 uint32_t data
, move_cmd
;
1131 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
, address
, size
, count
);
1133 if (target
->state
!= TARGET_HALTED
)
1135 LOG_WARNING("target not halted");
1136 return ERROR_TARGET_NOT_HALTED
;
1139 /* we only support 4 byte aligned data */
1142 return ERROR_INVALID_ARGUMENTS
;
1148 /* TODO: mark effected queued registers */
1149 move_cmd
= 0x61d800;
1152 move_cmd
= 0x69d800;
1155 move_cmd
= 0x07d891;
1158 return ERROR_INVALID_ARGUMENTS
;
1161 /* we use r0 to store temporary data */
1162 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1163 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1164 /* we use r1 to store temporary data */
1165 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1166 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1168 /* r0 is no longer valid on target */
1169 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1170 /* r1 is no longer valid on target */
1171 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1176 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0x60F400, address
)) != ERROR_OK
)
1179 for (i
= 0; i
< x
; i
++)
1181 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, move_cmd
)) != ERROR_OK
)
1183 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, 0x08D13C)) != ERROR_OK
)
1185 if ((err
= dsp563xx_once_reg_read_nq(target
->tap
, DSP563XX_ONCE_OGDBR
, (uint32_t*)b
)) != ERROR_OK
)
1190 /* flush the jtag queue */
1191 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1196 /* walk over the buffer and fix target endianness */
1199 for (i
= 0; i
< x
; i
++)
1201 data
= *((uint32_t*)b
) & 0x00FFFFFF;
1202 // LOG_DEBUG("R: %08X", *((uint32_t*)b));
1203 target_buffer_set_u32(target
, b
, data
);
1210 static int dsp563xx_read_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1212 return dsp563xx_read_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1215 static int dsp563xx_write_memory(struct target
*target
, int mem_type
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1218 struct dsp563xx_common
*dsp563xx
= target_to_dsp563xx(target
);
1220 uint32_t data
, move_cmd
;
1223 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
1225 if (target
->state
!= TARGET_HALTED
)
1227 LOG_WARNING("target not halted");
1228 return ERROR_TARGET_NOT_HALTED
;
1231 /* we only support 4 byte aligned data */
1234 return ERROR_INVALID_ARGUMENTS
;
1240 move_cmd
= 0x615800;
1243 move_cmd
= 0x695800;
1246 move_cmd
= 0x075891;
1249 return ERROR_INVALID_ARGUMENTS
;
1252 /* we use r0 to store temporary data */
1253 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].valid
)
1254 dsp563xx
->read_core_reg(target
, REG_NUM_R0
);
1255 /* we use r1 to store temporary data */
1256 if (!dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].valid
)
1257 dsp563xx
->read_core_reg(target
, REG_NUM_R1
);
1259 /* r0 is no longer valid on target */
1260 dsp563xx
->core_cache
->reg_list
[REG_NUM_R0
].dirty
= 1;
1261 /* r1 is no longer valid on target */
1262 dsp563xx
->core_cache
->reg_list
[REG_NUM_R1
].dirty
= 1;
1267 if ((err
= dsp563xx_once_execute_dw_ir(target
->tap
, 0x60F400, address
)) != ERROR_OK
)
1270 for (i
= 0; i
< x
; i
++)
1272 data
= target_buffer_get_u32(target
, b
);
1274 // LOG_DEBUG("W: %08X", data);
1278 if ((err
= dsp563xx_once_execute_dw_ir_nq(target
->tap
, 0x61F400, data
)) != ERROR_OK
)
1280 if ((err
= dsp563xx_once_execute_sw_ir_nq(target
->tap
, move_cmd
)) != ERROR_OK
)
1285 /* flush the jtag queue */
1286 if ((err
= jtag_execute_queue()) != ERROR_OK
)
1294 static int dsp563xx_write_memory_p(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t * buffer
)
1296 return dsp563xx_write_memory(target
, MEM_P
, address
, size
, count
, buffer
);
1299 static int dsp563xx_bulk_write_memory_p(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
1301 return dsp563xx_write_memory(target
, MEM_P
, address
, 4, count
, buffer
);
1304 static void handle_md_output(struct command_context
*cmd_ctx
, struct target
*target
, uint32_t address
, unsigned size
, unsigned count
, const uint8_t * buffer
)
1306 const unsigned line_bytecnt
= 32;
1307 unsigned line_modulo
= line_bytecnt
/ size
;
1309 char output
[line_bytecnt
* 4 + 1];
1310 unsigned output_len
= 0;
1312 const char *value_fmt
;
1316 value_fmt
= "%8.8x ";
1319 value_fmt
= "%4.4x ";
1322 value_fmt
= "%2.2x ";
1325 /* "can't happen", caller checked */
1326 LOG_ERROR("invalid memory read size: %u", size
);
1330 for (unsigned i
= 0; i
< count
; i
++)
1332 if (i
% line_modulo
== 0)
1334 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, "0x%8.8x: ", (unsigned) (address
+ (i
* size
)));
1338 const uint8_t *value_ptr
= buffer
+ i
* size
;
1342 value
= target_buffer_get_u32(target
, value_ptr
);
1345 value
= target_buffer_get_u16(target
, value_ptr
);
1350 output_len
+= snprintf(output
+ output_len
, sizeof(output
) - output_len
, value_fmt
, value
);
1352 if ((i
% line_modulo
== line_modulo
- 1) || (i
== count
- 1))
1354 command_print(cmd_ctx
, "%s", output
);
1360 COMMAND_HANDLER(dsp563xx_mem_command
)
1362 struct target
*target
= get_current_target(CMD_CTX
);
1365 uint32_t address
= 0;
1366 uint32_t count
= 1, i
;
1367 uint32_t pattern
= 0;
1369 uint8_t *buffer
, *b
;
1371 switch (CMD_NAME
[1])
1380 return ERROR_COMMAND_SYNTAX_ERROR
;
1383 switch (CMD_NAME
[3])
1395 return ERROR_COMMAND_SYNTAX_ERROR
;
1400 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1407 return ERROR_COMMAND_SYNTAX_ERROR
;
1411 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], pattern
);
1415 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], count
);
1423 return ERROR_COMMAND_SYNTAX_ERROR
;
1427 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], count
);
1431 buffer
= calloc(count
, sizeof(uint32_t));
1435 if ((err
= dsp563xx_read_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
)) == ERROR_OK
)
1436 handle_md_output(CMD_CTX
, target
, address
, sizeof(uint32_t), count
, buffer
);
1442 for (i
= 0; i
< count
; i
++)
1444 target_buffer_set_u32(target
, b
, pattern
);
1448 err
= dsp563xx_write_memory(target
, mem_type
, address
, sizeof(uint32_t), count
, buffer
);
1456 static const struct command_registration dsp563xx_command_handlers
[] = {
1459 .handler
= dsp563xx_mem_command
,
1460 .mode
= COMMAND_EXEC
,
1461 .help
= "write x memory words",
1462 .usage
= "mwwx address value [count]",
1466 .handler
= dsp563xx_mem_command
,
1467 .mode
= COMMAND_EXEC
,
1468 .help
= "write y memory words",
1469 .usage
= "mwwy address value [count]",
1473 .handler
= dsp563xx_mem_command
,
1474 .mode
= COMMAND_EXEC
,
1475 .help
= "write p memory words",
1476 .usage
= "mwwp address value [count]",
1480 .handler
= dsp563xx_mem_command
,
1481 .mode
= COMMAND_EXEC
,
1482 .help
= "display x memory words",
1483 .usage
= "mdwx address [count]",
1487 .handler
= dsp563xx_mem_command
,
1488 .mode
= COMMAND_EXEC
,
1489 .help
= "display y memory words",
1490 .usage
= "mdwy address [count]",
1494 .handler
= dsp563xx_mem_command
,
1495 .mode
= COMMAND_EXEC
,
1496 .help
= "display p memory words",
1497 .usage
= "mdwp address [count]",
1499 COMMAND_REGISTRATION_DONE
1502 /** Holds methods for DSP563XX targets. */
1503 struct target_type dsp563xx_target
= {
1506 .poll
= dsp563xx_poll
,
1507 .arch_state
= dsp563xx_arch_state
,
1509 .target_request_data
= NULL
,
1511 .get_gdb_reg_list
= dsp563xx_get_gdb_reg_list
,
1513 .halt
= dsp563xx_halt
,
1514 .resume
= dsp563xx_resume
,
1515 .step
= dsp563xx_step
,
1517 .assert_reset
= dsp563xx_assert_reset
,
1518 .deassert_reset
= dsp563xx_deassert_reset
,
1519 .soft_reset_halt
= dsp563xx_soft_reset_halt
,
1521 .read_memory
= dsp563xx_read_memory_p
,
1522 .write_memory
= dsp563xx_write_memory_p
,
1523 .bulk_write_memory
= dsp563xx_bulk_write_memory_p
,
1525 .commands
= dsp563xx_command_handlers
,
1526 .target_create
= dsp563xx_target_create
,
1527 .init_target
= dsp563xx_init_target
,
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