src/target/espressif/esp_xtensa_smp.h

   1 /***************************************************************************
   2  *   ESP Xtensa SMP target for OpenOCD                                     *
   3  *   Copyright (C) 2020 Espressif Systems Ltd. Co                          *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_XTENSA_ESP_SMP_H
  20 #define OPENOCD_TARGET_XTENSA_ESP_SMP_H
  21
  22 #include "esp_xtensa.h"
  23
  24 struct esp_xtensa_smp_chip_ops {
  25         int (*poll)(struct target *target);
  26         int (*reset)(struct target *target);
  27         int (*on_halt)(struct target *target);
  28 };
  29
  30 struct esp_xtensa_smp_common {
  31         struct esp_xtensa_common esp_xtensa;
  32         const struct esp_xtensa_smp_chip_ops *chip_ops;
  33         bool other_core_does_resume;
  34         /* number of attempts to examine other SMP cores, attempts are made after reset on target poll */
  35         int examine_other_cores;
  36 };
  37
  38 int esp_xtensa_smp_poll(struct target *target);
  39 int esp_xtensa_smp_resume(struct target *target,
  40         int current,
  41         target_addr_t address,
  42         int handle_breakpoints,
  43         int debug_execution);
  44 int esp_xtensa_smp_step(struct target *target,
  45         int current,
  46         target_addr_t address,
  47         int handle_breakpoints);
  48 int esp_xtensa_smp_assert_reset(struct target *target);
  49 int esp_xtensa_smp_deassert_reset(struct target *target);
  50 int esp_xtensa_smp_soft_reset_halt(struct target *target);
  51 int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
  52 int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
  53 int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event event, void *priv);
  54 int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
  55 int esp_xtensa_smp_init_arch_info(struct target *target,
  56         struct esp_xtensa_smp_common *esp_xtensa_smp,
  57         const struct xtensa_config *xtensa_cfg,
  58         struct xtensa_debug_module_config *dm_cfg,
  59         const struct esp_xtensa_smp_chip_ops *chip_ops);
  60
  61 extern const struct command_registration esp_xtensa_smp_command_handlers[];
  62 extern const struct command_registration esp_xtensa_smp_xtensa_command_handlers[];
  63 extern const struct command_registration esp_xtensa_smp_esp_command_handlers[];
  64
  65 #endif  /* OPENOCD_TARGET_XTENSA_ESP_SMP_H */