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[openocd.git] / src / target / etb.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include <string.h>
25
26 #include "arm7_9_common.h"
27 #include "etb.h"
28 #include "etm.h"
29
30 #include "log.h"
31 #include "types.h"
32 #include "binarybuffer.h"
33 #include "target.h"
34 #include "register.h"
35 #include "jtag.h"
36
37 #include <stdlib.h>
38
39 char* etb_reg_list[] =
40 {
41 "ETB_identification",
42 "ETB_ram_depth",
43 "ETB_ram_width",
44 "ETB_status",
45 "ETB_ram_data",
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
49 "ETB_control",
50 };
51
52 int etb_reg_arch_type = -1;
53
54 int etb_get_reg(reg_t *reg);
55 int etb_set_reg(reg_t *reg, u32 value);
56 int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
57
58 int etb_write_reg(reg_t *reg, u32 value);
59 int etb_read_reg(reg_t *reg);
60
61 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
62
63 int etb_set_instr(etb_t *etb, u32 new_instr)
64 {
65 jtag_device_t *device = jtag_get_device(etb->chain_pos);
66
67 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
68 {
69 scan_field_t field;
70
71 field.device = etb->chain_pos;
72 field.num_bits = device->ir_length;
73 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
74 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
75 field.out_mask = NULL;
76 field.in_value = NULL;
77 field.in_check_value = NULL;
78 field.in_check_mask = NULL;
79 field.in_handler = NULL;
80 field.in_handler_priv = NULL;
81
82 jtag_add_ir_scan(1, &field, -1);
83
84 free(field.out_value);
85 }
86
87 return ERROR_OK;
88 }
89
90 int etb_scann(etb_t *etb, u32 new_scan_chain)
91 {
92 if(etb->cur_scan_chain != new_scan_chain)
93 {
94 scan_field_t field;
95
96 field.device = etb->chain_pos;
97 field.num_bits = 5;
98 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
99 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
100 field.out_mask = NULL;
101 field.in_value = NULL;
102 field.in_check_value = NULL;
103 field.in_check_mask = NULL;
104 field.in_handler = NULL;
105 field.in_handler_priv = NULL;
106
107 /* select INTEST instruction */
108 etb_set_instr(etb, 0x2);
109 jtag_add_dr_scan(1, &field, -1);
110
111 etb->cur_scan_chain = new_scan_chain;
112
113 free(field.out_value);
114 }
115
116 return ERROR_OK;
117 }
118
119 reg_cache_t* etb_build_reg_cache(etb_t *etb)
120 {
121 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
122 reg_t *reg_list = NULL;
123 etb_reg_t *arch_info = NULL;
124 int num_regs = 9;
125 int i;
126
127 /* register a register arch-type for etm registers only once */
128 if (etb_reg_arch_type == -1)
129 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
130
131 /* the actual registers are kept in two arrays */
132 reg_list = calloc(num_regs, sizeof(reg_t));
133 arch_info = calloc(num_regs, sizeof(etb_reg_t));
134
135 /* fill in values for the reg cache */
136 reg_cache->name = "etb registers";
137 reg_cache->next = NULL;
138 reg_cache->reg_list = reg_list;
139 reg_cache->num_regs = num_regs;
140
141 /* set up registers */
142 for (i = 0; i < num_regs; i++)
143 {
144 reg_list[i].name = etb_reg_list[i];
145 reg_list[i].size = 32;
146 reg_list[i].dirty = 0;
147 reg_list[i].valid = 0;
148 reg_list[i].bitfield_desc = NULL;
149 reg_list[i].num_bitfields = 0;
150 reg_list[i].value = calloc(1, 4);
151 reg_list[i].arch_info = &arch_info[i];
152 reg_list[i].arch_type = etb_reg_arch_type;
153 reg_list[i].size = 32;
154 arch_info[i].addr = i;
155 arch_info[i].etb = etb;
156 }
157
158 return reg_cache;
159 }
160
161 int etb_get_reg(reg_t *reg)
162 {
163 if (etb_read_reg(reg) != ERROR_OK)
164 {
165 ERROR("BUG: error scheduling etm register read");
166 exit(-1);
167 }
168
169 if (jtag_execute_queue() != ERROR_OK)
170 {
171 ERROR("register read failed");
172 }
173
174 return ERROR_OK;
175 }
176
177 int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
178 {
179 scan_field_t fields[3];
180 int i;
181
182 jtag_add_end_state(TAP_RTI);
183 etb_scann(etb, 0x0);
184 etb_set_instr(etb, 0xc);
185
186 fields[0].device = etb->chain_pos;
187 fields[0].num_bits = 32;
188 fields[0].out_value = NULL;
189 fields[0].out_mask = NULL;
190 fields[0].in_value = NULL;
191 fields[0].in_check_value = NULL;
192 fields[0].in_check_mask = NULL;
193 fields[0].in_handler = NULL;
194 fields[0].in_handler_priv = NULL;
195
196 fields[1].device = etb->chain_pos;
197 fields[1].num_bits = 7;
198 fields[1].out_value = malloc(1);
199 buf_set_u32(fields[1].out_value, 0, 7, 4);
200 fields[1].out_mask = NULL;
201 fields[1].in_value = NULL;
202 fields[1].in_check_value = NULL;
203 fields[1].in_check_mask = NULL;
204 fields[1].in_handler = NULL;
205 fields[1].in_handler_priv = NULL;
206
207 fields[2].device = etb->chain_pos;
208 fields[2].num_bits = 1;
209 fields[2].out_value = malloc(1);
210 buf_set_u32(fields[2].out_value, 0, 1, 0);
211 fields[2].out_mask = NULL;
212 fields[2].in_value = NULL;
213 fields[2].in_check_value = NULL;
214 fields[2].in_check_mask = NULL;
215 fields[2].in_handler = NULL;
216 fields[2].in_handler_priv = NULL;
217
218 jtag_add_dr_scan(3, fields, -1);
219
220 fields[0].in_handler = buf_to_u32_handler;
221
222 for (i = 0; i < num_frames; i++)
223 {
224 /* ensure nR/W reamins set to read */
225 buf_set_u32(fields[2].out_value, 0, 1, 0);
226
227 /* address remains set to 0x4 (RAM data) until we read the last frame */
228 if (i < num_frames - 1)
229 buf_set_u32(fields[1].out_value, 0, 7, 4);
230 else
231 buf_set_u32(fields[1].out_value, 0, 7, 0);
232
233 fields[0].in_handler_priv = &data[i];
234 jtag_add_dr_scan(3, fields, -1);
235 }
236
237 jtag_execute_queue();
238
239 free(fields[1].out_value);
240 free(fields[2].out_value);
241
242 return ERROR_OK;
243 }
244
245 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
246 {
247 etb_reg_t *etb_reg = reg->arch_info;
248 u8 reg_addr = etb_reg->addr & 0x7f;
249 scan_field_t fields[3];
250
251 DEBUG("%i", etb_reg->addr);
252
253 jtag_add_end_state(TAP_RTI);
254 etb_scann(etb_reg->etb, 0x0);
255 etb_set_instr(etb_reg->etb, 0xc);
256
257 fields[0].device = etb_reg->etb->chain_pos;
258 fields[0].num_bits = 32;
259 fields[0].out_value = reg->value;
260 fields[0].out_mask = NULL;
261 fields[0].in_value = NULL;
262 fields[0].in_check_value = NULL;
263 fields[0].in_check_mask = NULL;
264 fields[0].in_handler = NULL;
265 fields[0].in_handler_priv = NULL;
266
267 fields[1].device = etb_reg->etb->chain_pos;
268 fields[1].num_bits = 7;
269 fields[1].out_value = malloc(1);
270 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
271 fields[1].out_mask = NULL;
272 fields[1].in_value = NULL;
273 fields[1].in_check_value = NULL;
274 fields[1].in_check_mask = NULL;
275 fields[1].in_handler = NULL;
276 fields[1].in_handler_priv = NULL;
277
278 fields[2].device = etb_reg->etb->chain_pos;
279 fields[2].num_bits = 1;
280 fields[2].out_value = malloc(1);
281 buf_set_u32(fields[2].out_value, 0, 1, 0);
282 fields[2].out_mask = NULL;
283 fields[2].in_value = NULL;
284 fields[2].in_check_value = NULL;
285 fields[2].in_check_mask = NULL;
286 fields[2].in_handler = NULL;
287 fields[2].in_handler_priv = NULL;
288
289 jtag_add_dr_scan(3, fields, -1);
290
291 /* read the identification register in the second run, to make sure we
292 * don't read the ETB data register twice, skipping every second entry
293 */
294 buf_set_u32(fields[1].out_value, 0, 7, 0x0);
295 fields[0].in_value = reg->value;
296
297 jtag_set_check_value(fields+0, check_value, check_mask, NULL);
298
299 jtag_add_dr_scan(3, fields, -1);
300
301 free(fields[1].out_value);
302 free(fields[2].out_value);
303
304 return ERROR_OK;
305 }
306
307 int etb_read_reg(reg_t *reg)
308 {
309 return etb_read_reg_w_check(reg, NULL, NULL);
310 }
311
312 int etb_set_reg(reg_t *reg, u32 value)
313 {
314 if (etb_write_reg(reg, value) != ERROR_OK)
315 {
316 ERROR("BUG: error scheduling etm register write");
317 exit(-1);
318 }
319
320 buf_set_u32(reg->value, 0, reg->size, value);
321 reg->valid = 1;
322 reg->dirty = 0;
323
324 return ERROR_OK;
325 }
326
327 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
328 {
329 etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
330
331 if (jtag_execute_queue() != ERROR_OK)
332 {
333 ERROR("register write failed");
334 exit(-1);
335 }
336 return ERROR_OK;
337 }
338
339 int etb_write_reg(reg_t *reg, u32 value)
340 {
341 etb_reg_t *etb_reg = reg->arch_info;
342 u8 reg_addr = etb_reg->addr & 0x7f;
343 scan_field_t fields[3];
344
345 DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
346
347 jtag_add_end_state(TAP_RTI);
348 etb_scann(etb_reg->etb, 0x0);
349 etb_set_instr(etb_reg->etb, 0xc);
350
351 fields[0].device = etb_reg->etb->chain_pos;
352 fields[0].num_bits = 32;
353 fields[0].out_value = malloc(4);
354 buf_set_u32(fields[0].out_value, 0, 32, value);
355 fields[0].out_mask = NULL;
356 fields[0].in_value = NULL;
357 fields[0].in_check_value = NULL;
358 fields[0].in_check_mask = NULL;
359 fields[0].in_handler = NULL;
360 fields[0].in_handler_priv = NULL;
361
362 fields[1].device = etb_reg->etb->chain_pos;
363 fields[1].num_bits = 7;
364 fields[1].out_value = malloc(1);
365 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
366 fields[1].out_mask = NULL;
367 fields[1].in_value = NULL;
368 fields[1].in_check_value = NULL;
369 fields[1].in_check_mask = NULL;
370 fields[1].in_handler = NULL;
371 fields[1].in_handler_priv = NULL;
372
373 fields[2].device = etb_reg->etb->chain_pos;
374 fields[2].num_bits = 1;
375 fields[2].out_value = malloc(1);
376 buf_set_u32(fields[2].out_value, 0, 1, 1);
377 fields[2].out_mask = NULL;
378 fields[2].in_value = NULL;
379 fields[2].in_check_value = NULL;
380 fields[2].in_check_mask = NULL;
381 fields[2].in_handler = NULL;
382 fields[2].in_handler_priv = NULL;
383
384 jtag_add_dr_scan(3, fields, -1);
385
386 free(fields[0].out_value);
387 free(fields[1].out_value);
388 free(fields[2].out_value);
389
390 return ERROR_OK;
391 }
392
393 int etb_store_reg(reg_t *reg)
394 {
395 return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
396 }
397
398 int etb_register_commands(struct command_context_s *cmd_ctx)
399 {
400 command_t *etb_cmd;
401
402 etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
403
404 register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
405
406 return ERROR_OK;
407 }
408
409 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
410 {
411 target_t *target;
412 jtag_device_t *jtag_device;
413 armv4_5_common_t *armv4_5;
414 arm7_9_common_t *arm7_9;
415
416 if (argc != 2)
417 {
418 ERROR("incomplete 'etb config <target> <chain_pos>' command");
419 exit(-1);
420 }
421
422 target = get_target_by_num(strtoul(args[0], NULL, 0));
423
424 if (!target)
425 {
426 ERROR("target number '%s' not defined", args[0]);
427 exit(-1);
428 }
429
430 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
431 {
432 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
433 return ERROR_OK;
434 }
435
436 jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
437
438 if (!jtag_device)
439 {
440 ERROR("jtag device number '%s' not defined", args[1]);
441 exit(-1);
442 }
443
444 if (arm7_9->etm_ctx)
445 {
446 etb_t *etb = malloc(sizeof(etb_t));
447
448 arm7_9->etm_ctx->capture_driver_priv = etb;
449
450 etb->chain_pos = strtoul(args[1], NULL, 0);
451 etb->cur_scan_chain = -1;
452 etb->reg_cache = NULL;
453 etb->ram_width = 0;
454 etb->ram_depth = 0;
455 }
456 else
457 {
458 ERROR("target has no ETM defined, ETB left unconfigured");
459 }
460
461 return ERROR_OK;
462 }
463
464 int etb_init(etm_context_t *etm_ctx)
465 {
466 etb_t *etb = etm_ctx->capture_driver_priv;
467
468 etb->etm_ctx = etm_ctx;
469
470 /* identify ETB RAM depth and width */
471 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
472 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
473 jtag_execute_queue();
474
475 etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
476 etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
477
478 return ERROR_OK;
479 }
480
481 trace_status_t etb_status(etm_context_t *etm_ctx)
482 {
483 etb_t *etb = etm_ctx->capture_driver_priv;
484
485 etb->etm_ctx = etm_ctx;
486
487 /* if tracing is currently idle, return this information */
488 if (etm_ctx->capture_status == TRACE_IDLE)
489 {
490 return etm_ctx->capture_status;
491 }
492 else if (etm_ctx->capture_status & TRACE_RUNNING)
493 {
494 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
495 int etb_timeout = 100;
496
497 /* trace is running, check the ETB status flags */
498 etb_get_reg(etb_status_reg);
499
500 /* check Full bit to identify an overflow */
501 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
502 etm_ctx->capture_status |= TRACE_OVERFLOWED;
503
504 /* check Triggered bit to identify trigger condition */
505 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
506 etm_ctx->capture_status |= TRACE_TRIGGERED;
507
508 /* check AcqComp to identify trace completion */
509 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
510 {
511 while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
512 {
513 /* wait for data formatter idle */
514 etb_get_reg(etb_status_reg);
515 }
516
517 if (etb_timeout == 0)
518 {
519 ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
520 buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
521 }
522
523 if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
524 {
525 ERROR("trace completed, but no trigger condition detected");
526 }
527
528 etm_ctx->capture_status &= ~TRACE_RUNNING;
529 etm_ctx->capture_status |= TRACE_COMPLETED;
530 }
531 }
532
533 return etm_ctx->capture_status;
534 }
535
536 int etb_read_trace(etm_context_t *etm_ctx)
537 {
538 etb_t *etb = etm_ctx->capture_driver_priv;
539 int first_frame = 0;
540 int num_frames = etb->ram_depth;
541 u32 *trace_data = NULL;
542 int i, j;
543
544 etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
545 etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
546 jtag_execute_queue();
547
548 /* check if we overflowed, and adjust first frame of the trace accordingly
549 * if we didn't overflow, read only up to the frame that would be written next,
550 * i.e. don't read invalid entries
551 */
552 if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
553 {
554 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
555 }
556 else
557 {
558 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
559 }
560
561 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
562
563 /* read data into temporary array for unpacking */
564 trace_data = malloc(sizeof(u32) * num_frames);
565 etb_read_ram(etb, trace_data, num_frames);
566
567 if (etm_ctx->trace_depth > 0)
568 {
569 free(etm_ctx->trace_data);
570 }
571
572 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
573 etm_ctx->trace_depth = num_frames * 3;
574 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
575 etm_ctx->trace_depth = num_frames * 2;
576 else
577 etm_ctx->trace_depth = num_frames;
578
579 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
580
581 for (i = 0, j = 0; i < num_frames; i++)
582 {
583 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
584 {
585 /* trace word j */
586 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
587 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
588 etm_ctx->trace_data[j].flags = 0;
589 if ((trace_data[i] & 0x80) >> 7)
590 {
591 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
592 }
593 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
594 {
595 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
596 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
597 }
598
599 /* trace word j+1 */
600 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
601 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
602 etm_ctx->trace_data[j+1].flags = 0;
603 if ((trace_data[i] & 0x8000) >> 15)
604 {
605 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
606 }
607 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
608 {
609 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
610 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
611 }
612
613 /* trace word j+2 */
614 etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
615 etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
616 etm_ctx->trace_data[j+2].flags = 0;
617 if ((trace_data[i] & 0x800000) >> 23)
618 {
619 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
620 }
621 if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
622 {
623 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
624 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
625 }
626
627 j += 3;
628 }
629 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
630 {
631 /* trace word j */
632 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
633 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
634 etm_ctx->trace_data[j].flags = 0;
635 if ((trace_data[i] & 0x800) >> 11)
636 {
637 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
638 }
639 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
640 {
641 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
642 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
643 }
644
645 /* trace word j+1 */
646 etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
647 etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
648 etm_ctx->trace_data[j+1].flags = 0;
649 if ((trace_data[i] & 0x800000) >> 23)
650 {
651 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
652 }
653 if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
654 {
655 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
656 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
657 }
658
659 j += 2;
660 }
661 else
662 {
663 /* trace word j */
664 etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
665 etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
666 etm_ctx->trace_data[j].flags = 0;
667 if ((trace_data[i] & 0x80000) >> 19)
668 {
669 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
670 }
671 if (etm_ctx->trace_data[j].pipestat == STAT_TR)
672 {
673 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
674 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
675 }
676
677 j += 1;
678 }
679 }
680
681 free(trace_data);
682
683 return ERROR_OK;
684 }
685
686 int etb_start_capture(etm_context_t *etm_ctx)
687 {
688 etb_t *etb = etm_ctx->capture_driver_priv;
689 u32 etb_ctrl_value = 0x1;
690 u32 trigger_count;
691
692 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
693 {
694 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
695 {
696 ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
697 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
698 }
699 etb_ctrl_value |= 0x2;
700 }
701
702 if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
703 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
704
705 trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
706
707 etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
708 etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
709 etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
710 jtag_execute_queue();
711
712 /* we're starting a new trace, initialize capture status */
713 etm_ctx->capture_status = TRACE_RUNNING;
714
715 return ERROR_OK;
716 }
717
718 int etb_stop_capture(etm_context_t *etm_ctx)
719 {
720 etb_t *etb = etm_ctx->capture_driver_priv;
721 reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
722
723 etb_write_reg(etb_ctrl_reg, 0x0);
724 jtag_execute_queue();
725
726 /* trace stopped, just clear running flag, but preserve others */
727 etm_ctx->capture_status &= ~TRACE_RUNNING;
728
729 return ERROR_OK;
730 }
731
732 etm_capture_driver_t etb_capture_driver =
733 {
734 .name = "etb",
735 .register_commands = etb_register_commands,
736 .init = etb_init,
737 .status = etb_status,
738 .start_capture = etb_start_capture,
739 .stop_capture = etb_stop_capture,
740 .read_trace = etb_read_trace,
741 };
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