1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm7_9_common.h"
28 static char* etb_reg_list
[] =
35 "ETB_ram_read_pointer",
36 "ETB_ram_write_pointer",
37 "ETB_trigger_counter",
41 static int etb_reg_arch_type
= -1;
43 static int etb_get_reg(reg_t
*reg
);
45 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 static int etb_set_instr(etb_t
*etb
, u32 new_instr
)
55 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
60 field
.num_bits
= tap
->ir_length
;
61 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
62 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
64 field
.in_value
= NULL
;
66 jtag_add_ir_scan(1, &field
, TAP_INVALID
);
68 free(field
.out_value
);
74 static int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
76 if (etb
->cur_scan_chain
!= new_scan_chain
)
82 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
83 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
85 field
.in_value
= NULL
;
87 /* select INTEST instruction */
88 etb_set_instr(etb
, 0x2);
89 jtag_add_dr_scan(1, &field
, TAP_INVALID
);
91 etb
->cur_scan_chain
= new_scan_chain
;
93 free(field
.out_value
);
99 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
101 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
102 reg_t
*reg_list
= NULL
;
103 etb_reg_t
*arch_info
= NULL
;
107 /* register a register arch-type for etm registers only once */
108 if (etb_reg_arch_type
== -1)
109 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
111 /* the actual registers are kept in two arrays */
112 reg_list
= calloc(num_regs
, sizeof(reg_t
));
113 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
115 /* fill in values for the reg cache */
116 reg_cache
->name
= "etb registers";
117 reg_cache
->next
= NULL
;
118 reg_cache
->reg_list
= reg_list
;
119 reg_cache
->num_regs
= num_regs
;
121 /* set up registers */
122 for (i
= 0; i
< num_regs
; i
++)
124 reg_list
[i
].name
= etb_reg_list
[i
];
125 reg_list
[i
].size
= 32;
126 reg_list
[i
].dirty
= 0;
127 reg_list
[i
].valid
= 0;
128 reg_list
[i
].bitfield_desc
= NULL
;
129 reg_list
[i
].num_bitfields
= 0;
130 reg_list
[i
].value
= calloc(1, 4);
131 reg_list
[i
].arch_info
= &arch_info
[i
];
132 reg_list
[i
].arch_type
= etb_reg_arch_type
;
133 reg_list
[i
].size
= 32;
134 arch_info
[i
].addr
= i
;
135 arch_info
[i
].etb
= etb
;
141 static int etb_get_reg(reg_t
*reg
)
145 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
147 LOG_ERROR("BUG: error scheduling etm register read");
151 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
153 LOG_ERROR("register read failed");
161 static void etb_getbuf(u8
*in
)
163 *((u32
*)in
)=buf_get_u32(in
, 0, 32);
167 static int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
169 scan_field_t fields
[3];
172 jtag_add_end_state(TAP_IDLE
);
174 etb_set_instr(etb
, 0xc);
176 fields
[0].tap
= etb
->tap
;
177 fields
[0].num_bits
= 32;
178 fields
[0].out_value
= NULL
;
179 fields
[0].in_value
= NULL
;
181 fields
[1].tap
= etb
->tap
;
182 fields
[1].num_bits
= 7;
183 fields
[1].out_value
= malloc(1);
184 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
185 fields
[1].in_value
= NULL
;
187 fields
[2].tap
= etb
->tap
;
188 fields
[2].num_bits
= 1;
189 fields
[2].out_value
= malloc(1);
190 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
191 fields
[2].in_value
= NULL
;
193 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
195 for (i
= 0; i
< num_frames
; i
++)
197 /* ensure nR/W reamins set to read */
198 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
200 /* address remains set to 0x4 (RAM data) until we read the last frame */
201 if (i
< num_frames
- 1)
202 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
204 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
206 fields
[0].in_value
= (u8
*)(data
+i
);
207 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
209 jtag_add_callback(etb_getbuf
, (u8
*)(data
+i
));
212 jtag_execute_queue();
214 free(fields
[1].out_value
);
215 free(fields
[2].out_value
);
220 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
222 etb_reg_t
*etb_reg
= reg
->arch_info
;
223 u8 reg_addr
= etb_reg
->addr
& 0x7f;
224 scan_field_t fields
[3];
226 LOG_DEBUG("%i", etb_reg
->addr
);
228 jtag_add_end_state(TAP_IDLE
);
229 etb_scann(etb_reg
->etb
, 0x0);
230 etb_set_instr(etb_reg
->etb
, 0xc);
232 fields
[0].tap
= etb_reg
->etb
->tap
;
233 fields
[0].num_bits
= 32;
234 fields
[0].out_value
= reg
->value
;
235 fields
[0].in_value
= NULL
;
236 fields
[0].check_value
= NULL
;
237 fields
[0].check_mask
= NULL
;
239 fields
[1].tap
= etb_reg
->etb
->tap
;
240 fields
[1].num_bits
= 7;
241 fields
[1].out_value
= malloc(1);
242 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
243 fields
[1].in_value
= NULL
;
244 fields
[1].check_value
= NULL
;
245 fields
[1].check_mask
= NULL
;
247 fields
[2].tap
= etb_reg
->etb
->tap
;
248 fields
[2].num_bits
= 1;
249 fields
[2].out_value
= malloc(1);
250 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
251 fields
[2].in_value
= NULL
;
252 fields
[2].check_value
= NULL
;
253 fields
[2].check_mask
= NULL
;
255 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
257 /* read the identification register in the second run, to make sure we
258 * don't read the ETB data register twice, skipping every second entry
260 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
261 fields
[0].in_value
= reg
->value
;
262 fields
[0].check_value
= check_value
;
263 fields
[0].check_mask
= check_mask
;
265 jtag_add_dr_scan_check(3, fields
, TAP_INVALID
);
267 free(fields
[1].out_value
);
268 free(fields
[2].out_value
);
273 int etb_read_reg(reg_t
*reg
)
275 return etb_read_reg_w_check(reg
, NULL
, NULL
);
278 int etb_set_reg(reg_t
*reg
, u32 value
)
282 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
284 LOG_ERROR("BUG: error scheduling etm register write");
288 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
295 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
299 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
301 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
303 LOG_ERROR("register write failed");
309 int etb_write_reg(reg_t
*reg
, u32 value
)
311 etb_reg_t
*etb_reg
= reg
->arch_info
;
312 u8 reg_addr
= etb_reg
->addr
& 0x7f;
313 scan_field_t fields
[3];
315 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
317 jtag_add_end_state(TAP_IDLE
);
318 etb_scann(etb_reg
->etb
, 0x0);
319 etb_set_instr(etb_reg
->etb
, 0xc);
321 fields
[0].tap
= etb_reg
->etb
->tap
;
322 fields
[0].num_bits
= 32;
323 fields
[0].out_value
= malloc(4);
324 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
325 fields
[0].in_value
= NULL
;
327 fields
[1].tap
= etb_reg
->etb
->tap
;
328 fields
[1].num_bits
= 7;
329 fields
[1].out_value
= malloc(1);
330 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
331 fields
[1].in_value
= NULL
;
333 fields
[2].tap
= etb_reg
->etb
->tap
;
334 fields
[2].num_bits
= 1;
335 fields
[2].out_value
= malloc(1);
336 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
338 fields
[2].in_value
= NULL
;
340 free(fields
[0].out_value
);
341 free(fields
[1].out_value
);
342 free(fields
[2].out_value
);
347 int etb_store_reg(reg_t
*reg
)
349 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
352 static int etb_register_commands(struct command_context_s
*cmd_ctx
)
356 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
358 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
363 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
367 armv4_5_common_t
*armv4_5
;
368 arm7_9_common_t
*arm7_9
;
372 return ERROR_COMMAND_SYNTAX_ERROR
;
375 target
= get_target(args
[0]);
379 LOG_ERROR("target '%s' not defined", args
[0]);
383 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
385 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
389 tap
= jtag_TapByString( args
[1] );
392 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1] );
398 etb_t
*etb
= malloc(sizeof(etb_t
));
400 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
403 etb
->cur_scan_chain
= 0xffffffff;
404 etb
->reg_cache
= NULL
;
410 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
417 static int etb_init(etm_context_t
*etm_ctx
)
419 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
421 etb
->etm_ctx
= etm_ctx
;
423 /* identify ETB RAM depth and width */
424 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
425 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
426 jtag_execute_queue();
428 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
429 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
434 static trace_status_t
etb_status(etm_context_t
*etm_ctx
)
436 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
438 etb
->etm_ctx
= etm_ctx
;
440 /* if tracing is currently idle, return this information */
441 if (etm_ctx
->capture_status
== TRACE_IDLE
)
443 return etm_ctx
->capture_status
;
445 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
447 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
448 int etb_timeout
= 100;
450 /* trace is running, check the ETB status flags */
451 etb_get_reg(etb_status_reg
);
453 /* check Full bit to identify an overflow */
454 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
455 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
457 /* check Triggered bit to identify trigger condition */
458 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
459 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
461 /* check AcqComp to identify trace completion */
462 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
464 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
466 /* wait for data formatter idle */
467 etb_get_reg(etb_status_reg
);
470 if (etb_timeout
== 0)
472 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
473 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
476 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
478 LOG_ERROR("trace completed, but no trigger condition detected");
481 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
482 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
486 return etm_ctx
->capture_status
;
489 static int etb_read_trace(etm_context_t
*etm_ctx
)
491 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
493 int num_frames
= etb
->ram_depth
;
494 u32
*trace_data
= NULL
;
497 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
498 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
499 jtag_execute_queue();
501 /* check if we overflowed, and adjust first frame of the trace accordingly
502 * if we didn't overflow, read only up to the frame that would be written next,
503 * i.e. don't read invalid entries
505 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
507 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
511 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
514 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
516 /* read data into temporary array for unpacking */
517 trace_data
= malloc(sizeof(u32
) * num_frames
);
518 etb_read_ram(etb
, trace_data
, num_frames
);
520 if (etm_ctx
->trace_depth
> 0)
522 free(etm_ctx
->trace_data
);
525 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
526 etm_ctx
->trace_depth
= num_frames
* 3;
527 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
528 etm_ctx
->trace_depth
= num_frames
* 2;
530 etm_ctx
->trace_depth
= num_frames
;
532 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
534 for (i
= 0, j
= 0; i
< num_frames
; i
++)
536 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
539 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
540 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
541 etm_ctx
->trace_data
[j
].flags
= 0;
542 if ((trace_data
[i
] & 0x80) >> 7)
544 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
546 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
548 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
549 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
553 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
554 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
555 etm_ctx
->trace_data
[j
+1].flags
= 0;
556 if ((trace_data
[i
] & 0x8000) >> 15)
558 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
560 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
562 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
563 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
567 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
568 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
569 etm_ctx
->trace_data
[j
+2].flags
= 0;
570 if ((trace_data
[i
] & 0x800000) >> 23)
572 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
574 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
576 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
577 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
582 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
585 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
586 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
587 etm_ctx
->trace_data
[j
].flags
= 0;
588 if ((trace_data
[i
] & 0x800) >> 11)
590 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
592 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
594 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
595 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
599 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
600 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
601 etm_ctx
->trace_data
[j
+1].flags
= 0;
602 if ((trace_data
[i
] & 0x800000) >> 23)
604 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
606 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
608 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
609 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
617 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
618 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
619 etm_ctx
->trace_data
[j
].flags
= 0;
620 if ((trace_data
[i
] & 0x80000) >> 19)
622 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
624 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
626 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
627 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
639 static int etb_start_capture(etm_context_t
*etm_ctx
)
641 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
642 u32 etb_ctrl_value
= 0x1;
645 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
647 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
649 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
650 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
652 etb_ctrl_value
|= 0x2;
655 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
656 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
658 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
660 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
661 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
662 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
663 jtag_execute_queue();
665 /* we're starting a new trace, initialize capture status */
666 etm_ctx
->capture_status
= TRACE_RUNNING
;
671 static int etb_stop_capture(etm_context_t
*etm_ctx
)
673 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
674 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
676 etb_write_reg(etb_ctrl_reg
, 0x0);
677 jtag_execute_queue();
679 /* trace stopped, just clear running flag, but preserve others */
680 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
685 etm_capture_driver_t etb_capture_driver
=
688 .register_commands
= etb_register_commands
,
690 .status
= etb_status
,
691 .start_capture
= etb_start_capture
,
692 .stop_capture
= etb_stop_capture
,
693 .read_trace
= etb_read_trace
,
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