1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 static char* etb_reg_list
[] =
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
52 static int etb_reg_arch_type
= -1;
54 static int etb_get_reg(reg_t
*reg
);
56 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 static int etb_set_instr(etb_t
*etb
, u32 new_instr
)
66 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
71 field
.num_bits
= tap
->ir_length
;
72 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
73 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
75 field
.in_value
= NULL
;
77 jtag_add_ir_scan(1, &field
, TAP_INVALID
);
79 free(field
.out_value
);
85 static int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
87 if (etb
->cur_scan_chain
!= new_scan_chain
)
93 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
94 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
96 field
.in_value
= NULL
;
98 /* select INTEST instruction */
99 etb_set_instr(etb
, 0x2);
100 jtag_add_dr_scan(1, &field
, TAP_INVALID
);
102 etb
->cur_scan_chain
= new_scan_chain
;
104 free(field
.out_value
);
110 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
112 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
113 reg_t
*reg_list
= NULL
;
114 etb_reg_t
*arch_info
= NULL
;
118 /* register a register arch-type for etm registers only once */
119 if (etb_reg_arch_type
== -1)
120 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
122 /* the actual registers are kept in two arrays */
123 reg_list
= calloc(num_regs
, sizeof(reg_t
));
124 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
126 /* fill in values for the reg cache */
127 reg_cache
->name
= "etb registers";
128 reg_cache
->next
= NULL
;
129 reg_cache
->reg_list
= reg_list
;
130 reg_cache
->num_regs
= num_regs
;
132 /* set up registers */
133 for (i
= 0; i
< num_regs
; i
++)
135 reg_list
[i
].name
= etb_reg_list
[i
];
136 reg_list
[i
].size
= 32;
137 reg_list
[i
].dirty
= 0;
138 reg_list
[i
].valid
= 0;
139 reg_list
[i
].bitfield_desc
= NULL
;
140 reg_list
[i
].num_bitfields
= 0;
141 reg_list
[i
].value
= calloc(1, 4);
142 reg_list
[i
].arch_info
= &arch_info
[i
];
143 reg_list
[i
].arch_type
= etb_reg_arch_type
;
144 reg_list
[i
].size
= 32;
145 arch_info
[i
].addr
= i
;
146 arch_info
[i
].etb
= etb
;
152 static int etb_get_reg(reg_t
*reg
)
156 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
158 LOG_ERROR("BUG: error scheduling etm register read");
162 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
164 LOG_ERROR("register read failed");
171 static int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
173 scan_field_t fields
[3];
176 jtag_add_end_state(TAP_IDLE
);
178 etb_set_instr(etb
, 0xc);
180 fields
[0].tap
= etb
->tap
;
181 fields
[0].num_bits
= 32;
182 fields
[0].out_value
= NULL
;
184 fields
[0].in_value
= tmp
;
186 fields
[1].tap
= etb
->tap
;
187 fields
[1].num_bits
= 7;
188 fields
[1].out_value
= malloc(1);
189 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
190 fields
[1].in_value
= NULL
;
192 fields
[2].tap
= etb
->tap
;
193 fields
[2].num_bits
= 1;
194 fields
[2].out_value
= malloc(1);
195 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
196 fields
[2].in_value
= NULL
;
198 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
200 for (i
= 0; i
< num_frames
; i
++)
202 /* ensure nR/W reamins set to read */
203 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
205 /* address remains set to 0x4 (RAM data) until we read the last frame */
206 if (i
< num_frames
- 1)
207 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
209 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
211 jtag_add_dr_scan_now(3, fields
, TAP_INVALID
);
213 data
[i
]=buf_get_u32(tmp
, 0, 32);
216 jtag_execute_queue();
218 free(fields
[1].out_value
);
219 free(fields
[2].out_value
);
224 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
226 etb_reg_t
*etb_reg
= reg
->arch_info
;
227 u8 reg_addr
= etb_reg
->addr
& 0x7f;
228 scan_field_t fields
[3];
230 LOG_DEBUG("%i", etb_reg
->addr
);
232 jtag_add_end_state(TAP_IDLE
);
233 etb_scann(etb_reg
->etb
, 0x0);
234 etb_set_instr(etb_reg
->etb
, 0xc);
236 fields
[0].tap
= etb_reg
->etb
->tap
;
237 fields
[0].num_bits
= 32;
238 fields
[0].out_value
= reg
->value
;
239 fields
[0].in_value
= NULL
;
241 fields
[1].tap
= etb_reg
->etb
->tap
;
242 fields
[1].num_bits
= 7;
243 fields
[1].out_value
= malloc(1);
244 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
245 fields
[1].in_value
= NULL
;
247 fields
[2].tap
= etb_reg
->etb
->tap
;
248 fields
[2].num_bits
= 1;
249 fields
[2].out_value
= malloc(1);
250 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
251 fields
[2].in_value
= NULL
;
253 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
255 /* read the identification register in the second run, to make sure we
256 * don't read the ETB data register twice, skipping every second entry
258 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
259 fields
[0].in_value
= reg
->value
;
261 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
263 jtag_check_value_mask(fields
+0, check_value
, check_mask
);
265 free(fields
[1].out_value
);
266 free(fields
[2].out_value
);
271 int etb_read_reg(reg_t
*reg
)
273 return etb_read_reg_w_check(reg
, NULL
, NULL
);
276 int etb_set_reg(reg_t
*reg
, u32 value
)
280 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
282 LOG_ERROR("BUG: error scheduling etm register write");
286 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
293 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
297 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
299 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
301 LOG_ERROR("register write failed");
307 int etb_write_reg(reg_t
*reg
, u32 value
)
309 etb_reg_t
*etb_reg
= reg
->arch_info
;
310 u8 reg_addr
= etb_reg
->addr
& 0x7f;
311 scan_field_t fields
[3];
313 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
315 jtag_add_end_state(TAP_IDLE
);
316 etb_scann(etb_reg
->etb
, 0x0);
317 etb_set_instr(etb_reg
->etb
, 0xc);
319 fields
[0].tap
= etb_reg
->etb
->tap
;
320 fields
[0].num_bits
= 32;
321 fields
[0].out_value
= malloc(4);
322 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
323 fields
[0].in_value
= NULL
;
325 fields
[1].tap
= etb_reg
->etb
->tap
;
326 fields
[1].num_bits
= 7;
327 fields
[1].out_value
= malloc(1);
328 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
329 fields
[1].in_value
= NULL
;
331 fields
[2].tap
= etb_reg
->etb
->tap
;
332 fields
[2].num_bits
= 1;
333 fields
[2].out_value
= malloc(1);
334 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
336 fields
[2].in_value
= NULL
;
338 free(fields
[0].out_value
);
339 free(fields
[1].out_value
);
340 free(fields
[2].out_value
);
345 int etb_store_reg(reg_t
*reg
)
347 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
350 static int etb_register_commands(struct command_context_s
*cmd_ctx
)
354 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
356 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
361 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
365 armv4_5_common_t
*armv4_5
;
366 arm7_9_common_t
*arm7_9
;
370 return ERROR_COMMAND_SYNTAX_ERROR
;
373 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
377 LOG_ERROR("target number '%s' not defined", args
[0]);
381 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
383 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
387 tap
= jtag_TapByString( args
[1] );
390 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1] );
396 etb_t
*etb
= malloc(sizeof(etb_t
));
398 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
401 etb
->cur_scan_chain
= 0xffffffff;
402 etb
->reg_cache
= NULL
;
408 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
415 static int etb_init(etm_context_t
*etm_ctx
)
417 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
419 etb
->etm_ctx
= etm_ctx
;
421 /* identify ETB RAM depth and width */
422 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
423 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
424 jtag_execute_queue();
426 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
427 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
432 static trace_status_t
etb_status(etm_context_t
*etm_ctx
)
434 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
436 etb
->etm_ctx
= etm_ctx
;
438 /* if tracing is currently idle, return this information */
439 if (etm_ctx
->capture_status
== TRACE_IDLE
)
441 return etm_ctx
->capture_status
;
443 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
445 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
446 int etb_timeout
= 100;
448 /* trace is running, check the ETB status flags */
449 etb_get_reg(etb_status_reg
);
451 /* check Full bit to identify an overflow */
452 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
453 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
455 /* check Triggered bit to identify trigger condition */
456 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
457 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
459 /* check AcqComp to identify trace completion */
460 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
462 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
464 /* wait for data formatter idle */
465 etb_get_reg(etb_status_reg
);
468 if (etb_timeout
== 0)
470 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
471 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
474 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
476 LOG_ERROR("trace completed, but no trigger condition detected");
479 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
480 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
484 return etm_ctx
->capture_status
;
487 static int etb_read_trace(etm_context_t
*etm_ctx
)
489 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
491 int num_frames
= etb
->ram_depth
;
492 u32
*trace_data
= NULL
;
495 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
496 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
497 jtag_execute_queue();
499 /* check if we overflowed, and adjust first frame of the trace accordingly
500 * if we didn't overflow, read only up to the frame that would be written next,
501 * i.e. don't read invalid entries
503 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
505 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
509 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
512 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
514 /* read data into temporary array for unpacking */
515 trace_data
= malloc(sizeof(u32
) * num_frames
);
516 etb_read_ram(etb
, trace_data
, num_frames
);
518 if (etm_ctx
->trace_depth
> 0)
520 free(etm_ctx
->trace_data
);
523 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
524 etm_ctx
->trace_depth
= num_frames
* 3;
525 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
526 etm_ctx
->trace_depth
= num_frames
* 2;
528 etm_ctx
->trace_depth
= num_frames
;
530 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
532 for (i
= 0, j
= 0; i
< num_frames
; i
++)
534 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
537 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
538 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
539 etm_ctx
->trace_data
[j
].flags
= 0;
540 if ((trace_data
[i
] & 0x80) >> 7)
542 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
544 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
546 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
547 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
551 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
552 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
553 etm_ctx
->trace_data
[j
+1].flags
= 0;
554 if ((trace_data
[i
] & 0x8000) >> 15)
556 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
558 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
560 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
561 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
565 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
566 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
567 etm_ctx
->trace_data
[j
+2].flags
= 0;
568 if ((trace_data
[i
] & 0x800000) >> 23)
570 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
572 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
574 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
575 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
580 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
583 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
584 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
585 etm_ctx
->trace_data
[j
].flags
= 0;
586 if ((trace_data
[i
] & 0x800) >> 11)
588 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
590 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
592 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
593 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
597 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
598 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
599 etm_ctx
->trace_data
[j
+1].flags
= 0;
600 if ((trace_data
[i
] & 0x800000) >> 23)
602 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
604 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
606 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
607 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
615 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
616 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
617 etm_ctx
->trace_data
[j
].flags
= 0;
618 if ((trace_data
[i
] & 0x80000) >> 19)
620 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
622 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
624 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
625 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
637 static int etb_start_capture(etm_context_t
*etm_ctx
)
639 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
640 u32 etb_ctrl_value
= 0x1;
643 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
645 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
647 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
648 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
650 etb_ctrl_value
|= 0x2;
653 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
654 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
656 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
658 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
659 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
660 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
661 jtag_execute_queue();
663 /* we're starting a new trace, initialize capture status */
664 etm_ctx
->capture_status
= TRACE_RUNNING
;
669 static int etb_stop_capture(etm_context_t
*etm_ctx
)
671 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
672 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
674 etb_write_reg(etb_ctrl_reg
, 0x0);
675 jtag_execute_queue();
677 /* trace stopped, just clear running flag, but preserve others */
678 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
683 etm_capture_driver_t etb_capture_driver
=
686 .register_commands
= etb_register_commands
,
688 .status
= etb_status
,
689 .start_capture
= etb_start_capture
,
690 .stop_capture
= etb_stop_capture
,
691 .read_trace
= etb_read_trace
,
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