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target/cortex_a: Use 'bool' data type
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "arm.h"
23 #include "etm.h"
24 #include "etb.h"
25 #include "image.h"
26 #include "arm_disassembler.h"
27 #include "register.h"
28 #include "etm_dummy.h"
29
30 #if BUILD_OOCD_TRACE == 1
31 #include "oocd_trace.h"
32 #endif
33
34
35 /*
36 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
37 *
38 * ETM modules collect instruction and/or data trace information, compress
39 * it, and transfer it to a debugging host through either a (buffered) trace
40 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
41 *
42 * There are several generations of these modules. Original versions have
43 * JTAG access through a dedicated scan chain. Recent versions have added
44 * access via coprocessor instructions, memory addressing, and the ARM Debug
45 * Interface v5 (ADIv5); and phased out direct JTAG access.
46 *
47 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
48 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
49 * implying non-JTAG connectivity options.
50 *
51 * Relevant documentation includes:
52 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
53 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
54 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
55 */
56
57 enum {
58 RO, /* read/only */
59 WO, /* write/only */
60 RW, /* read/write */
61 };
62
63 struct etm_reg_info {
64 uint8_t addr;
65 uint8_t size; /* low-N of 32 bits */
66 uint8_t mode; /* RO, WO, RW */
67 uint8_t bcd_vers; /* 1.0, 2.0, etc */
68 const char *name;
69 };
70
71 /*
72 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
73 * (Or on some processors, through coprocessor operations.)
74 * Newer versions of ETM make some W/O registers R/W, and
75 * provide definitions for some previously-unused bits.
76 */
77
78 /* core registers used to version/configure the ETM */
79 static const struct etm_reg_info etm_core[] = {
80 /* NOTE: we "know" the order here ... */
81 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
82 { ETM_ID, 32, RO, 0x20, "ETM_id", },
83 };
84
85 /* basic registers that are always there given the right ETM version */
86 static const struct etm_reg_info etm_basic[] = {
87 /* ETM Trace Registers */
88 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
89 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
90 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
91 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
92 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
93
94 /* TraceEnable configuration */
95 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
96 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
97 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
98 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
99
100 /* ViewData configuration (data trace) */
101 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
102 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
103 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
104 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
105
106 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
107
108 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
109 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
110 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
111 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
112 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
113 };
114
115 static const struct etm_reg_info etm_fifofull[] = {
116 /* FIFOFULL configuration */
117 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
118 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
119 };
120
121 static const struct etm_reg_info etm_addr_comp[] = {
122 /* Address comparator register pairs */
123 #define ADDR_COMPARATOR(i) \
124 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
125 "ETM_addr_" #i "_comparator_value", }, \
126 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
127 "ETM_addr_" #i "_access_type", }
128 ADDR_COMPARATOR(1),
129 ADDR_COMPARATOR(2),
130 ADDR_COMPARATOR(3),
131 ADDR_COMPARATOR(4),
132 ADDR_COMPARATOR(5),
133 ADDR_COMPARATOR(6),
134 ADDR_COMPARATOR(7),
135 ADDR_COMPARATOR(8),
136
137 ADDR_COMPARATOR(9),
138 ADDR_COMPARATOR(10),
139 ADDR_COMPARATOR(11),
140 ADDR_COMPARATOR(12),
141 ADDR_COMPARATOR(13),
142 ADDR_COMPARATOR(14),
143 ADDR_COMPARATOR(15),
144 ADDR_COMPARATOR(16),
145 { 0, 0, 0, 0, NULL }
146 #undef ADDR_COMPARATOR
147 };
148
149 static const struct etm_reg_info etm_data_comp[] = {
150 /* Data Value Comparators (NOTE: odd addresses are reserved) */
151 #define DATA_COMPARATOR(i) \
152 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
153 "ETM_data_" #i "_comparator_value", }, \
154 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
155 "ETM_data_" #i "_comparator_mask", }
156 DATA_COMPARATOR(1),
157 DATA_COMPARATOR(2),
158 DATA_COMPARATOR(3),
159 DATA_COMPARATOR(4),
160 DATA_COMPARATOR(5),
161 DATA_COMPARATOR(6),
162 DATA_COMPARATOR(7),
163 DATA_COMPARATOR(8),
164 { 0, 0, 0, 0, NULL }
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
178 ETM_COUNTER(1),
179 ETM_COUNTER(2),
180 ETM_COUNTER(3),
181 ETM_COUNTER(4),
182 { 0, 0, 0, 0, NULL }
183 #undef ETM_COUNTER
184 };
185
186 static const struct etm_reg_info etm_sequencer[] = {
187 #define ETM_SEQ(i) \
188 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
189 "ETM_sequencer_event" #i, }
190 ETM_SEQ(0), /* 1->2 */
191 ETM_SEQ(1), /* 2->1 */
192 ETM_SEQ(2), /* 2->3 */
193 ETM_SEQ(3), /* 3->1 */
194 ETM_SEQ(4), /* 3->2 */
195 ETM_SEQ(5), /* 1->3 */
196 #undef ETM_SEQ
197 /* 0x66 reserved */
198 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
199 };
200
201 static const struct etm_reg_info etm_outputs[] = {
202 #define ETM_OUTPUT(i) \
203 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
204 "ETM_external_output" #i, }
205
206 ETM_OUTPUT(1),
207 ETM_OUTPUT(2),
208 ETM_OUTPUT(3),
209 ETM_OUTPUT(4),
210 { 0, 0, 0, 0, NULL }
211 #undef ETM_OUTPUT
212 };
213
214 #if 0
215 /* registers from 0x6c..0x7f were added after ETMv1.3 */
216
217 /* Context ID Comparators */
218 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
219 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
220 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
221 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
222 #endif
223
224 static int etm_get_reg(struct reg *reg);
225 static int etm_read_reg_w_check(struct reg *reg,
226 uint8_t *check_value, uint8_t *check_mask);
227 static int etm_register_user_commands(struct command_context *cmd_ctx);
228 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
229 static int etm_write_reg(struct reg *reg, uint32_t value);
230
231 static const struct reg_arch_type etm_scan6_type = {
232 .get = etm_get_reg,
233 .set = etm_set_reg_w_exec,
234 };
235
236 /* Look up register by ID ... most ETM instances only
237 * support a subset of the possible registers.
238 */
239 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
240 {
241 struct reg_cache *cache = etm_ctx->reg_cache;
242 unsigned i;
243
244 for (i = 0; i < cache->num_regs; i++) {
245 struct etm_reg *reg = cache->reg_list[i].arch_info;
246
247 if (reg->reg_info->addr == id)
248 return &cache->reg_list[i];
249 }
250
251 /* caller asking for nonexistent register is a bug!
252 * REVISIT say which of the N targets was involved */
253 LOG_ERROR("ETM: register 0x%02x not available", id);
254 return NULL;
255 }
256
257 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
258 struct reg_cache *cache, struct etm_reg *ereg,
259 const struct etm_reg_info *r, unsigned nreg)
260 {
261 struct reg *reg = cache->reg_list;
262
263 reg += cache->num_regs;
264 ereg += cache->num_regs;
265
266 /* add up to "nreg" registers from "r", if supported by this
267 * version of the ETM, to the specified cache.
268 */
269 for (; nreg--; r++) {
270 /* No more registers to add */
271 if (!r->size) {
272 LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
273 return;
274 }
275
276 /* this ETM may be too old to have some registers */
277 if (r->bcd_vers > bcd_vers)
278 continue;
279
280 reg->name = r->name;
281 reg->size = r->size;
282 reg->value = &ereg->value;
283 reg->arch_info = ereg;
284 reg->type = &etm_scan6_type;
285 reg++;
286 cache->num_regs++;
287
288 ereg->reg_info = r;
289 ereg->jtag_info = jtag_info;
290 ereg++;
291 }
292 }
293
294 struct reg_cache *etm_build_reg_cache(struct target *target,
295 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
296 {
297 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
298 struct reg *reg_list = NULL;
299 struct etm_reg *arch_info = NULL;
300 unsigned bcd_vers, config;
301
302 /* the actual registers are kept in two arrays */
303 reg_list = calloc(128, sizeof(struct reg));
304 arch_info = calloc(128, sizeof(struct etm_reg));
305
306 /* fill in values for the reg cache */
307 reg_cache->name = "etm registers";
308 reg_cache->next = NULL;
309 reg_cache->reg_list = reg_list;
310 reg_cache->num_regs = 0;
311
312 /* add ETM_CONFIG, then parse its values to see
313 * which other registers exist in this ETM
314 */
315 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
316 etm_core, 1);
317
318 etm_get_reg(reg_list);
319 etm_ctx->config = buf_get_u32(arch_info->value, 0, 32);
320 config = etm_ctx->config;
321
322 /* figure ETM version then add base registers */
323 if (config & (1 << 31)) {
324 LOG_WARNING("ETMv2+ support is incomplete");
325
326 /* REVISIT more registers may exist; they may now be
327 * readable; more register bits have defined meanings;
328 * don't presume trace start/stop support is present;
329 * and include any context ID comparator registers.
330 */
331 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
332 etm_core + 1, 1);
333 etm_get_reg(reg_list + 1);
334 etm_ctx->id = buf_get_u32(
335 arch_info[1].value, 0, 32);
336 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
337 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
338
339 } else {
340 switch (config >> 28) {
341 case 7:
342 case 5:
343 case 3:
344 bcd_vers = 0x13;
345 break;
346 case 4:
347 case 2:
348 bcd_vers = 0x12;
349 break;
350 case 1:
351 bcd_vers = 0x11;
352 break;
353 case 0:
354 bcd_vers = 0x10;
355 break;
356 default:
357 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
358 goto fail;
359 }
360 }
361 etm_ctx->bcd_vers = bcd_vers;
362 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
363
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_basic, ARRAY_SIZE(etm_basic));
366
367 /* address and data comparators; counters; outputs */
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_addr_comp, 4 * (0x0f & (config >> 0)));
370 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
371 etm_data_comp, 2 * (0x0f & (config >> 4)));
372 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
373 etm_counters, 4 * (0x07 & (config >> 13)));
374 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
375 etm_outputs, (0x07 & (config >> 20)));
376
377 /* FIFOFULL presence is optional
378 * REVISIT for ETMv1.2 and later, don't bother adding this
379 * unless ETM_SYS_CONFIG says it's also *supported* ...
380 */
381 if (config & (1 << 23))
382 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
383 etm_fifofull, ARRAY_SIZE(etm_fifofull));
384
385 /* sequencer is optional (for state-dependant triggering) */
386 if (config & (1 << 16))
387 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
388 etm_sequencer, ARRAY_SIZE(etm_sequencer));
389
390 /* REVISIT could realloc and likely save half the memory
391 * in the two chunks we allocated...
392 */
393
394 /* the ETM might have an ETB connected */
395 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
396 struct etb *etb = etm_ctx->capture_driver_priv;
397
398 if (!etb) {
399 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
400 goto fail;
401 }
402
403 reg_cache->next = etb_build_reg_cache(etb);
404
405 etb->reg_cache = reg_cache->next;
406 }
407
408 etm_ctx->reg_cache = reg_cache;
409 return reg_cache;
410
411 fail:
412 free(reg_cache);
413 free(reg_list);
414 free(arch_info);
415 return NULL;
416 }
417
418 static int etm_read_reg(struct reg *reg)
419 {
420 return etm_read_reg_w_check(reg, NULL, NULL);
421 }
422
423 static int etm_store_reg(struct reg *reg)
424 {
425 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
426 }
427
428 int etm_setup(struct target *target)
429 {
430 int retval;
431 uint32_t etm_ctrl_value;
432 struct arm *arm = target_to_arm(target);
433 struct etm_context *etm_ctx = arm->etm;
434 struct reg *etm_ctrl_reg;
435
436 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
437 if (!etm_ctrl_reg)
438 return ERROR_OK;
439
440 /* initialize some ETM control register settings */
441 etm_get_reg(etm_ctrl_reg);
442 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
443
444 /* clear the ETM powerdown bit (0) */
445 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
446
447 /* configure port width (21,6:4), mode (13,17:16) and
448 * for older modules clocking (13)
449 */
450 etm_ctrl_value = (etm_ctrl_value
451 & ~ETM_PORT_WIDTH_MASK
452 & ~ETM_PORT_MODE_MASK
453 & ~ETM_CTRL_DBGRQ
454 & ~ETM_PORT_CLOCK_MASK)
455 | etm_ctx->control;
456
457 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
458 etm_store_reg(etm_ctrl_reg);
459
460 etm_ctx->control = etm_ctrl_value;
461
462 retval = jtag_execute_queue();
463 if (retval != ERROR_OK)
464 return retval;
465
466 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
467 * verify that those width and mode settings are OK ...
468 */
469
470 retval = etm_ctx->capture_driver->init(etm_ctx);
471 if (retval != ERROR_OK) {
472 LOG_ERROR("ETM capture driver initialization failed");
473 return retval;
474 }
475 return ERROR_OK;
476 }
477
478 static int etm_get_reg(struct reg *reg)
479 {
480 int retval;
481
482 retval = etm_read_reg(reg);
483 if (retval != ERROR_OK) {
484 LOG_ERROR("BUG: error scheduling etm register read");
485 return retval;
486 }
487
488 retval = jtag_execute_queue();
489 if (retval != ERROR_OK) {
490 LOG_ERROR("register read failed");
491 return retval;
492 }
493
494 return ERROR_OK;
495 }
496
497 static int etm_read_reg_w_check(struct reg *reg,
498 uint8_t *check_value, uint8_t *check_mask)
499 {
500 struct etm_reg *etm_reg = reg->arch_info;
501 const struct etm_reg_info *r = etm_reg->reg_info;
502 uint8_t reg_addr = r->addr & 0x7f;
503 struct scan_field fields[3];
504 int retval;
505
506 if (etm_reg->reg_info->mode == WO) {
507 LOG_ERROR("BUG: can't read write-only register %s", r->name);
508 return ERROR_COMMAND_SYNTAX_ERROR;
509 }
510
511 LOG_DEBUG("%s (%u)", r->name, reg_addr);
512
513 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
514 if (retval != ERROR_OK)
515 return retval;
516 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
517 etm_reg->jtag_info->intest_instr,
518 NULL,
519 TAP_IDLE);
520 if (retval != ERROR_OK)
521 return retval;
522
523 fields[0].num_bits = 32;
524 fields[0].out_value = reg->value;
525 fields[0].in_value = NULL;
526 fields[0].check_value = NULL;
527 fields[0].check_mask = NULL;
528
529 fields[1].num_bits = 7;
530 uint8_t temp1;
531 fields[1].out_value = &temp1;
532 buf_set_u32(&temp1, 0, 7, reg_addr);
533 fields[1].in_value = NULL;
534 fields[1].check_value = NULL;
535 fields[1].check_mask = NULL;
536
537 fields[2].num_bits = 1;
538 uint8_t temp2;
539 fields[2].out_value = &temp2;
540 buf_set_u32(&temp2, 0, 1, 0);
541 fields[2].in_value = NULL;
542 fields[2].check_value = NULL;
543 fields[2].check_mask = NULL;
544
545 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
546
547 fields[0].in_value = reg->value;
548 fields[0].check_value = check_value;
549 fields[0].check_mask = check_mask;
550
551 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
552
553 return ERROR_OK;
554 }
555
556 static int etm_set_reg(struct reg *reg, uint32_t value)
557 {
558 int retval = etm_write_reg(reg, value);
559 if (retval != ERROR_OK) {
560 LOG_ERROR("BUG: error scheduling etm register write");
561 return retval;
562 }
563
564 buf_set_u32(reg->value, 0, reg->size, value);
565 reg->valid = 1;
566 reg->dirty = 0;
567
568 return ERROR_OK;
569 }
570
571 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
572 {
573 int retval;
574
575 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
576
577 retval = jtag_execute_queue();
578 if (retval != ERROR_OK) {
579 LOG_ERROR("register write failed");
580 return retval;
581 }
582 return ERROR_OK;
583 }
584
585 static int etm_write_reg(struct reg *reg, uint32_t value)
586 {
587 struct etm_reg *etm_reg = reg->arch_info;
588 const struct etm_reg_info *r = etm_reg->reg_info;
589 uint8_t reg_addr = r->addr & 0x7f;
590 struct scan_field fields[3];
591 int retval;
592
593 if (etm_reg->reg_info->mode == RO) {
594 LOG_ERROR("BUG: can't write read--only register %s", r->name);
595 return ERROR_COMMAND_SYNTAX_ERROR;
596 }
597
598 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
599
600 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
601 if (retval != ERROR_OK)
602 return retval;
603 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
604 etm_reg->jtag_info->intest_instr,
605 NULL,
606 TAP_IDLE);
607 if (retval != ERROR_OK)
608 return retval;
609
610 fields[0].num_bits = 32;
611 uint8_t tmp1[4];
612 fields[0].out_value = tmp1;
613 buf_set_u32(tmp1, 0, 32, value);
614 fields[0].in_value = NULL;
615
616 fields[1].num_bits = 7;
617 uint8_t tmp2;
618 fields[1].out_value = &tmp2;
619 buf_set_u32(&tmp2, 0, 7, reg_addr);
620 fields[1].in_value = NULL;
621
622 fields[2].num_bits = 1;
623 uint8_t tmp3;
624 fields[2].out_value = &tmp3;
625 buf_set_u32(&tmp3, 0, 1, 1);
626 fields[2].in_value = NULL;
627
628 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
629
630 return ERROR_OK;
631 }
632
633
634 /* ETM trace analysis functionality */
635
636 static struct etm_capture_driver *etm_capture_drivers[] = {
637 &etb_capture_driver,
638 &etm_dummy_capture_driver,
639 #if BUILD_OOCD_TRACE == 1
640 &oocd_trace_capture_driver,
641 #endif
642 NULL
643 };
644
645 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
646 {
647 int i;
648 int section = -1;
649 size_t size_read;
650 uint32_t opcode;
651 int retval;
652
653 if (!ctx->image)
654 return ERROR_TRACE_IMAGE_UNAVAILABLE;
655
656 /* search for the section the current instruction belongs to */
657 for (i = 0; i < ctx->image->num_sections; i++) {
658 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
659 (ctx->image->sections[i].base_address + ctx->image->sections[i].size >
660 ctx->current_pc)) {
661 section = i;
662 break;
663 }
664 }
665
666 if (section == -1) {
667 /* current instruction couldn't be found in the image */
668 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
669 }
670
671 if (ctx->core_state == ARM_STATE_ARM) {
672 uint8_t buf[4];
673 retval = image_read_section(ctx->image, section,
674 ctx->current_pc -
675 ctx->image->sections[section].base_address,
676 4, buf, &size_read);
677 if (retval != ERROR_OK) {
678 LOG_ERROR("error while reading instruction");
679 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
680 }
681 opcode = target_buffer_get_u32(ctx->target, buf);
682 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
683 } else if (ctx->core_state == ARM_STATE_THUMB) {
684 uint8_t buf[2];
685 retval = image_read_section(ctx->image, section,
686 ctx->current_pc -
687 ctx->image->sections[section].base_address,
688 2, buf, &size_read);
689 if (retval != ERROR_OK) {
690 LOG_ERROR("error while reading instruction");
691 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
692 }
693 opcode = target_buffer_get_u16(ctx->target, buf);
694 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
695 } else if (ctx->core_state == ARM_STATE_JAZELLE) {
696 LOG_ERROR("BUG: tracing of jazelle code not supported");
697 return ERROR_FAIL;
698 } else {
699 LOG_ERROR("BUG: unknown core state encountered");
700 return ERROR_FAIL;
701 }
702
703 return ERROR_OK;
704 }
705
706 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
707 {
708 while (ctx->data_index < ctx->trace_depth) {
709 /* if the caller specified an address packet offset, skip until the
710 * we reach the n-th cycle marked with tracesync */
711 if (apo > 0) {
712 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
713 apo--;
714
715 if (apo > 0) {
716 ctx->data_index++;
717 ctx->data_half = 0;
718 }
719 continue;
720 }
721
722 /* no tracedata output during a TD cycle
723 * or in a trigger cycle */
724 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
725 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
726 ctx->data_index++;
727 ctx->data_half = 0;
728 continue;
729 }
730
731 /* FIXME there are more port widths than these... */
732 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
733 if (ctx->data_half == 0) {
734 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
735 ctx->data_half = 1;
736 } else {
737 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
738 ctx->data_half = 0;
739 ctx->data_index++;
740 }
741 } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
742 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
743 ctx->data_index++;
744 } else {
745 /* on a 4-bit port, a packet will be output during two consecutive cycles */
746 if (ctx->data_index > (ctx->trace_depth - 2))
747 return -1;
748
749 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
750 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
751 ctx->data_index += 2;
752 }
753
754 return 0;
755 }
756
757 return -1;
758 }
759
760 static int etmv1_branch_address(struct etm_context *ctx)
761 {
762 int retval;
763 uint8_t packet;
764 int shift = 0;
765 int apo;
766 uint32_t i;
767
768 /* quit analysis if less than two cycles are left in the trace
769 * because we can't extract the APO */
770 if (ctx->data_index > (ctx->trace_depth - 2))
771 return -1;
772
773 /* a BE could be output during an APO cycle, skip the current
774 * and continue with the new one */
775 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
776 return 1;
777 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
778 return 2;
779
780 /* address packet offset encoded in the next two cycles' pipestat bits */
781 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
782 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
783
784 /* count number of tracesync cycles between current pipe_index and data_index
785 * i.e. the number of tracesyncs that data_index already passed by
786 * to subtract them from the APO */
787 for (i = ctx->pipe_index; i < ctx->data_index; i++) {
788 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
789 apo--;
790 }
791
792 /* extract up to four 7-bit packets */
793 do {
794 retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
795 if (retval != 0)
796 return -1;
797 ctx->last_branch &= ~(0x7f << shift);
798 ctx->last_branch |= (packet & 0x7f) << shift;
799 shift += 7;
800 } while ((packet & 0x80) && (shift < 28));
801
802 /* one last packet holding 4 bits of the address, plus the branch reason code */
803 if ((shift == 28) && (packet & 0x80)) {
804 retval = etmv1_next_packet(ctx, &packet, 0);
805 if (retval != 0)
806 return -1;
807 ctx->last_branch &= 0x0fffffff;
808 ctx->last_branch |= (packet & 0x0f) << 28;
809 ctx->last_branch_reason = (packet & 0x70) >> 4;
810 shift += 4;
811 } else
812 ctx->last_branch_reason = 0;
813
814 if (shift == 32)
815 ctx->pc_ok = 1;
816
817 /* if a full address was output, we might have branched into Jazelle state */
818 if ((shift == 32) && (packet & 0x80))
819 ctx->core_state = ARM_STATE_JAZELLE;
820 else {
821 /* if we didn't branch into Jazelle state, the current processor state is
822 * encoded in bit 0 of the branch target address */
823 if (ctx->last_branch & 0x1) {
824 ctx->core_state = ARM_STATE_THUMB;
825 ctx->last_branch &= ~0x1;
826 } else {
827 ctx->core_state = ARM_STATE_ARM;
828 ctx->last_branch &= ~0x3;
829 }
830 }
831
832 return 0;
833 }
834
835 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
836 {
837 int j;
838 uint8_t buf[4];
839 int retval;
840
841 for (j = 0; j < size; j++) {
842 retval = etmv1_next_packet(ctx, &buf[j], 0);
843 if (retval != 0)
844 return -1;
845 }
846
847 if (size == 8) {
848 LOG_ERROR("TODO: add support for 64-bit values");
849 return -1;
850 } else if (size == 4)
851 *data = target_buffer_get_u32(ctx->target, buf);
852 else if (size == 2)
853 *data = target_buffer_get_u16(ctx->target, buf);
854 else if (size == 1)
855 *data = buf[0];
856 else
857 return -1;
858
859 return 0;
860 }
861
862 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
863 {
864 int retval;
865 struct arm_instruction instruction;
866
867 /* read the trace data if it wasn't read already */
868 if (ctx->trace_depth == 0)
869 ctx->capture_driver->read_trace(ctx);
870
871 if (ctx->trace_depth == 0) {
872 command_print(cmd_ctx, "Trace is empty.");
873 return ERROR_OK;
874 }
875
876 /* start at the beginning of the captured trace */
877 ctx->pipe_index = 0;
878 ctx->data_index = 0;
879 ctx->data_half = 0;
880
881 /* neither the PC nor the data pointer are valid */
882 ctx->pc_ok = 0;
883 ctx->ptr_ok = 0;
884
885 while (ctx->pipe_index < ctx->trace_depth) {
886 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
887 uint32_t next_pc = ctx->current_pc;
888 uint32_t old_data_index = ctx->data_index;
889 uint32_t old_data_half = ctx->data_half;
890 uint32_t old_index = ctx->pipe_index;
891 uint32_t last_instruction = ctx->last_instruction;
892 uint32_t cycles = 0;
893 int current_pc_ok = ctx->pc_ok;
894
895 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
896 command_print(cmd_ctx, "--- trigger ---");
897
898 /* instructions execute in IE/D or BE/D cycles */
899 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
900 ctx->last_instruction = ctx->pipe_index;
901
902 /* if we don't have a valid pc skip until we reach an indirect branch */
903 if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
904 ctx->pipe_index++;
905 continue;
906 }
907
908 /* any indirect branch could have interrupted instruction flow
909 * - the branch reason code could indicate a trace discontinuity
910 * - a branch to the exception vectors indicates an exception
911 */
912 if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
913 /* backup current data index, to be able to consume the branch address
914 * before examining data address and values
915 */
916 old_data_index = ctx->data_index;
917 old_data_half = ctx->data_half;
918
919 ctx->last_instruction = ctx->pipe_index;
920
921 retval = etmv1_branch_address(ctx);
922 if (retval != 0) {
923 /* negative return value from etmv1_branch_address means we ran out of packets,
924 * quit analysing the trace */
925 if (retval < 0)
926 break;
927
928 /* a positive return values means the current branch was abandoned,
929 * and a new branch was encountered in cycle ctx->pipe_index + retval;
930 */
931 LOG_WARNING(
932 "abandoned branch encountered, correctness of analysis uncertain");
933 ctx->pipe_index += retval;
934 continue;
935 }
936
937 /* skip over APO cycles */
938 ctx->pipe_index += 2;
939
940 switch (ctx->last_branch_reason) {
941 case 0x0: /* normal PC change */
942 next_pc = ctx->last_branch;
943 break;
944 case 0x1: /* tracing enabled */
945 command_print(cmd_ctx,
946 "--- tracing enabled at 0x%8.8" PRIx32 " ---",
947 ctx->last_branch);
948 ctx->current_pc = ctx->last_branch;
949 ctx->pipe_index++;
950 continue;
951 break;
952 case 0x2: /* trace restarted after FIFO overflow */
953 command_print(cmd_ctx,
954 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
955 ctx->last_branch);
956 ctx->current_pc = ctx->last_branch;
957 ctx->pipe_index++;
958 continue;
959 break;
960 case 0x3: /* exit from debug state */
961 command_print(cmd_ctx,
962 "--- exit from debug state at 0x%8.8" PRIx32 " ---",
963 ctx->last_branch);
964 ctx->current_pc = ctx->last_branch;
965 ctx->pipe_index++;
966 continue;
967 break;
968 case 0x4: /* periodic synchronization point */
969 next_pc = ctx->last_branch;
970 /* if we had no valid PC prior to this synchronization point,
971 * we have to move on with the next trace cycle
972 */
973 if (!current_pc_ok) {
974 command_print(cmd_ctx,
975 "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
976 next_pc);
977 ctx->current_pc = next_pc;
978 ctx->pipe_index++;
979 continue;
980 }
981 break;
982 default: /* reserved */
983 LOG_ERROR(
984 "BUG: branch reason code 0x%" PRIx32 " is reserved",
985 ctx->last_branch_reason);
986 return ERROR_FAIL;
987 }
988
989 /* if we got here the branch was a normal PC change
990 * (or a periodic synchronization point, which means the same for that matter)
991 * if we didn't acquire a complete PC continue with the next cycle
992 */
993 if (!ctx->pc_ok)
994 continue;
995
996 /* indirect branch to the exception vector means an exception occurred */
997 if ((ctx->last_branch <= 0x20)
998 || ((ctx->last_branch >= 0xffff0000) &&
999 (ctx->last_branch <= 0xffff0020))) {
1000 if ((ctx->last_branch & 0xff) == 0x10)
1001 command_print(cmd_ctx, "data abort");
1002 else {
1003 command_print(cmd_ctx,
1004 "exception vector 0x%2.2" PRIx32 "",
1005 ctx->last_branch);
1006 ctx->current_pc = ctx->last_branch;
1007 ctx->pipe_index++;
1008 continue;
1009 }
1010 }
1011 }
1012
1013 /* an instruction was executed (or not, depending on the condition flags)
1014 * retrieve it from the image for displaying */
1015 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1016 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1017 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) {
1018 retval = etm_read_instruction(ctx, &instruction);
1019 if (retval != ERROR_OK) {
1020 /* can't continue tracing with no image available */
1021 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1022 return retval;
1023 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) {
1024 /* TODO: handle incomplete images
1025 * for now we just quit the analysis*/
1026 return retval;
1027 }
1028 }
1029
1030 cycles = old_index - last_instruction;
1031 }
1032
1033 if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) {
1034 uint32_t new_data_index = ctx->data_index;
1035 uint32_t new_data_half = ctx->data_half;
1036
1037 /* in case of a branch with data, the branch target address was consumed before
1038 * we temporarily go back to the saved data index */
1039 if (pipestat == STAT_BD) {
1040 ctx->data_index = old_data_index;
1041 ctx->data_half = old_data_half;
1042 }
1043
1044 if (ctx->control & ETM_CTRL_TRACE_ADDR) {
1045 uint8_t packet;
1046 int shift = 0;
1047
1048 do {
1049 retval = etmv1_next_packet(ctx, &packet, 0);
1050 if (retval != 0)
1051 return ERROR_ETM_ANALYSIS_FAILED;
1052 ctx->last_ptr &= ~(0x7f << shift);
1053 ctx->last_ptr |= (packet & 0x7f) << shift;
1054 shift += 7;
1055 } while ((packet & 0x80) && (shift < 32));
1056
1057 if (shift >= 32)
1058 ctx->ptr_ok = 1;
1059
1060 if (ctx->ptr_ok)
1061 command_print(cmd_ctx,
1062 "address: 0x%8.8" PRIx32 "",
1063 ctx->last_ptr);
1064 }
1065
1066 if (ctx->control & ETM_CTRL_TRACE_DATA) {
1067 if ((instruction.type == ARM_LDM) ||
1068 (instruction.type == ARM_STM)) {
1069 int i;
1070 for (i = 0; i < 16; i++) {
1071 if (instruction.info.load_store_multiple.
1072 register_list & (1 << i)) {
1073 uint32_t data;
1074 if (etmv1_data(ctx, 4, &data) != 0)
1075 return ERROR_ETM_ANALYSIS_FAILED;
1076 command_print(cmd_ctx,
1077 "data: 0x%8.8" PRIx32 "",
1078 data);
1079 }
1080 }
1081 } else if ((instruction.type >= ARM_LDR) &&
1082 (instruction.type <= ARM_STRH)) {
1083 uint32_t data;
1084 if (etmv1_data(ctx, arm_access_size(&instruction),
1085 &data) != 0)
1086 return ERROR_ETM_ANALYSIS_FAILED;
1087 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1088 }
1089 }
1090
1091 /* restore data index after consuming BD address and data */
1092 if (pipestat == STAT_BD) {
1093 ctx->data_index = new_data_index;
1094 ctx->data_half = new_data_half;
1095 }
1096 }
1097
1098 /* adjust PC */
1099 if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) {
1100 if (((instruction.type == ARM_B) ||
1101 (instruction.type == ARM_BL) ||
1102 (instruction.type == ARM_BLX)) &&
1103 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1104 next_pc = instruction.info.b_bl_bx_blx.target_address;
1105 else
1106 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1107 } else if (pipestat == STAT_IN)
1108 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1109
1110 if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) {
1111 char cycles_text[32] = "";
1112
1113 /* if the trace was captured with cycle accurate tracing enabled,
1114 * output the number of cycles since the last executed instruction
1115 */
1116 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) {
1117 snprintf(cycles_text, 32, " (%i %s)",
1118 (int)cycles,
1119 (cycles == 1) ? "cycle" : "cycles");
1120 }
1121
1122 command_print(cmd_ctx, "%s%s%s",
1123 instruction.text,
1124 (pipestat == STAT_IN) ? " (not executed)" : "",
1125 cycles_text);
1126
1127 ctx->current_pc = next_pc;
1128
1129 /* packets for an instruction don't start on or before the preceding
1130 * functional pipestat (i.e. other than WT or TD)
1131 */
1132 if (ctx->data_index <= ctx->pipe_index) {
1133 ctx->data_index = ctx->pipe_index + 1;
1134 ctx->data_half = 0;
1135 }
1136 }
1137
1138 ctx->pipe_index += 1;
1139 }
1140
1141 return ERROR_OK;
1142 }
1143
1144 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1145 uint32_t *mode)
1146 {
1147 uint32_t tracemode;
1148
1149 /* what parts of data access are traced? */
1150 if (strcmp(CMD_ARGV[0], "none") == 0)
1151 tracemode = 0;
1152 else if (strcmp(CMD_ARGV[0], "data") == 0)
1153 tracemode = ETM_CTRL_TRACE_DATA;
1154 else if (strcmp(CMD_ARGV[0], "address") == 0)
1155 tracemode = ETM_CTRL_TRACE_ADDR;
1156 else if (strcmp(CMD_ARGV[0], "all") == 0)
1157 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1158 else {
1159 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1160 return ERROR_COMMAND_SYNTAX_ERROR;
1161 }
1162
1163 uint8_t context_id;
1164 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1165 switch (context_id) {
1166 case 0:
1167 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1168 break;
1169 case 8:
1170 tracemode |= ETM_CTRL_CONTEXTID_8;
1171 break;
1172 case 16:
1173 tracemode |= ETM_CTRL_CONTEXTID_16;
1174 break;
1175 case 32:
1176 tracemode |= ETM_CTRL_CONTEXTID_32;
1177 break;
1178 default:
1179 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1180 return ERROR_COMMAND_SYNTAX_ERROR;
1181 }
1182
1183 bool etmv1_cycle_accurate;
1184 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1185 if (etmv1_cycle_accurate)
1186 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1187
1188 bool etmv1_branch_output;
1189 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1190 if (etmv1_branch_output)
1191 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1192
1193 /* IGNORED:
1194 * - CPRT tracing (coprocessor register transfers)
1195 * - debug request (causes debug entry on trigger)
1196 * - stall on FIFOFULL (preventing tracedata loss)
1197 */
1198 *mode = tracemode;
1199
1200 return ERROR_OK;
1201 }
1202
1203 COMMAND_HANDLER(handle_etm_tracemode_command)
1204 {
1205 struct target *target = get_current_target(CMD_CTX);
1206 struct arm *arm = target_to_arm(target);
1207 struct etm_context *etm;
1208
1209 if (!is_arm(arm)) {
1210 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1211 return ERROR_FAIL;
1212 }
1213
1214 etm = arm->etm;
1215 if (!etm) {
1216 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1217 return ERROR_FAIL;
1218 }
1219
1220 uint32_t tracemode = etm->control;
1221
1222 switch (CMD_ARGC) {
1223 case 0:
1224 break;
1225 case 4:
1226 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1227 &tracemode);
1228 break;
1229 default:
1230 return ERROR_COMMAND_SYNTAX_ERROR;
1231 }
1232
1233 /**
1234 * todo: fail if parameters were invalid for this hardware,
1235 * or couldn't be written; display actual hardware state...
1236 */
1237
1238 command_print(CMD_CTX, "current tracemode configuration:");
1239
1240 switch (tracemode & ETM_CTRL_TRACE_MASK) {
1241 default:
1242 command_print(CMD_CTX, "data tracing: none");
1243 break;
1244 case ETM_CTRL_TRACE_DATA:
1245 command_print(CMD_CTX, "data tracing: data only");
1246 break;
1247 case ETM_CTRL_TRACE_ADDR:
1248 command_print(CMD_CTX, "data tracing: address only");
1249 break;
1250 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1251 command_print(CMD_CTX, "data tracing: address and data");
1252 break;
1253 }
1254
1255 switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
1256 case ETM_CTRL_CONTEXTID_NONE:
1257 command_print(CMD_CTX, "contextid tracing: none");
1258 break;
1259 case ETM_CTRL_CONTEXTID_8:
1260 command_print(CMD_CTX, "contextid tracing: 8 bit");
1261 break;
1262 case ETM_CTRL_CONTEXTID_16:
1263 command_print(CMD_CTX, "contextid tracing: 16 bit");
1264 break;
1265 case ETM_CTRL_CONTEXTID_32:
1266 command_print(CMD_CTX, "contextid tracing: 32 bit");
1267 break;
1268 }
1269
1270 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1271 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1272 else
1273 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1274
1275 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1276 command_print(CMD_CTX, "full branch address output enabled");
1277 else
1278 command_print(CMD_CTX, "full branch address output disabled");
1279
1280 #define TRACEMODE_MASK ( \
1281 ETM_CTRL_CONTEXTID_MASK \
1282 | ETM_CTRL_BRANCH_OUTPUT \
1283 | ETM_CTRL_CYCLE_ACCURATE \
1284 | ETM_CTRL_TRACE_MASK \
1285 )
1286
1287 /* only update ETM_CTRL register if tracemode changed */
1288 if ((etm->control & TRACEMODE_MASK) != tracemode) {
1289 struct reg *etm_ctrl_reg;
1290
1291 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1292 if (!etm_ctrl_reg)
1293 return ERROR_FAIL;
1294
1295 etm->control &= ~TRACEMODE_MASK;
1296 etm->control |= tracemode & TRACEMODE_MASK;
1297
1298 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1299 etm_store_reg(etm_ctrl_reg);
1300
1301 /* invalidate old trace data */
1302 etm->capture_status = TRACE_IDLE;
1303 if (etm->trace_depth > 0) {
1304 free(etm->trace_data);
1305 etm->trace_data = NULL;
1306 }
1307 etm->trace_depth = 0;
1308 }
1309
1310 #undef TRACEMODE_MASK
1311
1312 return ERROR_OK;
1313 }
1314
1315 COMMAND_HANDLER(handle_etm_config_command)
1316 {
1317 struct target *target;
1318 struct arm *arm;
1319 uint32_t portmode = 0x0;
1320 struct etm_context *etm_ctx;
1321 int i;
1322
1323 if (CMD_ARGC != 5)
1324 return ERROR_COMMAND_SYNTAX_ERROR;
1325
1326 target = get_target(CMD_ARGV[0]);
1327 if (!target) {
1328 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1329 return ERROR_FAIL;
1330 }
1331
1332 arm = target_to_arm(target);
1333 if (!is_arm(arm)) {
1334 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1335 target_name(target),
1336 target_type_name(target));
1337 return ERROR_FAIL;
1338 }
1339
1340 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1341 * version we'll be using!! -- so we can't know how to validate
1342 * params yet. "etm config" should likely be *AFTER* hookup...
1343 *
1344 * - Many more widths might be supported ... and we can easily
1345 * check whether our setting "took".
1346 *
1347 * - The "clock" and "mode" bits are interpreted differently.
1348 * See ARM IHI 0014O table 2-17 for the old behaviour, and
1349 * table 2-18 for the new. With ETB it's best to specify
1350 * "normal full" ...
1351 */
1352 uint8_t port_width;
1353 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1354 switch (port_width) {
1355 /* before ETMv3.0 */
1356 case 4:
1357 portmode |= ETM_PORT_4BIT;
1358 break;
1359 case 8:
1360 portmode |= ETM_PORT_8BIT;
1361 break;
1362 case 16:
1363 portmode |= ETM_PORT_16BIT;
1364 break;
1365 /* ETMv3.0 and later*/
1366 case 24:
1367 portmode |= ETM_PORT_24BIT;
1368 break;
1369 case 32:
1370 portmode |= ETM_PORT_32BIT;
1371 break;
1372 case 48:
1373 portmode |= ETM_PORT_48BIT;
1374 break;
1375 case 64:
1376 portmode |= ETM_PORT_64BIT;
1377 break;
1378 case 1:
1379 portmode |= ETM_PORT_1BIT;
1380 break;
1381 case 2:
1382 portmode |= ETM_PORT_2BIT;
1383 break;
1384 default:
1385 command_print(CMD_CTX,
1386 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1387 return ERROR_FAIL;
1388 }
1389
1390 if (strcmp("normal", CMD_ARGV[2]) == 0)
1391 portmode |= ETM_PORT_NORMAL;
1392 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1393 portmode |= ETM_PORT_MUXED;
1394 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1395 portmode |= ETM_PORT_DEMUXED;
1396 else {
1397 command_print(CMD_CTX,
1398 "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1399 CMD_ARGV[2]);
1400 return ERROR_FAIL;
1401 }
1402
1403 if (strcmp("half", CMD_ARGV[3]) == 0)
1404 portmode |= ETM_PORT_HALF_CLOCK;
1405 else if (strcmp("full", CMD_ARGV[3]) == 0)
1406 portmode |= ETM_PORT_FULL_CLOCK;
1407 else {
1408 command_print(CMD_CTX,
1409 "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1410 CMD_ARGV[3]);
1411 return ERROR_FAIL;
1412 }
1413
1414 etm_ctx = calloc(1, sizeof(struct etm_context));
1415 if (!etm_ctx) {
1416 LOG_DEBUG("out of memory");
1417 return ERROR_FAIL;
1418 }
1419
1420 for (i = 0; etm_capture_drivers[i]; i++) {
1421 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
1422 int retval = register_commands(CMD_CTX, NULL,
1423 etm_capture_drivers[i]->commands);
1424 if (ERROR_OK != retval) {
1425 free(etm_ctx);
1426 return retval;
1427 }
1428
1429 etm_ctx->capture_driver = etm_capture_drivers[i];
1430
1431 break;
1432 }
1433 }
1434
1435 if (!etm_capture_drivers[i]) {
1436 /* no supported capture driver found, don't register an ETM */
1437 free(etm_ctx);
1438 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1439 return ERROR_FAIL;
1440 }
1441
1442 etm_ctx->target = target;
1443 etm_ctx->trace_data = NULL;
1444 etm_ctx->control = portmode;
1445 etm_ctx->core_state = ARM_STATE_ARM;
1446
1447 arm->etm = etm_ctx;
1448
1449 return etm_register_user_commands(CMD_CTX);
1450 }
1451
1452 COMMAND_HANDLER(handle_etm_info_command)
1453 {
1454 struct target *target;
1455 struct arm *arm;
1456 struct etm_context *etm;
1457 struct reg *etm_sys_config_reg;
1458 int max_port_size;
1459 uint32_t config;
1460
1461 target = get_current_target(CMD_CTX);
1462 arm = target_to_arm(target);
1463 if (!is_arm(arm)) {
1464 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1465 return ERROR_FAIL;
1466 }
1467
1468 etm = arm->etm;
1469 if (!etm) {
1470 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1471 return ERROR_FAIL;
1472 }
1473
1474 command_print(CMD_CTX, "ETM v%d.%d",
1475 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1476 command_print(CMD_CTX, "pairs of address comparators: %i",
1477 (int) (etm->config >> 0) & 0x0f);
1478 command_print(CMD_CTX, "data comparators: %i",
1479 (int) (etm->config >> 4) & 0x0f);
1480 command_print(CMD_CTX, "memory map decoders: %i",
1481 (int) (etm->config >> 8) & 0x1f);
1482 command_print(CMD_CTX, "number of counters: %i",
1483 (int) (etm->config >> 13) & 0x07);
1484 command_print(CMD_CTX, "sequencer %spresent",
1485 (int) (etm->config & (1 << 16)) ? "" : "not ");
1486 command_print(CMD_CTX, "number of ext. inputs: %i",
1487 (int) (etm->config >> 17) & 0x07);
1488 command_print(CMD_CTX, "number of ext. outputs: %i",
1489 (int) (etm->config >> 20) & 0x07);
1490 command_print(CMD_CTX, "FIFO full %spresent",
1491 (int) (etm->config & (1 << 23)) ? "" : "not ");
1492 if (etm->bcd_vers < 0x20)
1493 command_print(CMD_CTX, "protocol version: %i",
1494 (int) (etm->config >> 28) & 0x07);
1495 else {
1496 command_print(CMD_CTX,
1497 "coprocessor and memory access %ssupported",
1498 (etm->config & (1 << 26)) ? "" : "not ");
1499 command_print(CMD_CTX, "trace start/stop %spresent",
1500 (etm->config & (1 << 26)) ? "" : "not ");
1501 command_print(CMD_CTX, "number of context comparators: %i",
1502 (int) (etm->config >> 24) & 0x03);
1503 }
1504
1505 /* SYS_CONFIG isn't present before ETMv1.2 */
1506 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1507 if (!etm_sys_config_reg)
1508 return ERROR_OK;
1509
1510 etm_get_reg(etm_sys_config_reg);
1511 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1512
1513 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1514
1515 max_port_size = config & 0x7;
1516 if (etm->bcd_vers >= 0x30)
1517 max_port_size |= (config >> 6) & 0x08;
1518 switch (max_port_size) {
1519 /* before ETMv3.0 */
1520 case 0:
1521 max_port_size = 4;
1522 break;
1523 case 1:
1524 max_port_size = 8;
1525 break;
1526 case 2:
1527 max_port_size = 16;
1528 break;
1529 /* ETMv3.0 and later*/
1530 case 3:
1531 max_port_size = 24;
1532 break;
1533 case 4:
1534 max_port_size = 32;
1535 break;
1536 case 5:
1537 max_port_size = 48;
1538 break;
1539 case 6:
1540 max_port_size = 64;
1541 break;
1542 case 8:
1543 max_port_size = 1;
1544 break;
1545 case 9:
1546 max_port_size = 2;
1547 break;
1548 default:
1549 LOG_ERROR("Illegal max_port_size");
1550 return ERROR_FAIL;
1551 }
1552 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1553
1554 if (etm->bcd_vers < 0x30) {
1555 command_print(CMD_CTX, "half-rate clocking %ssupported",
1556 (config & (1 << 3)) ? "" : "not ");
1557 command_print(CMD_CTX, "full-rate clocking %ssupported",
1558 (config & (1 << 4)) ? "" : "not ");
1559 command_print(CMD_CTX, "normal trace format %ssupported",
1560 (config & (1 << 5)) ? "" : "not ");
1561 command_print(CMD_CTX, "multiplex trace format %ssupported",
1562 (config & (1 << 6)) ? "" : "not ");
1563 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1564 (config & (1 << 7)) ? "" : "not ");
1565 } else {
1566 /* REVISIT show which size and format are selected ... */
1567 command_print(CMD_CTX, "current port size %ssupported",
1568 (config & (1 << 10)) ? "" : "not ");
1569 command_print(CMD_CTX, "current trace format %ssupported",
1570 (config & (1 << 11)) ? "" : "not ");
1571 }
1572 if (etm->bcd_vers >= 0x21)
1573 command_print(CMD_CTX, "fetch comparisons %ssupported",
1574 (config & (1 << 17)) ? "not " : "");
1575 command_print(CMD_CTX, "FIFO full %ssupported",
1576 (config & (1 << 8)) ? "" : "not ");
1577
1578 return ERROR_OK;
1579 }
1580
1581 COMMAND_HANDLER(handle_etm_status_command)
1582 {
1583 struct target *target;
1584 struct arm *arm;
1585 struct etm_context *etm;
1586 trace_status_t trace_status;
1587
1588 target = get_current_target(CMD_CTX);
1589 arm = target_to_arm(target);
1590 if (!is_arm(arm)) {
1591 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1592 return ERROR_FAIL;
1593 }
1594
1595 etm = arm->etm;
1596 if (!etm) {
1597 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1598 return ERROR_FAIL;
1599 }
1600
1601 /* ETM status */
1602 if (etm->bcd_vers >= 0x11) {
1603 struct reg *reg;
1604
1605 reg = etm_reg_lookup(etm, ETM_STATUS);
1606 if (!reg)
1607 return ERROR_FAIL;
1608 if (etm_get_reg(reg) == ERROR_OK) {
1609 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1610
1611 command_print(CMD_CTX, "etm: %s%s%s%s",
1612 /* bit(1) == progbit */
1613 (etm->bcd_vers >= 0x12)
1614 ? ((s & (1 << 1))
1615 ? "disabled" : "enabled")
1616 : "?",
1617 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1618 ? " triggered" : "",
1619 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1620 ? " start/stop" : "",
1621 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1622 ? " untraced-overflow" : "");
1623 } /* else ignore and try showing trace port status */
1624 }
1625
1626 /* Trace Port Driver status */
1627 trace_status = etm->capture_driver->status(etm);
1628 if (trace_status == TRACE_IDLE)
1629 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1630 else {
1631 static char *completed = " completed";
1632 static char *running = " is running";
1633 static char *overflowed = ", overflowed";
1634 static char *triggered = ", triggered";
1635
1636 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1637 etm->capture_driver->name,
1638 (trace_status & TRACE_RUNNING) ? running : completed,
1639 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1640 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1641
1642 if (etm->trace_depth > 0) {
1643 command_print(CMD_CTX, "%i frames of trace data read",
1644 (int)(etm->trace_depth));
1645 }
1646 }
1647
1648 return ERROR_OK;
1649 }
1650
1651 COMMAND_HANDLER(handle_etm_image_command)
1652 {
1653 struct target *target;
1654 struct arm *arm;
1655 struct etm_context *etm_ctx;
1656
1657 if (CMD_ARGC < 1)
1658 return ERROR_COMMAND_SYNTAX_ERROR;
1659
1660 target = get_current_target(CMD_CTX);
1661 arm = target_to_arm(target);
1662 if (!is_arm(arm)) {
1663 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1664 return ERROR_FAIL;
1665 }
1666
1667 etm_ctx = arm->etm;
1668 if (!etm_ctx) {
1669 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1670 return ERROR_FAIL;
1671 }
1672
1673 if (etm_ctx->image) {
1674 image_close(etm_ctx->image);
1675 free(etm_ctx->image);
1676 command_print(CMD_CTX, "previously loaded image found and closed");
1677 }
1678
1679 etm_ctx->image = malloc(sizeof(struct image));
1680 etm_ctx->image->base_address_set = 0;
1681 etm_ctx->image->start_address_set = 0;
1682
1683 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1684 if (CMD_ARGC >= 2) {
1685 etm_ctx->image->base_address_set = 1;
1686 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1687 } else
1688 etm_ctx->image->base_address_set = 0;
1689
1690 if (image_open(etm_ctx->image, CMD_ARGV[0],
1691 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
1692 free(etm_ctx->image);
1693 etm_ctx->image = NULL;
1694 return ERROR_FAIL;
1695 }
1696
1697 return ERROR_OK;
1698 }
1699
1700 COMMAND_HANDLER(handle_etm_dump_command)
1701 {
1702 struct fileio *file;
1703 struct target *target;
1704 struct arm *arm;
1705 struct etm_context *etm_ctx;
1706 uint32_t i;
1707
1708 if (CMD_ARGC != 1)
1709 return ERROR_COMMAND_SYNTAX_ERROR;
1710
1711 target = get_current_target(CMD_CTX);
1712 arm = target_to_arm(target);
1713 if (!is_arm(arm)) {
1714 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1715 return ERROR_FAIL;
1716 }
1717
1718 etm_ctx = arm->etm;
1719 if (!etm_ctx) {
1720 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1721 return ERROR_FAIL;
1722 }
1723
1724 if (etm_ctx->capture_driver->status == TRACE_IDLE) {
1725 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1726 return ERROR_OK;
1727 }
1728
1729 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1730 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1731 command_print(CMD_CTX, "trace capture not completed");
1732 return ERROR_FAIL;
1733 }
1734
1735 /* read the trace data if it wasn't read already */
1736 if (etm_ctx->trace_depth == 0)
1737 etm_ctx->capture_driver->read_trace(etm_ctx);
1738
1739 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1740 return ERROR_FAIL;
1741
1742 fileio_write_u32(file, etm_ctx->capture_status);
1743 fileio_write_u32(file, etm_ctx->control);
1744 fileio_write_u32(file, etm_ctx->trace_depth);
1745
1746 for (i = 0; i < etm_ctx->trace_depth; i++) {
1747 fileio_write_u32(file, etm_ctx->trace_data[i].pipestat);
1748 fileio_write_u32(file, etm_ctx->trace_data[i].packet);
1749 fileio_write_u32(file, etm_ctx->trace_data[i].flags);
1750 }
1751
1752 fileio_close(file);
1753
1754 return ERROR_OK;
1755 }
1756
1757 COMMAND_HANDLER(handle_etm_load_command)
1758 {
1759 struct fileio *file;
1760 struct target *target;
1761 struct arm *arm;
1762 struct etm_context *etm_ctx;
1763 uint32_t i;
1764
1765 if (CMD_ARGC != 1)
1766 return ERROR_COMMAND_SYNTAX_ERROR;
1767
1768 target = get_current_target(CMD_CTX);
1769 arm = target_to_arm(target);
1770 if (!is_arm(arm)) {
1771 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1772 return ERROR_FAIL;
1773 }
1774
1775 etm_ctx = arm->etm;
1776 if (!etm_ctx) {
1777 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1778 return ERROR_FAIL;
1779 }
1780
1781 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1782 command_print(CMD_CTX, "trace capture running, stop first");
1783 return ERROR_FAIL;
1784 }
1785
1786 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1787 return ERROR_FAIL;
1788
1789 size_t filesize;
1790 int retval = fileio_size(file, &filesize);
1791 if (retval != ERROR_OK) {
1792 fileio_close(file);
1793 return retval;
1794 }
1795
1796 if (filesize % 4) {
1797 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1798 fileio_close(file);
1799 return ERROR_FAIL;
1800 }
1801
1802 if (etm_ctx->trace_depth > 0) {
1803 free(etm_ctx->trace_data);
1804 etm_ctx->trace_data = NULL;
1805 }
1806
1807 {
1808 uint32_t tmp;
1809 fileio_read_u32(file, &tmp); etm_ctx->capture_status = tmp;
1810 fileio_read_u32(file, &tmp); etm_ctx->control = tmp;
1811 fileio_read_u32(file, &etm_ctx->trace_depth);
1812 }
1813 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1814 if (etm_ctx->trace_data == NULL) {
1815 command_print(CMD_CTX, "not enough memory to perform operation");
1816 fileio_close(file);
1817 return ERROR_FAIL;
1818 }
1819
1820 for (i = 0; i < etm_ctx->trace_depth; i++) {
1821 uint32_t pipestat, packet, flags;
1822 fileio_read_u32(file, &pipestat);
1823 fileio_read_u32(file, &packet);
1824 fileio_read_u32(file, &flags);
1825 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1826 etm_ctx->trace_data[i].packet = packet & 0xffff;
1827 etm_ctx->trace_data[i].flags = flags;
1828 }
1829
1830 fileio_close(file);
1831
1832 return ERROR_OK;
1833 }
1834
1835 COMMAND_HANDLER(handle_etm_start_command)
1836 {
1837 struct target *target;
1838 struct arm *arm;
1839 struct etm_context *etm_ctx;
1840 struct reg *etm_ctrl_reg;
1841
1842 target = get_current_target(CMD_CTX);
1843 arm = target_to_arm(target);
1844 if (!is_arm(arm)) {
1845 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1846 return ERROR_FAIL;
1847 }
1848
1849 etm_ctx = arm->etm;
1850 if (!etm_ctx) {
1851 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1852 return ERROR_FAIL;
1853 }
1854
1855 /* invalidate old tracing data */
1856 etm_ctx->capture_status = TRACE_IDLE;
1857 if (etm_ctx->trace_depth > 0) {
1858 free(etm_ctx->trace_data);
1859 etm_ctx->trace_data = NULL;
1860 }
1861 etm_ctx->trace_depth = 0;
1862
1863 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1864 if (!etm_ctrl_reg)
1865 return ERROR_FAIL;
1866
1867 etm_get_reg(etm_ctrl_reg);
1868
1869 /* Clear programming bit (10), set port selection bit (11) */
1870 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1871
1872 etm_store_reg(etm_ctrl_reg);
1873 jtag_execute_queue();
1874
1875 etm_ctx->capture_driver->start_capture(etm_ctx);
1876
1877 return ERROR_OK;
1878 }
1879
1880 COMMAND_HANDLER(handle_etm_stop_command)
1881 {
1882 struct target *target;
1883 struct arm *arm;
1884 struct etm_context *etm_ctx;
1885 struct reg *etm_ctrl_reg;
1886
1887 target = get_current_target(CMD_CTX);
1888 arm = target_to_arm(target);
1889 if (!is_arm(arm)) {
1890 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1891 return ERROR_FAIL;
1892 }
1893
1894 etm_ctx = arm->etm;
1895 if (!etm_ctx) {
1896 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1897 return ERROR_FAIL;
1898 }
1899
1900 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1901 if (!etm_ctrl_reg)
1902 return ERROR_FAIL;
1903
1904 etm_get_reg(etm_ctrl_reg);
1905
1906 /* Set programming bit (10), clear port selection bit (11) */
1907 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1908
1909 etm_store_reg(etm_ctrl_reg);
1910 jtag_execute_queue();
1911
1912 etm_ctx->capture_driver->stop_capture(etm_ctx);
1913
1914 return ERROR_OK;
1915 }
1916
1917 COMMAND_HANDLER(handle_etm_trigger_debug_command)
1918 {
1919 struct target *target;
1920 struct arm *arm;
1921 struct etm_context *etm;
1922
1923 target = get_current_target(CMD_CTX);
1924 arm = target_to_arm(target);
1925 if (!is_arm(arm)) {
1926 command_print(CMD_CTX, "ETM: %s isn't an ARM",
1927 target_name(target));
1928 return ERROR_FAIL;
1929 }
1930
1931 etm = arm->etm;
1932 if (!etm) {
1933 command_print(CMD_CTX, "ETM: no ETM configured for %s",
1934 target_name(target));
1935 return ERROR_FAIL;
1936 }
1937
1938 if (CMD_ARGC == 1) {
1939 struct reg *etm_ctrl_reg;
1940 bool dbgrq;
1941
1942 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1943 if (!etm_ctrl_reg)
1944 return ERROR_FAIL;
1945
1946 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
1947 if (dbgrq)
1948 etm->control |= ETM_CTRL_DBGRQ;
1949 else
1950 etm->control &= ~ETM_CTRL_DBGRQ;
1951
1952 /* etm->control will be written to hardware
1953 * the next time an "etm start" is issued.
1954 */
1955 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1956 }
1957
1958 command_print(CMD_CTX, "ETM: %s debug halt",
1959 (etm->control & ETM_CTRL_DBGRQ)
1960 ? "triggers"
1961 : "does not trigger");
1962 return ERROR_OK;
1963 }
1964
1965 COMMAND_HANDLER(handle_etm_analyze_command)
1966 {
1967 struct target *target;
1968 struct arm *arm;
1969 struct etm_context *etm_ctx;
1970 int retval;
1971
1972 target = get_current_target(CMD_CTX);
1973 arm = target_to_arm(target);
1974 if (!is_arm(arm)) {
1975 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1976 return ERROR_FAIL;
1977 }
1978
1979 etm_ctx = arm->etm;
1980 if (!etm_ctx) {
1981 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1982 return ERROR_FAIL;
1983 }
1984
1985 retval = etmv1_analyze_trace(etm_ctx, CMD_CTX);
1986 if (retval != ERROR_OK) {
1987 /* FIX! error should be reported inside etmv1_analyze_trace() */
1988 switch (retval) {
1989 case ERROR_ETM_ANALYSIS_FAILED:
1990 command_print(CMD_CTX,
1991 "further analysis failed (corrupted trace data or just end of data");
1992 break;
1993 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1994 command_print(CMD_CTX,
1995 "no instruction for current address available, analysis aborted");
1996 break;
1997 case ERROR_TRACE_IMAGE_UNAVAILABLE:
1998 command_print(CMD_CTX, "no image available for trace analysis");
1999 break;
2000 default:
2001 command_print(CMD_CTX, "unknown error");
2002 }
2003 }
2004
2005 return retval;
2006 }
2007
2008 static const struct command_registration etm_config_command_handlers[] = {
2009 {
2010 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2011 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2012 *
2013 * Also, these parameters don't match ETM v3+ modules...
2014 */
2015 .name = "config",
2016 .handler = handle_etm_config_command,
2017 .mode = COMMAND_CONFIG,
2018 .help = "Set up ETM output port.",
2019 .usage = "target port_width port_mode clocking capture_driver",
2020 },
2021 COMMAND_REGISTRATION_DONE
2022 };
2023 const struct command_registration etm_command_handlers[] = {
2024 {
2025 .name = "etm",
2026 .mode = COMMAND_ANY,
2027 .help = "Embedded Trace Macrocell command group",
2028 .usage = "",
2029 .chain = etm_config_command_handlers,
2030 },
2031 COMMAND_REGISTRATION_DONE
2032 };
2033
2034 static const struct command_registration etm_exec_command_handlers[] = {
2035 {
2036 .name = "tracemode",
2037 .handler = handle_etm_tracemode_command,
2038 .mode = COMMAND_EXEC,
2039 .help = "configure/display trace mode",
2040 .usage = "('none'|'data'|'address'|'all') "
2041 "context_id_bits "
2042 "['enable'|'disable'] "
2043 "['enable'|'disable']",
2044 },
2045 {
2046 .name = "info",
2047 .handler = handle_etm_info_command,
2048 .mode = COMMAND_EXEC,
2049 .usage = "",
2050 .help = "display info about the current target's ETM",
2051 },
2052 {
2053 .name = "status",
2054 .handler = handle_etm_status_command,
2055 .mode = COMMAND_EXEC,
2056 .usage = "",
2057 .help = "display current target's ETM status",
2058 },
2059 {
2060 .name = "start",
2061 .handler = handle_etm_start_command,
2062 .mode = COMMAND_EXEC,
2063 .usage = "",
2064 .help = "start ETM trace collection",
2065 },
2066 {
2067 .name = "stop",
2068 .handler = handle_etm_stop_command,
2069 .mode = COMMAND_EXEC,
2070 .usage = "",
2071 .help = "stop ETM trace collection",
2072 },
2073 {
2074 .name = "trigger_debug",
2075 .handler = handle_etm_trigger_debug_command,
2076 .mode = COMMAND_EXEC,
2077 .help = "enable/disable debug entry on trigger",
2078 .usage = "['enable'|'disable']",
2079 },
2080 {
2081 .name = "analyze",
2082 .handler = handle_etm_analyze_command,
2083 .mode = COMMAND_EXEC,
2084 .usage = "",
2085 .help = "analyze collected ETM trace",
2086 },
2087 {
2088 .name = "image",
2089 .handler = handle_etm_image_command,
2090 .mode = COMMAND_EXEC,
2091 .help = "load image from file with optional offset",
2092 .usage = "<file> [base address] [type]",
2093 },
2094 {
2095 .name = "dump",
2096 .handler = handle_etm_dump_command,
2097 .mode = COMMAND_EXEC,
2098 .help = "dump captured trace data to file",
2099 .usage = "filename",
2100 },
2101 {
2102 .name = "load",
2103 .handler = handle_etm_load_command,
2104 .mode = COMMAND_EXEC,
2105 .usage = "",
2106 .help = "load trace data for analysis <file>",
2107 },
2108 COMMAND_REGISTRATION_DONE
2109 };
2110
2111 static int etm_register_user_commands(struct command_context *cmd_ctx)
2112 {
2113 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2114 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2115 }
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