1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
30 #include "arm7_9_common.h"
31 #include "arm_disassembler.h"
32 #include "arm_simulator.h"
37 #include "binarybuffer.h"
45 /* ETM register access functionality
49 bitfield_desc_t etm_comms_ctrl_bitfield_desc
[] =
57 int etm_reg_arch_info
[] =
59 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
60 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
61 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
62 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
63 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
64 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
65 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
66 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
67 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
68 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
69 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
70 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
71 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
72 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
75 int etm_reg_arch_size_info
[] =
77 32, 32, 17, 8, 3, 9, 32, 16,
78 17, 26, 25, 8, 17, 32, 32, 17,
79 32, 32, 32, 32, 32, 32, 32, 32,
80 32, 32, 32, 32, 32, 32, 32, 32,
81 7, 7, 7, 7, 7, 7, 7, 7,
82 7, 7, 7, 7, 7, 7, 7, 7,
83 32, 32, 32, 32, 32, 32, 32, 32,
84 32, 32, 32, 32, 32, 32, 32, 32,
85 32, 32, 32, 32, 32, 32, 32, 32,
86 32, 32, 32, 32, 32, 32, 32, 32,
87 16, 16, 16, 16, 18, 18, 18, 18,
88 17, 17, 17, 17, 16, 16, 16, 16,
89 17, 17, 17, 17, 17, 17, 2,
90 17, 17, 17, 17, 32, 32, 32, 32
93 char* etm_reg_list
[] =
101 "ETM_TRACE_RESOURCE_CTRL",
102 "ETM_TRACE_EN_CTRL2",
103 "ETM_TRACE_EN_EVENT",
104 "ETM_TRACE_EN_CTRL1",
105 "ETM_FIFOFULL_REGION",
106 "ETM_FIFOFULL_LEVEL",
107 "ETM_VIEWDATA_EVENT",
108 "ETM_VIEWDATA_CTRL1",
109 "ETM_VIEWDATA_CTRL2",
110 "ETM_VIEWDATA_CTRL3",
111 "ETM_ADDR_COMPARATOR_VALUE1",
112 "ETM_ADDR_COMPARATOR_VALUE2",
113 "ETM_ADDR_COMPARATOR_VALUE3",
114 "ETM_ADDR_COMPARATOR_VALUE4",
115 "ETM_ADDR_COMPARATOR_VALUE5",
116 "ETM_ADDR_COMPARATOR_VALUE6",
117 "ETM_ADDR_COMPARATOR_VALUE7",
118 "ETM_ADDR_COMPARATOR_VALUE8",
119 "ETM_ADDR_COMPARATOR_VALUE9",
120 "ETM_ADDR_COMPARATOR_VALUE10",
121 "ETM_ADDR_COMPARATOR_VALUE11",
122 "ETM_ADDR_COMPARATOR_VALUE12",
123 "ETM_ADDR_COMPARATOR_VALUE13",
124 "ETM_ADDR_COMPARATOR_VALUE14",
125 "ETM_ADDR_COMPARATOR_VALUE15",
126 "ETM_ADDR_COMPARATOR_VALUE16",
127 "ETM_ADDR_ACCESS_TYPE1",
128 "ETM_ADDR_ACCESS_TYPE2",
129 "ETM_ADDR_ACCESS_TYPE3",
130 "ETM_ADDR_ACCESS_TYPE4",
131 "ETM_ADDR_ACCESS_TYPE5",
132 "ETM_ADDR_ACCESS_TYPE6",
133 "ETM_ADDR_ACCESS_TYPE7",
134 "ETM_ADDR_ACCESS_TYPE8",
135 "ETM_ADDR_ACCESS_TYPE9",
136 "ETM_ADDR_ACCESS_TYPE10",
137 "ETM_ADDR_ACCESS_TYPE11",
138 "ETM_ADDR_ACCESS_TYPE12",
139 "ETM_ADDR_ACCESS_TYPE13",
140 "ETM_ADDR_ACCESS_TYPE14",
141 "ETM_ADDR_ACCESS_TYPE15",
142 "ETM_ADDR_ACCESS_TYPE16",
143 "ETM_DATA_COMPARATOR_VALUE1",
144 "ETM_DATA_COMPARATOR_VALUE2",
145 "ETM_DATA_COMPARATOR_VALUE3",
146 "ETM_DATA_COMPARATOR_VALUE4",
147 "ETM_DATA_COMPARATOR_VALUE5",
148 "ETM_DATA_COMPARATOR_VALUE6",
149 "ETM_DATA_COMPARATOR_VALUE7",
150 "ETM_DATA_COMPARATOR_VALUE8",
151 "ETM_DATA_COMPARATOR_VALUE9",
152 "ETM_DATA_COMPARATOR_VALUE10",
153 "ETM_DATA_COMPARATOR_VALUE11",
154 "ETM_DATA_COMPARATOR_VALUE12",
155 "ETM_DATA_COMPARATOR_VALUE13",
156 "ETM_DATA_COMPARATOR_VALUE14",
157 "ETM_DATA_COMPARATOR_VALUE15",
158 "ETM_DATA_COMPARATOR_VALUE16",
159 "ETM_DATA_COMPARATOR_MASK1",
160 "ETM_DATA_COMPARATOR_MASK2",
161 "ETM_DATA_COMPARATOR_MASK3",
162 "ETM_DATA_COMPARATOR_MASK4",
163 "ETM_DATA_COMPARATOR_MASK5",
164 "ETM_DATA_COMPARATOR_MASK6",
165 "ETM_DATA_COMPARATOR_MASK7",
166 "ETM_DATA_COMPARATOR_MASK8",
167 "ETM_DATA_COMPARATOR_MASK9",
168 "ETM_DATA_COMPARATOR_MASK10",
169 "ETM_DATA_COMPARATOR_MASK11",
170 "ETM_DATA_COMPARATOR_MASK12",
171 "ETM_DATA_COMPARATOR_MASK13",
172 "ETM_DATA_COMPARATOR_MASK14",
173 "ETM_DATA_COMPARATOR_MASK15",
174 "ETM_DATA_COMPARATOR_MASK16",
175 "ETM_COUNTER_INITAL_VALUE1",
176 "ETM_COUNTER_INITAL_VALUE2",
177 "ETM_COUNTER_INITAL_VALUE3",
178 "ETM_COUNTER_INITAL_VALUE4",
179 "ETM_COUNTER_ENABLE1",
180 "ETM_COUNTER_ENABLE2",
181 "ETM_COUNTER_ENABLE3",
182 "ETM_COUNTER_ENABLE4",
183 "ETM_COUNTER_RELOAD_VALUE1",
184 "ETM_COUNTER_RELOAD_VALUE2",
185 "ETM_COUNTER_RELOAD_VALUE3",
186 "ETM_COUNTER_RELOAD_VALUE4",
187 "ETM_COUNTER_VALUE1",
188 "ETM_COUNTER_VALUE2",
189 "ETM_COUNTER_VALUE3",
190 "ETM_COUNTER_VALUE4",
191 "ETM_SEQUENCER_CTRL1",
192 "ETM_SEQUENCER_CTRL2",
193 "ETM_SEQUENCER_CTRL3",
194 "ETM_SEQUENCER_CTRL4",
195 "ETM_SEQUENCER_CTRL5",
196 "ETM_SEQUENCER_CTRL6",
197 "ETM_SEQUENCER_STATE",
198 "ETM_EXTERNAL_OUTPUT1",
199 "ETM_EXTERNAL_OUTPUT2",
200 "ETM_EXTERNAL_OUTPUT3",
201 "ETM_EXTERNAL_OUTPUT4",
202 "ETM_CONTEXTID_COMPARATOR_VALUE1",
203 "ETM_CONTEXTID_COMPARATOR_VALUE2",
204 "ETM_CONTEXTID_COMPARATOR_VALUE3",
205 "ETM_CONTEXTID_COMPARATOR_MASK"
208 int etm_reg_arch_type
= -1;
210 int etm_get_reg(reg_t
*reg
);
211 int etm_set_reg(reg_t
*reg
, u32 value
);
212 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
214 int etm_write_reg(reg_t
*reg
, u32 value
);
215 int etm_read_reg(reg_t
*reg
);
217 command_t
*etm_cmd
= NULL
;
219 reg_cache_t
* etm_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
221 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
222 reg_t
*reg_list
= NULL
;
223 etm_reg_t
*arch_info
= NULL
;
224 int num_regs
= sizeof(etm_reg_arch_info
)/sizeof(int);
228 /* register a register arch-type for etm registers only once */
229 if (etm_reg_arch_type
== -1)
230 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
, etm_set_reg_w_exec
);
232 /* the actual registers are kept in two arrays */
233 reg_list
= calloc(num_regs
, sizeof(reg_t
));
234 arch_info
= calloc(num_regs
, sizeof(etm_reg_t
));
236 /* fill in values for the reg cache */
237 reg_cache
->name
= "etm registers";
238 reg_cache
->next
= NULL
;
239 reg_cache
->reg_list
= reg_list
;
240 reg_cache
->num_regs
= num_regs
;
242 /* set up registers */
243 for (i
= 0; i
< num_regs
; i
++)
245 reg_list
[i
].name
= etm_reg_list
[i
];
246 reg_list
[i
].size
= 32;
247 reg_list
[i
].dirty
= 0;
248 reg_list
[i
].valid
= 0;
249 reg_list
[i
].bitfield_desc
= NULL
;
250 reg_list
[i
].num_bitfields
= 0;
251 reg_list
[i
].value
= calloc(1, 4);
252 reg_list
[i
].arch_info
= &arch_info
[i
];
253 reg_list
[i
].arch_type
= etm_reg_arch_type
;
254 reg_list
[i
].size
= etm_reg_arch_size_info
[i
];
255 arch_info
[i
].addr
= etm_reg_arch_info
[i
];
256 arch_info
[i
].jtag_info
= jtag_info
;
259 /* initialize some ETM control register settings */
260 etm_get_reg(®_list
[ETM_CTRL
]);
261 etm_ctrl_value
= buf_get_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
);
263 /* clear the ETM powerdown bit (0) */
264 etm_ctrl_value
&= ~0x1;
266 /* configure port width (6:4), mode (17:16) and clocking (13) */
267 etm_ctrl_value
= (etm_ctrl_value
&
268 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
271 buf_set_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
, etm_ctrl_value
);
272 etm_store_reg(®_list
[ETM_CTRL
]);
274 /* the ETM might have an ETB connected */
275 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
277 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
281 ERROR("etb selected as etm capture driver, but no ETB configured");
285 reg_cache
->next
= etb_build_reg_cache(etb
);
287 etb
->reg_cache
= reg_cache
->next
;
290 if (etm_ctx
->capture_driver
->init(etm_ctx
) != ERROR_OK
)
292 ERROR("ETM capture driver initialization failed");
299 int etm_get_reg(reg_t
*reg
)
301 if (etm_read_reg(reg
) != ERROR_OK
)
303 ERROR("BUG: error scheduling etm register read");
307 if (jtag_execute_queue() != ERROR_OK
)
309 ERROR("register read failed");
315 int etm_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
317 etm_reg_t
*etm_reg
= reg
->arch_info
;
318 u8 reg_addr
= etm_reg
->addr
& 0x7f;
319 scan_field_t fields
[3];
321 DEBUG("%i", etm_reg
->addr
);
323 jtag_add_end_state(TAP_RTI
);
324 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
325 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
327 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
328 fields
[0].num_bits
= 32;
329 fields
[0].out_value
= reg
->value
;
330 fields
[0].out_mask
= NULL
;
331 fields
[0].in_value
= NULL
;
332 fields
[0].in_check_value
= NULL
;
333 fields
[0].in_check_mask
= NULL
;
334 fields
[0].in_handler
= NULL
;
335 fields
[0].in_handler_priv
= NULL
;
337 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
338 fields
[1].num_bits
= 7;
339 fields
[1].out_value
= malloc(1);
340 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
341 fields
[1].out_mask
= NULL
;
342 fields
[1].in_value
= NULL
;
343 fields
[1].in_check_value
= NULL
;
344 fields
[1].in_check_mask
= NULL
;
345 fields
[1].in_handler
= NULL
;
346 fields
[1].in_handler_priv
= NULL
;
348 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
349 fields
[2].num_bits
= 1;
350 fields
[2].out_value
= malloc(1);
351 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
352 fields
[2].out_mask
= NULL
;
353 fields
[2].in_value
= NULL
;
354 fields
[2].in_check_value
= NULL
;
355 fields
[2].in_check_mask
= NULL
;
356 fields
[2].in_handler
= NULL
;
357 fields
[2].in_handler_priv
= NULL
;
359 jtag_add_dr_scan(3, fields
, -1, NULL
);
361 fields
[0].in_value
= reg
->value
;
362 fields
[0].in_check_value
= check_value
;
363 fields
[0].in_check_mask
= check_mask
;
365 jtag_add_dr_scan(3, fields
, -1, NULL
);
367 free(fields
[1].out_value
);
368 free(fields
[2].out_value
);
373 int etm_read_reg(reg_t
*reg
)
375 return etm_read_reg_w_check(reg
, NULL
, NULL
);
378 int etm_set_reg(reg_t
*reg
, u32 value
)
380 if (etm_write_reg(reg
, value
) != ERROR_OK
)
382 ERROR("BUG: error scheduling etm register write");
386 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
393 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
395 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
397 if (jtag_execute_queue() != ERROR_OK
)
399 ERROR("register write failed");
405 int etm_write_reg(reg_t
*reg
, u32 value
)
407 etm_reg_t
*etm_reg
= reg
->arch_info
;
408 u8 reg_addr
= etm_reg
->addr
& 0x7f;
409 scan_field_t fields
[3];
411 DEBUG("%i: 0x%8.8x", etm_reg
->addr
, value
);
413 jtag_add_end_state(TAP_RTI
);
414 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
415 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
417 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
418 fields
[0].num_bits
= 32;
419 fields
[0].out_value
= malloc(4);
420 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
421 fields
[0].out_mask
= NULL
;
422 fields
[0].in_value
= NULL
;
423 fields
[0].in_check_value
= NULL
;
424 fields
[0].in_check_mask
= NULL
;
425 fields
[0].in_handler
= NULL
;
426 fields
[0].in_handler_priv
= NULL
;
428 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
429 fields
[1].num_bits
= 7;
430 fields
[1].out_value
= malloc(1);
431 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
432 fields
[1].out_mask
= NULL
;
433 fields
[1].in_value
= NULL
;
434 fields
[1].in_check_value
= NULL
;
435 fields
[1].in_check_mask
= NULL
;
436 fields
[1].in_handler
= NULL
;
437 fields
[1].in_handler_priv
= NULL
;
439 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
440 fields
[2].num_bits
= 1;
441 fields
[2].out_value
= malloc(1);
442 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
443 fields
[2].out_mask
= NULL
;
444 fields
[2].in_value
= NULL
;
445 fields
[2].in_check_value
= NULL
;
446 fields
[2].in_check_mask
= NULL
;
447 fields
[2].in_handler
= NULL
;
448 fields
[2].in_handler_priv
= NULL
;
450 jtag_add_dr_scan(3, fields
, -1, NULL
);
452 free(fields
[0].out_value
);
453 free(fields
[1].out_value
);
454 free(fields
[2].out_value
);
459 int etm_store_reg(reg_t
*reg
)
461 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
464 /* ETM trace analysis functionality
467 extern etm_capture_driver_t etb_capture_driver
;
468 extern etm_capture_driver_t etm_dummy_capture_driver
;
469 #if BUILD_OOCD_TRACE == 1
470 extern etm_capture_driver_t oocd_trace_capture_driver
;
473 etm_capture_driver_t
*etm_capture_drivers
[] =
476 &etm_dummy_capture_driver
,
477 #if BUILD_OOCD_TRACE == 1
478 &oocd_trace_capture_driver
,
483 char *etmv1v1_branch_reason_strings
[] =
487 "trace restarted after overflow",
489 "periodic synchronization",
495 int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
504 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
506 /* search for the section the current instruction belongs to */
507 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
509 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
510 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
519 /* current instruction couldn't be found in the image */
520 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
523 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
526 if ((retval
= image_read_section(ctx
->image
, section
,
527 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
528 4, buf
, &size_read
)) != ERROR_OK
)
530 ERROR("error while reading instruction: %i", retval
);
531 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
533 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
534 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
536 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
539 if ((retval
= image_read_section(ctx
->image
, section
,
540 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
541 2, buf
, &size_read
)) != ERROR_OK
)
543 ERROR("error while reading instruction: %i", retval
);
544 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
546 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
547 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
549 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
551 ERROR("BUG: tracing of jazelle code not supported");
556 ERROR("BUG: unknown core state encountered");
563 int etmv1_next_packet(etm_context_t
*ctx
, u8
*packet
, int apo
)
565 while (ctx
->data_index
< ctx
->trace_depth
)
567 /* if the caller specified an address packet offset, skip until the
568 * we reach the n-th cycle marked with tracesync */
571 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
582 /* no tracedata output during a TD cycle
583 * or in a trigger cycle */
584 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
585 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
592 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
594 if (ctx
->data_half
== 0)
596 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
601 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
606 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
608 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
613 /* on a 4-bit port, a packet will be output during two consecutive cycles */
614 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
617 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
618 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
619 ctx
->data_index
+= 2;
628 int etmv1_branch_address(etm_context_t
*ctx
)
636 /* quit analysis if less than two cycles are left in the trace
637 * because we can't extract the APO */
638 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
641 /* a BE could be output during an APO cycle, skip the current
642 * and continue with the new one */
643 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
645 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
648 /* address packet offset encoded in the next two cycles' pipestat bits */
649 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
650 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
652 /* count number of tracesync cycles between current pipe_index and data_index
653 * i.e. the number of tracesyncs that data_index already passed by
654 * to subtract them from the APO */
655 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
657 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
661 /* extract up to four 7-bit packets */
663 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
665 ctx
->last_branch
&= ~(0x7f << shift
);
666 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
668 } while ((packet
& 0x80) && (shift
< 28));
670 /* one last packet holding 4 bits of the address, plus the branch reason code */
671 if ((shift
== 28) && (packet
& 0x80))
673 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
675 ctx
->last_branch
&= 0x0fffffff;
676 ctx
->last_branch
|= (packet
& 0x0f) << 28;
677 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
682 ctx
->last_branch_reason
= 0;
690 /* if a full address was output, we might have branched into Jazelle state */
691 if ((shift
== 32) && (packet
& 0x80))
693 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
697 /* if we didn't branch into Jazelle state, the current processor state is
698 * encoded in bit 0 of the branch target address */
699 if (ctx
->last_branch
& 0x1)
701 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
702 ctx
->last_branch
&= ~0x1;
706 ctx
->core_state
= ARMV4_5_STATE_ARM
;
707 ctx
->last_branch
&= ~0x3;
714 int etmv1_data(etm_context_t
*ctx
, int size
, u32
*data
)
720 for (j
= 0; j
< size
; j
++)
722 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
727 ERROR("TODO: add support for 64-bit values");
729 *data
= target_buffer_get_u32(ctx
->target
, buf
);
731 *data
= target_buffer_get_u16(ctx
->target
, buf
);
738 int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
741 arm_instruction_t instruction
;
743 /* read the trace data if it wasn't read already */
744 if (ctx
->trace_depth
== 0)
745 ctx
->capture_driver
->read_trace(ctx
);
747 /* start at the beginning of the captured trace */
752 /* neither the PC nor the data pointer are valid */
756 while (ctx
->pipe_index
< ctx
->trace_depth
)
758 u8 pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
759 u32 next_pc
= ctx
->current_pc
;
760 u32 old_data_index
= ctx
->data_index
;
761 u32 old_data_half
= ctx
->data_half
;
762 u32 old_index
= ctx
->pipe_index
;
763 u32 last_instruction
= ctx
->last_instruction
;
765 int current_pc_ok
= ctx
->pc_ok
;
767 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
769 command_print(cmd_ctx
, "--- trigger ---");
772 /* instructions execute in IE/D or BE/D cycles */
773 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
774 ctx
->last_instruction
= ctx
->pipe_index
;
776 /* if we don't have a valid pc skip until we reach an indirect branch */
777 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
783 /* any indirect branch could have interrupted instruction flow
784 * - the branch reason code could indicate a trace discontinuity
785 * - a branch to the exception vectors indicates an exception
787 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
789 /* backup current data index, to be able to consume the branch address
790 * before examining data address and values
792 old_data_index
= ctx
->data_index
;
793 old_data_half
= ctx
->data_half
;
795 ctx
->last_instruction
= ctx
->pipe_index
;
797 if ((retval
= etmv1_branch_address(ctx
)) != 0)
799 /* negative return value from etmv1_branch_address means we ran out of packets,
800 * quit analysing the trace */
804 /* a positive return values means the current branch was abandoned,
805 * and a new branch was encountered in cycle ctx->pipe_index + retval;
807 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
808 ctx
->pipe_index
+= retval
;
812 /* skip over APO cycles */
813 ctx
->pipe_index
+= 2;
815 switch (ctx
->last_branch_reason
)
817 case 0x0: /* normal PC change */
818 next_pc
= ctx
->last_branch
;
820 case 0x1: /* tracing enabled */
821 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8x ---", ctx
->last_branch
);
822 ctx
->current_pc
= ctx
->last_branch
;
826 case 0x2: /* trace restarted after FIFO overflow */
827 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx
->last_branch
);
828 ctx
->current_pc
= ctx
->last_branch
;
832 case 0x3: /* exit from debug state */
833 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8x ---", ctx
->last_branch
);
834 ctx
->current_pc
= ctx
->last_branch
;
838 case 0x4: /* periodic synchronization point */
839 next_pc
= ctx
->last_branch
;
840 /* if we had no valid PC prior to this synchronization point,
841 * we have to move on with the next trace cycle
845 command_print(cmd_ctx
, "--- periodic synchronization point at 0x%8.8x ---", next_pc
);
846 ctx
->current_pc
= next_pc
;
851 default: /* reserved */
852 ERROR("BUG: branch reason code 0x%x is reserved", ctx
->last_branch_reason
);
857 /* if we got here the branch was a normal PC change
858 * (or a periodic synchronization point, which means the same for that matter)
859 * if we didn't accquire a complete PC continue with the next cycle
864 /* indirect branch to the exception vector means an exception occured */
865 if (((ctx
->last_branch
>= 0x0) && (ctx
->last_branch
<= 0x20))
866 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
868 if ((ctx
->last_branch
& 0xff) == 0x10)
870 command_print(cmd_ctx
, "data abort");
874 command_print(cmd_ctx
, "exception vector 0x%2.2x", ctx
->last_branch
);
875 ctx
->current_pc
= ctx
->last_branch
;
882 /* an instruction was executed (or not, depending on the condition flags)
883 * retrieve it from the image for displaying */
884 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
885 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
886 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
888 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
890 /* can't continue tracing with no image available */
891 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
895 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
897 /* TODO: handle incomplete images
898 * for now we just quit the analsysis*/
903 cycles
= old_index
- last_instruction
;
906 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
908 u32 new_data_index
= ctx
->data_index
;
909 u32 new_data_half
= ctx
->data_half
;
911 /* in case of a branch with data, the branch target address was consumed before
912 * we temporarily go back to the saved data index */
913 if (pipestat
== STAT_BD
)
915 ctx
->data_index
= old_data_index
;
916 ctx
->data_half
= old_data_half
;
919 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
925 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
926 return ERROR_ETM_ANALYSIS_FAILED
;
927 ctx
->last_ptr
&= ~(0x7f << shift
);
928 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
930 } while ((packet
& 0x80) && (shift
< 32));
937 command_print(cmd_ctx
, "address: 0x%8.8x", ctx
->last_ptr
);
941 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
943 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
946 for (i
= 0; i
< 16; i
++)
948 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
951 if (etmv1_data(ctx
, 4, &data
) != 0)
952 return ERROR_ETM_ANALYSIS_FAILED
;
953 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
957 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
960 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
961 return ERROR_ETM_ANALYSIS_FAILED
;
962 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
966 /* restore data index after consuming BD address and data */
967 if (pipestat
== STAT_BD
)
969 ctx
->data_index
= new_data_index
;
970 ctx
->data_half
= new_data_half
;
975 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
977 if (((instruction
.type
== ARM_B
) ||
978 (instruction
.type
== ARM_BL
) ||
979 (instruction
.type
== ARM_BLX
)) &&
980 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1))
982 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
986 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
989 else if (pipestat
== STAT_IN
)
991 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
994 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
996 char cycles_text
[32] = "";
998 /* if the trace was captured with cycle accurate tracing enabled,
999 * output the number of cycles since the last executed instruction
1001 if (ctx
->tracemode
& ETMV1_CYCLE_ACCURATE
)
1003 snprintf(cycles_text
, 32, " (%i %s)",
1005 (cycles
== 1) ? "cycle" : "cycles");
1008 command_print(cmd_ctx
, "%s%s%s",
1010 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1013 ctx
->current_pc
= next_pc
;
1015 /* packets for an instruction don't start on or before the preceding
1016 * functional pipestat (i.e. other than WT or TD)
1018 if (ctx
->data_index
<= ctx
->pipe_index
)
1020 ctx
->data_index
= ctx
->pipe_index
+ 1;
1025 ctx
->pipe_index
+= 1;
1031 int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1034 armv4_5_common_t
*armv4_5
;
1035 arm7_9_common_t
*arm7_9
;
1036 etmv1_tracemode_t tracemode
;
1038 target
= get_current_target(cmd_ctx
);
1040 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1042 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1046 if (!arm7_9
->etm_ctx
)
1048 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1052 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1056 if (strcmp(args
[0], "none") == 0)
1058 tracemode
= ETMV1_TRACE_NONE
;
1060 else if (strcmp(args
[0], "data") == 0)
1062 tracemode
= ETMV1_TRACE_DATA
;
1064 else if (strcmp(args
[0], "address") == 0)
1066 tracemode
= ETMV1_TRACE_ADDR
;
1068 else if (strcmp(args
[0], "all") == 0)
1070 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1074 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1078 switch (strtol(args
[1], NULL
, 0))
1081 tracemode
|= ETMV1_CONTEXTID_NONE
;
1084 tracemode
|= ETMV1_CONTEXTID_8
;
1087 tracemode
|= ETMV1_CONTEXTID_16
;
1090 tracemode
|= ETMV1_CONTEXTID_32
;
1093 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1097 if (strcmp(args
[2], "enable") == 0)
1099 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1101 else if (strcmp(args
[2], "disable") == 0)
1107 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1111 if (strcmp(args
[3], "enable") == 0)
1113 tracemode
|= ETMV1_BRANCH_OUTPUT
;
1115 else if (strcmp(args
[3], "disable") == 0)
1121 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1127 command_print(cmd_ctx
, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1131 command_print(cmd_ctx
, "current tracemode configuration:");
1133 switch (tracemode
& ETMV1_TRACE_MASK
)
1135 case ETMV1_TRACE_NONE
:
1136 command_print(cmd_ctx
, "data tracing: none");
1138 case ETMV1_TRACE_DATA
:
1139 command_print(cmd_ctx
, "data tracing: data only");
1141 case ETMV1_TRACE_ADDR
:
1142 command_print(cmd_ctx
, "data tracing: address only");
1144 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1145 command_print(cmd_ctx
, "data tracing: address and data");
1149 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1151 case ETMV1_CONTEXTID_NONE
:
1152 command_print(cmd_ctx
, "contextid tracing: none");
1154 case ETMV1_CONTEXTID_8
:
1155 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1157 case ETMV1_CONTEXTID_16
:
1158 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1160 case ETMV1_CONTEXTID_32
:
1161 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1165 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1167 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1171 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1174 if (tracemode
& ETMV1_BRANCH_OUTPUT
)
1176 command_print(cmd_ctx
, "full branch address output enabled");
1180 command_print(cmd_ctx
, "full branch address output disabled");
1183 /* only update ETM_CTRL register if tracemode changed */
1184 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1186 reg_t
*etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1188 etm_get_reg(etm_ctrl_reg
);
1190 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1191 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1192 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1193 buf_set_u32(etm_ctrl_reg
->value
, 8, 1, (tracemode
& ETMV1_BRANCH_OUTPUT
) >> 9);
1194 etm_store_reg(etm_ctrl_reg
);
1196 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1198 /* invalidate old trace data */
1199 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1200 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1202 free(arm7_9
->etm_ctx
->trace_data
);
1203 arm7_9
->etm_ctx
->trace_data
= NULL
;
1205 arm7_9
->etm_ctx
->trace_depth
= 0;
1211 int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1214 armv4_5_common_t
*armv4_5
;
1215 arm7_9_common_t
*arm7_9
;
1216 etm_portmode_t portmode
= 0x0;
1217 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1222 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1226 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
1230 ERROR("target number '%s' not defined", args
[0]);
1234 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1236 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1240 switch (strtoul(args
[1], NULL
, 0))
1243 portmode
|= ETM_PORT_4BIT
;
1246 portmode
|= ETM_PORT_8BIT
;
1249 portmode
|= ETM_PORT_16BIT
;
1252 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1256 if (strcmp("normal", args
[2]) == 0)
1258 portmode
|= ETM_PORT_NORMAL
;
1260 else if (strcmp("multiplexed", args
[2]) == 0)
1262 portmode
|= ETM_PORT_MUXED
;
1264 else if (strcmp("demultiplexed", args
[2]) == 0)
1266 portmode
|= ETM_PORT_DEMUXED
;
1270 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1274 if (strcmp("half", args
[3]) == 0)
1276 portmode
|= ETM_PORT_HALF_CLOCK
;
1278 else if (strcmp("full", args
[3]) == 0)
1280 portmode
|= ETM_PORT_FULL_CLOCK
;
1284 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1288 for (i
=0; etm_capture_drivers
[i
]; i
++)
1290 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1292 if (etm_capture_drivers
[i
]->register_commands(cmd_ctx
) != ERROR_OK
)
1298 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1304 if (!etm_capture_drivers
[i
])
1306 /* no supported capture driver found, don't register an ETM */
1308 ERROR("trace capture driver '%s' not found", args
[4]);
1312 etm_ctx
->target
= target
;
1313 etm_ctx
->trigger_percent
= 50;
1314 etm_ctx
->trace_data
= NULL
;
1315 etm_ctx
->trace_depth
= 0;
1316 etm_ctx
->portmode
= portmode
;
1317 etm_ctx
->tracemode
= 0x0;
1318 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1319 etm_ctx
->image
= NULL
;
1320 etm_ctx
->pipe_index
= 0;
1321 etm_ctx
->data_index
= 0;
1322 etm_ctx
->current_pc
= 0x0;
1324 etm_ctx
->last_branch
= 0x0;
1325 etm_ctx
->last_branch_reason
= 0x0;
1326 etm_ctx
->last_ptr
= 0x0;
1327 etm_ctx
->ptr_ok
= 0x0;
1328 etm_ctx
->context_id
= 0x0;
1329 etm_ctx
->last_instruction
= 0;
1331 arm7_9
->etm_ctx
= etm_ctx
;
1333 etm_register_user_commands(cmd_ctx
);
1338 int handle_etm_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1341 armv4_5_common_t
*armv4_5
;
1342 arm7_9_common_t
*arm7_9
;
1343 reg_t
*etm_config_reg
;
1344 reg_t
*etm_sys_config_reg
;
1348 target
= get_current_target(cmd_ctx
);
1350 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1352 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1356 if (!arm7_9
->etm_ctx
)
1358 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1362 etm_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CONFIG
];
1363 etm_sys_config_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_SYS_CONFIG
];
1365 etm_get_reg(etm_config_reg
);
1366 command_print(cmd_ctx
, "pairs of address comparators: %i", buf_get_u32(etm_config_reg
->value
, 0, 4));
1367 command_print(cmd_ctx
, "pairs of data comparators: %i", buf_get_u32(etm_config_reg
->value
, 4, 4));
1368 command_print(cmd_ctx
, "memory map decoders: %i", buf_get_u32(etm_config_reg
->value
, 8, 5));
1369 command_print(cmd_ctx
, "number of counters: %i", buf_get_u32(etm_config_reg
->value
, 13, 3));
1370 command_print(cmd_ctx
, "sequencer %spresent",
1371 (buf_get_u32(etm_config_reg
->value
, 16, 1) == 1) ? "" : "not ");
1372 command_print(cmd_ctx
, "number of ext. inputs: %i", buf_get_u32(etm_config_reg
->value
, 17, 3));
1373 command_print(cmd_ctx
, "number of ext. outputs: %i", buf_get_u32(etm_config_reg
->value
, 20, 3));
1374 command_print(cmd_ctx
, "FIFO full %spresent",
1375 (buf_get_u32(etm_config_reg
->value
, 23, 1) == 1) ? "" : "not ");
1376 command_print(cmd_ctx
, "protocol version: %i", buf_get_u32(etm_config_reg
->value
, 28, 3));
1378 etm_get_reg(etm_sys_config_reg
);
1380 switch (buf_get_u32(etm_sys_config_reg
->value
, 0, 3))
1392 command_print(cmd_ctx
, "max. port size: %i", max_port_size
);
1394 command_print(cmd_ctx
, "half-rate clocking %ssupported",
1395 (buf_get_u32(etm_sys_config_reg
->value
, 3, 1) == 1) ? "" : "not ");
1396 command_print(cmd_ctx
, "full-rate clocking %ssupported",
1397 (buf_get_u32(etm_sys_config_reg
->value
, 4, 1) == 1) ? "" : "not ");
1398 command_print(cmd_ctx
, "normal trace format %ssupported",
1399 (buf_get_u32(etm_sys_config_reg
->value
, 5, 1) == 1) ? "" : "not ");
1400 command_print(cmd_ctx
, "multiplex trace format %ssupported",
1401 (buf_get_u32(etm_sys_config_reg
->value
, 6, 1) == 1) ? "" : "not ");
1402 command_print(cmd_ctx
, "demultiplex trace format %ssupported",
1403 (buf_get_u32(etm_sys_config_reg
->value
, 7, 1) == 1) ? "" : "not ");
1404 command_print(cmd_ctx
, "FIFO full %ssupported",
1405 (buf_get_u32(etm_sys_config_reg
->value
, 8, 1) == 1) ? "" : "not ");
1410 int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1413 armv4_5_common_t
*armv4_5
;
1414 arm7_9_common_t
*arm7_9
;
1415 trace_status_t trace_status
;
1417 target
= get_current_target(cmd_ctx
);
1419 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1421 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1425 if (!arm7_9
->etm_ctx
)
1427 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1431 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1433 if (trace_status
== TRACE_IDLE
)
1435 command_print(cmd_ctx
, "tracing is idle");
1439 static char *completed
= " completed";
1440 static char *running
= " is running";
1441 static char *overflowed
= ", trace overflowed";
1442 static char *triggered
= ", trace triggered";
1444 command_print(cmd_ctx
, "trace collection%s%s%s",
1445 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1446 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1447 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1449 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1451 command_print(cmd_ctx
, "%i frames of trace data read", arm7_9
->etm_ctx
->trace_depth
);
1458 int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1461 armv4_5_common_t
*armv4_5
;
1462 arm7_9_common_t
*arm7_9
;
1463 etm_context_t
*etm_ctx
;
1467 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1471 target
= get_current_target(cmd_ctx
);
1473 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1475 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1479 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1481 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1487 image_close(etm_ctx
->image
);
1488 free(etm_ctx
->image
);
1489 command_print(cmd_ctx
, "previously loaded image found and closed");
1492 etm_ctx
->image
= malloc(sizeof(image_t
));
1493 etm_ctx
->image
->base_address_set
= 0;
1494 etm_ctx
->image
->start_address_set
= 0;
1496 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1499 etm_ctx
->image
->base_address_set
= 1;
1500 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1504 etm_ctx
->image
->base_address_set
= 0;
1507 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1509 command_print(cmd_ctx
, "image opening error: %s", etm_ctx
->image
->error_str
);
1510 free(etm_ctx
->image
);
1511 etm_ctx
->image
= NULL
;
1518 int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1522 armv4_5_common_t
*armv4_5
;
1523 arm7_9_common_t
*arm7_9
;
1524 etm_context_t
*etm_ctx
;
1529 command_print(cmd_ctx
, "usage: etm dump <file>");
1533 target
= get_current_target(cmd_ctx
);
1535 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1537 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1541 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1543 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1547 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1549 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1553 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1555 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1556 command_print(cmd_ctx
, "trace capture not completed");
1560 /* read the trace data if it wasn't read already */
1561 if (etm_ctx
->trace_depth
== 0)
1562 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1564 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1566 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1570 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1571 fileio_write_u32(&file
, etm_ctx
->portmode
);
1572 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1573 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1575 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1577 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1578 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1579 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1582 fileio_close(&file
);
1587 int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1591 armv4_5_common_t
*armv4_5
;
1592 arm7_9_common_t
*arm7_9
;
1593 etm_context_t
*etm_ctx
;
1598 command_print(cmd_ctx
, "usage: etm load <file>");
1602 target
= get_current_target(cmd_ctx
);
1604 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1606 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1610 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1612 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1616 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1618 command_print(cmd_ctx
, "trace capture running, stop first");
1622 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1624 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1630 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1634 if (etm_ctx
->trace_depth
> 0)
1636 free(etm_ctx
->trace_data
);
1639 fileio_read_u32(&file
, &etm_ctx
->capture_status
);
1640 fileio_read_u32(&file
, &etm_ctx
->portmode
);
1641 fileio_read_u32(&file
, &etm_ctx
->tracemode
);
1642 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1644 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1646 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1648 u32 pipestat
, packet
, flags
;
1649 fileio_read_u32(&file
, &pipestat
);
1650 fileio_read_u32(&file
, &packet
);
1651 fileio_read_u32(&file
, &flags
);
1652 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1653 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1654 etm_ctx
->trace_data
[i
].flags
= flags
;
1657 fileio_close(&file
);
1662 int handle_etm_trigger_percent_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1665 armv4_5_common_t
*armv4_5
;
1666 arm7_9_common_t
*arm7_9
;
1667 etm_context_t
*etm_ctx
;
1669 target
= get_current_target(cmd_ctx
);
1671 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1673 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1677 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1679 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1685 u32 new_value
= strtoul(args
[0], NULL
, 0);
1687 if ((new_value
< 2) || (new_value
> 100))
1689 command_print(cmd_ctx
, "valid settings are 2% to 100%");
1693 etm_ctx
->trigger_percent
= new_value
;
1697 command_print(cmd_ctx
, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx
->trigger_percent
);
1702 int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1705 armv4_5_common_t
*armv4_5
;
1706 arm7_9_common_t
*arm7_9
;
1707 etm_context_t
*etm_ctx
;
1708 reg_t
*etm_ctrl_reg
;
1710 target
= get_current_target(cmd_ctx
);
1712 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1714 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1718 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1720 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1724 /* invalidate old tracing data */
1725 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1726 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1728 free(arm7_9
->etm_ctx
->trace_data
);
1729 arm7_9
->etm_ctx
->trace_data
= NULL
;
1731 arm7_9
->etm_ctx
->trace_depth
= 0;
1733 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1734 etm_get_reg(etm_ctrl_reg
);
1736 /* Clear programming bit (10), set port selection bit (11) */
1737 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1739 etm_store_reg(etm_ctrl_reg
);
1740 jtag_execute_queue();
1742 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1747 int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1750 armv4_5_common_t
*armv4_5
;
1751 arm7_9_common_t
*arm7_9
;
1752 etm_context_t
*etm_ctx
;
1753 reg_t
*etm_ctrl_reg
;
1755 target
= get_current_target(cmd_ctx
);
1757 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1759 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1763 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1765 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1769 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1770 etm_get_reg(etm_ctrl_reg
);
1772 /* Set programming bit (10), clear port selection bit (11) */
1773 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1775 etm_store_reg(etm_ctrl_reg
);
1776 jtag_execute_queue();
1778 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1783 int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1786 armv4_5_common_t
*armv4_5
;
1787 arm7_9_common_t
*arm7_9
;
1788 etm_context_t
*etm_ctx
;
1791 target
= get_current_target(cmd_ctx
);
1793 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1795 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1799 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1801 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1805 if ((retval
= etmv1_analyze_trace(etm_ctx
, cmd_ctx
)) != ERROR_OK
)
1809 case ERROR_ETM_ANALYSIS_FAILED
:
1810 command_print(cmd_ctx
, "further analysis failed (corrupted trace data or just end of data");
1812 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1813 command_print(cmd_ctx
, "no instruction for current address available, analysis aborted");
1815 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
1816 command_print(cmd_ctx
, "no image available for trace analysis");
1819 command_print(cmd_ctx
, "unknown error: %i", retval
);
1826 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1828 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1830 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
, COMMAND_CONFIG
, NULL
);
1835 int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
1837 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
1838 COMMAND_EXEC
, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1840 register_command(cmd_ctx
, etm_cmd
, "info", handle_etm_info_command
,
1841 COMMAND_EXEC
, "display info about the current target's ETM");
1843 register_command(cmd_ctx
, etm_cmd
, "trigger_percent <percent>", handle_etm_trigger_percent_command
,
1844 COMMAND_EXEC
, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1845 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
1846 COMMAND_EXEC
, "display current target's ETM status");
1847 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
1848 COMMAND_EXEC
, "start ETM trace collection");
1849 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
1850 COMMAND_EXEC
, "stop ETM trace collection");
1852 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
1853 COMMAND_EXEC
, "anaylze collected ETM trace");
1855 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
1856 COMMAND_EXEC
, "load image from <file> [base address]");
1858 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
1859 COMMAND_EXEC
, "dump captured trace data <file>");
1860 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
1861 COMMAND_EXEC
, "load trace data for analysis <file>");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)