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[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "armv4_5.h"
25 #include "etb.h"
26 #include "image.h"
27 #include "arm_disassembler.h"
28
29
30 /*
31 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
32 *
33 * ETM modules collect instruction and/or data trace information, compress
34 * it, and transfer it to a debugging host through either a (buffered) trace
35 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
36 *
37 * There are several generations of these modules. Original versions have
38 * JTAG access through a dedicated scan chain. Recent versions have added
39 * access via coprocessor instructions, memory addressing, and the ARM Debug
40 * Interface v5 (ADIv5); and phased out direct JTAG access.
41 *
42 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
43 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
44 * implying non-JTAG connectivity options.
45 *
46 * Relevant documentation includes:
47 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
48 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
49 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
50 */
51
52 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
53
54 enum {
55 RO, /* read/only */
56 WO, /* write/only */
57 RW, /* read/write */
58 };
59
60 struct etm_reg_info {
61 uint8_t addr;
62 uint8_t size; /* low-N of 32 bits */
63 uint8_t mode; /* RO, WO, RW */
64 uint8_t bcd_vers; /* 1.0, 2.0, etc */
65 char *name;
66 };
67
68 /*
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
73 */
74
75 /* core registers used to version/configure the ETM */
76 static const struct etm_reg_info etm_core[] = {
77 /* NOTE: we "know" the order here ... */
78 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
79 { ETM_ID, 32, RO, 0x20, "ETM_id", },
80 };
81
82 /* basic registers that are always there given the right ETM version */
83 static const struct etm_reg_info etm_basic[] = {
84 /* ETM Trace Registers */
85 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
86 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
87 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
88 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
89 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
90
91 /* TraceEnable configuration */
92 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
93 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
94 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
95 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
96
97 /* ViewData configuration (data trace) */
98 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
99 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
100 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
101 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
102
103 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
104
105 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
106 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
107 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
108 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
109 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
110 };
111
112 static const struct etm_reg_info etm_fifofull[] = {
113 /* FIFOFULL configuration */
114 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
115 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
116 };
117
118 static const struct etm_reg_info etm_addr_comp[] = {
119 /* Address comparator register pairs */
120 #define ADDR_COMPARATOR(i) \
121 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
122 "ETM_addr_" #i "_comparator_value", }, \
123 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
124 "ETM_addr_" #i "_access_type", }
125 ADDR_COMPARATOR(1),
126 ADDR_COMPARATOR(2),
127 ADDR_COMPARATOR(3),
128 ADDR_COMPARATOR(4),
129 ADDR_COMPARATOR(5),
130 ADDR_COMPARATOR(6),
131 ADDR_COMPARATOR(7),
132 ADDR_COMPARATOR(8),
133
134 ADDR_COMPARATOR(9),
135 ADDR_COMPARATOR(10),
136 ADDR_COMPARATOR(11),
137 ADDR_COMPARATOR(12),
138 ADDR_COMPARATOR(13),
139 ADDR_COMPARATOR(14),
140 ADDR_COMPARATOR(15),
141 ADDR_COMPARATOR(16),
142 #undef ADDR_COMPARATOR
143 };
144
145 static const struct etm_reg_info etm_data_comp[] = {
146 /* Data Value Comparators (NOTE: odd addresses are reserved) */
147 #define DATA_COMPARATOR(i) \
148 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
149 "ETM_data_" #i "_comparator_value", }, \
150 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
151 "ETM_data_" #i "_comparator_mask", }
152 DATA_COMPARATOR(1),
153 DATA_COMPARATOR(2),
154 DATA_COMPARATOR(3),
155 DATA_COMPARATOR(4),
156 DATA_COMPARATOR(5),
157 DATA_COMPARATOR(6),
158 DATA_COMPARATOR(7),
159 DATA_COMPARATOR(8),
160 #undef DATA_COMPARATOR
161 };
162
163 static const struct etm_reg_info etm_counters[] = {
164 #define ETM_COUNTER(i) \
165 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
166 "ETM_counter_" #i "_reload_value", }, \
167 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
168 "ETM_counter_" #i "_enable", }, \
169 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
170 "ETM_counter_" #i "_reload_event", }, \
171 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
172 "ETM_counter_" #i "_value", }
173 ETM_COUNTER(1),
174 ETM_COUNTER(2),
175 ETM_COUNTER(3),
176 ETM_COUNTER(4),
177 #undef ETM_COUNTER
178 };
179
180 static const struct etm_reg_info etm_sequencer[] = {
181 #define ETM_SEQ(i) \
182 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
183 "ETM_sequencer_event" #i, }
184 ETM_SEQ(0), /* 1->2 */
185 ETM_SEQ(1), /* 2->1 */
186 ETM_SEQ(2), /* 2->3 */
187 ETM_SEQ(3), /* 3->1 */
188 ETM_SEQ(4), /* 3->2 */
189 ETM_SEQ(5), /* 1->3 */
190 #undef ETM_SEQ
191 /* 0x66 reserved */
192 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
193 };
194
195 static const struct etm_reg_info etm_outputs[] = {
196 #define ETM_OUTPUT(i) \
197 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
198 "ETM_external_output" #i, }
199
200 ETM_OUTPUT(1),
201 ETM_OUTPUT(2),
202 ETM_OUTPUT(3),
203 ETM_OUTPUT(4),
204 #undef ETM_OUTPUT
205 };
206
207 #if 0
208 /* registers from 0x6c..0x7f were added after ETMv1.3 */
209
210 /* Context ID Comparators */
211 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
212 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
213 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
214 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
215 #endif
216
217 static int etm_reg_arch_type = -1;
218
219 static int etm_get_reg(reg_t *reg);
220 static int etm_read_reg_w_check(reg_t *reg,
221 uint8_t* check_value, uint8_t* check_mask);
222 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
223 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
224 static int etm_write_reg(reg_t *reg, uint32_t value);
225
226 static command_t *etm_cmd;
227
228
229 /* Look up register by ID ... most ETM instances only
230 * support a subset of the possible registers.
231 */
232 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
233 {
234 struct reg_cache *cache = etm_ctx->reg_cache;
235 int i;
236
237 for (i = 0; i < cache->num_regs; i++) {
238 struct etm_reg *reg = cache->reg_list[i].arch_info;
239
240 if (reg->reg_info->addr == id)
241 return &cache->reg_list[i];
242 }
243
244 /* caller asking for nonexistent register is a bug! */
245 /* REVISIT say which of the N targets was involved */
246 LOG_ERROR("ETM: register 0x%02x not available", id);
247 return NULL;
248 }
249
250 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
251 struct reg_cache *cache, struct etm_reg *ereg,
252 const struct etm_reg_info *r, unsigned nreg)
253 {
254 reg_t *reg = cache->reg_list;
255
256 reg += cache->num_regs;
257 ereg += cache->num_regs;
258
259 /* add up to "nreg" registers from "r", if supported by this
260 * version of the ETM, to the specified cache.
261 */
262 for (; nreg--; r++) {
263
264 /* this ETM may be too old to have some registers */
265 if (r->bcd_vers > bcd_vers)
266 continue;
267
268 reg->name = r->name;
269 reg->size = r->size;
270 reg->value = &ereg->value;
271 reg->arch_info = ereg;
272 reg->arch_type = etm_reg_arch_type;
273 reg++;
274 cache->num_regs++;
275
276 ereg->reg_info = r;
277 ereg->jtag_info = jtag_info;
278 ereg++;
279 }
280 }
281
282 struct reg_cache *etm_build_reg_cache(target_t *target,
283 struct arm_jtag *jtag_info, etm_context_t *etm_ctx)
284 {
285 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
286 reg_t *reg_list = NULL;
287 struct etm_reg *arch_info = NULL;
288 unsigned bcd_vers, config;
289
290 /* register a register arch-type for etm registers only once */
291 if (etm_reg_arch_type == -1)
292 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
293 etm_set_reg_w_exec);
294
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(reg_t));
297 arch_info = calloc(128, sizeof(struct etm_reg));
298
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
304
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
307 */
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
309 etm_core, 1);
310
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
314
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
317 bcd_vers = 0x20;
318 LOG_WARNING("ETMv2+ support is incomplete");
319
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
324 */
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
326 etm_core + 1, 1);
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
332
333 } else {
334 switch (config >> 28) {
335 case 7:
336 case 5:
337 case 3:
338 bcd_vers = 0x13;
339 break;
340 case 4:
341 case 2:
342 bcd_vers = 0x12;
343 break;
344 case 1:
345 bcd_vers = 0x11;
346 break;
347 case 0:
348 bcd_vers = 0x10;
349 break;
350 default:
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 free(reg_cache);
353 free(reg_list);
354 free(arch_info);
355 return ERROR_OK;
356 }
357 }
358 etm_ctx->bcd_vers = bcd_vers;
359 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
360
361 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
362 etm_basic, ARRAY_SIZE(etm_basic));
363
364 /* address and data comparators; counters; outputs */
365 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
366 etm_addr_comp, 4 * (0x0f & (config >> 0)));
367 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
368 etm_data_comp, 2 * (0x0f & (config >> 4)));
369 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370 etm_counters, 4 * (0x07 & (config >> 13)));
371 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
372 etm_outputs, (0x07 & (config >> 20)));
373
374 /* FIFOFULL presence is optional
375 * REVISIT for ETMv1.2 and later, don't bother adding this
376 * unless ETM_SYS_CONFIG says it's also *supported* ...
377 */
378 if (config & (1 << 23))
379 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
380 etm_fifofull, ARRAY_SIZE(etm_fifofull));
381
382 /* sequencer is optional (for state-dependant triggering) */
383 if (config & (1 << 16))
384 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
385 etm_sequencer, ARRAY_SIZE(etm_sequencer));
386
387 /* REVISIT could realloc and likely save half the memory
388 * in the two chunks we allocated...
389 */
390
391 /* the ETM might have an ETB connected */
392 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
393 {
394 struct etb *etb = etm_ctx->capture_driver_priv;
395
396 if (!etb)
397 {
398 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
399 free(reg_cache);
400 free(reg_list);
401 free(arch_info);
402 return ERROR_OK;
403 }
404
405 reg_cache->next = etb_build_reg_cache(etb);
406
407 etb->reg_cache = reg_cache->next;
408 }
409
410 etm_ctx->reg_cache = reg_cache;
411 return reg_cache;
412 }
413
414 static int etm_read_reg(reg_t *reg)
415 {
416 return etm_read_reg_w_check(reg, NULL, NULL);
417 }
418
419 static int etm_store_reg(reg_t *reg)
420 {
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
422 }
423
424 int etm_setup(target_t *target)
425 {
426 int retval;
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 etm_context_t *etm_ctx = arm->etm;
430 reg_t *etm_ctrl_reg;
431
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 if (!etm_ctrl_reg)
434 return ERROR_OK;
435
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
439
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~0x1;
442
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
445 */
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
449 & ~ETM_PORT_CLOCK_MASK)
450 | etm_ctx->portmode;
451
452 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
453 etm_store_reg(etm_ctrl_reg);
454
455 if ((retval = jtag_execute_queue()) != ERROR_OK)
456 return retval;
457
458 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
459 * verify that those width and mode settings are OK ...
460 */
461
462 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
463 {
464 LOG_ERROR("ETM capture driver initialization failed");
465 return retval;
466 }
467 return ERROR_OK;
468 }
469
470 static int etm_get_reg(reg_t *reg)
471 {
472 int retval;
473
474 if ((retval = etm_read_reg(reg)) != ERROR_OK)
475 {
476 LOG_ERROR("BUG: error scheduling etm register read");
477 return retval;
478 }
479
480 if ((retval = jtag_execute_queue()) != ERROR_OK)
481 {
482 LOG_ERROR("register read failed");
483 return retval;
484 }
485
486 return ERROR_OK;
487 }
488
489 static int etm_read_reg_w_check(reg_t *reg,
490 uint8_t* check_value, uint8_t* check_mask)
491 {
492 struct etm_reg *etm_reg = reg->arch_info;
493 const struct etm_reg_info *r = etm_reg->reg_info;
494 uint8_t reg_addr = r->addr & 0x7f;
495 struct scan_field fields[3];
496
497 if (etm_reg->reg_info->mode == WO) {
498 LOG_ERROR("BUG: can't read write-only register %s", r->name);
499 return ERROR_INVALID_ARGUMENTS;
500 }
501
502 LOG_DEBUG("%s (%u)", r->name, reg_addr);
503
504 jtag_set_end_state(TAP_IDLE);
505 arm_jtag_scann(etm_reg->jtag_info, 0x6);
506 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
507
508 fields[0].tap = etm_reg->jtag_info->tap;
509 fields[0].num_bits = 32;
510 fields[0].out_value = reg->value;
511 fields[0].in_value = NULL;
512 fields[0].check_value = NULL;
513 fields[0].check_mask = NULL;
514
515 fields[1].tap = etm_reg->jtag_info->tap;
516 fields[1].num_bits = 7;
517 fields[1].out_value = malloc(1);
518 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
519 fields[1].in_value = NULL;
520 fields[1].check_value = NULL;
521 fields[1].check_mask = NULL;
522
523 fields[2].tap = etm_reg->jtag_info->tap;
524 fields[2].num_bits = 1;
525 fields[2].out_value = malloc(1);
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].in_value = NULL;
528 fields[2].check_value = NULL;
529 fields[2].check_mask = NULL;
530
531 jtag_add_dr_scan(3, fields, jtag_get_end_state());
532
533 fields[0].in_value = reg->value;
534 fields[0].check_value = check_value;
535 fields[0].check_mask = check_mask;
536
537 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
538
539 free(fields[1].out_value);
540 free(fields[2].out_value);
541
542 return ERROR_OK;
543 }
544
545 static int etm_set_reg(reg_t *reg, uint32_t value)
546 {
547 int retval;
548
549 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
550 {
551 LOG_ERROR("BUG: error scheduling etm register write");
552 return retval;
553 }
554
555 buf_set_u32(reg->value, 0, reg->size, value);
556 reg->valid = 1;
557 reg->dirty = 0;
558
559 return ERROR_OK;
560 }
561
562 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
563 {
564 int retval;
565
566 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
567
568 if ((retval = jtag_execute_queue()) != ERROR_OK)
569 {
570 LOG_ERROR("register write failed");
571 return retval;
572 }
573 return ERROR_OK;
574 }
575
576 static int etm_write_reg(reg_t *reg, uint32_t value)
577 {
578 struct etm_reg *etm_reg = reg->arch_info;
579 const struct etm_reg_info *r = etm_reg->reg_info;
580 uint8_t reg_addr = r->addr & 0x7f;
581 struct scan_field fields[3];
582
583 if (etm_reg->reg_info->mode == RO) {
584 LOG_ERROR("BUG: can't write read--only register %s", r->name);
585 return ERROR_INVALID_ARGUMENTS;
586 }
587
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
589
590 jtag_set_end_state(TAP_IDLE);
591 arm_jtag_scann(etm_reg->jtag_info, 0x6);
592 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
593
594 fields[0].tap = etm_reg->jtag_info->tap;
595 fields[0].num_bits = 32;
596 uint8_t tmp1[4];
597 fields[0].out_value = tmp1;
598 buf_set_u32(fields[0].out_value, 0, 32, value);
599 fields[0].in_value = NULL;
600
601 fields[1].tap = etm_reg->jtag_info->tap;
602 fields[1].num_bits = 7;
603 uint8_t tmp2;
604 fields[1].out_value = &tmp2;
605 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
606 fields[1].in_value = NULL;
607
608 fields[2].tap = etm_reg->jtag_info->tap;
609 fields[2].num_bits = 1;
610 uint8_t tmp3;
611 fields[2].out_value = &tmp3;
612 buf_set_u32(fields[2].out_value, 0, 1, 1);
613 fields[2].in_value = NULL;
614
615 jtag_add_dr_scan(3, fields, jtag_get_end_state());
616
617 return ERROR_OK;
618 }
619
620
621 /* ETM trace analysis functionality
622 *
623 */
624 extern struct etm_capture_driver etm_dummy_capture_driver;
625 #if BUILD_OOCD_TRACE == 1
626 extern struct etm_capture_driver oocd_trace_capture_driver;
627 #endif
628
629 static struct etm_capture_driver *etm_capture_drivers[] =
630 {
631 &etb_capture_driver,
632 &etm_dummy_capture_driver,
633 #if BUILD_OOCD_TRACE == 1
634 &oocd_trace_capture_driver,
635 #endif
636 NULL
637 };
638
639 static int etm_read_instruction(etm_context_t *ctx, struct arm_instruction *instruction)
640 {
641 int i;
642 int section = -1;
643 uint32_t size_read;
644 uint32_t opcode;
645 int retval;
646
647 if (!ctx->image)
648 return ERROR_TRACE_IMAGE_UNAVAILABLE;
649
650 /* search for the section the current instruction belongs to */
651 for (i = 0; i < ctx->image->num_sections; i++)
652 {
653 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
654 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
655 {
656 section = i;
657 break;
658 }
659 }
660
661 if (section == -1)
662 {
663 /* current instruction couldn't be found in the image */
664 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
665 }
666
667 if (ctx->core_state == ARMV4_5_STATE_ARM)
668 {
669 uint8_t buf[4];
670 if ((retval = image_read_section(ctx->image, section,
671 ctx->current_pc - ctx->image->sections[section].base_address,
672 4, buf, &size_read)) != ERROR_OK)
673 {
674 LOG_ERROR("error while reading instruction: %i", retval);
675 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
676 }
677 opcode = target_buffer_get_u32(ctx->target, buf);
678 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
679 }
680 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
681 {
682 uint8_t buf[2];
683 if ((retval = image_read_section(ctx->image, section,
684 ctx->current_pc - ctx->image->sections[section].base_address,
685 2, buf, &size_read)) != ERROR_OK)
686 {
687 LOG_ERROR("error while reading instruction: %i", retval);
688 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
689 }
690 opcode = target_buffer_get_u16(ctx->target, buf);
691 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
692 }
693 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
694 {
695 LOG_ERROR("BUG: tracing of jazelle code not supported");
696 return ERROR_FAIL;
697 }
698 else
699 {
700 LOG_ERROR("BUG: unknown core state encountered");
701 return ERROR_FAIL;
702 }
703
704 return ERROR_OK;
705 }
706
707 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
708 {
709 while (ctx->data_index < ctx->trace_depth)
710 {
711 /* if the caller specified an address packet offset, skip until the
712 * we reach the n-th cycle marked with tracesync */
713 if (apo > 0)
714 {
715 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
716 apo--;
717
718 if (apo > 0)
719 {
720 ctx->data_index++;
721 ctx->data_half = 0;
722 }
723 continue;
724 }
725
726 /* no tracedata output during a TD cycle
727 * or in a trigger cycle */
728 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
729 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
730 {
731 ctx->data_index++;
732 ctx->data_half = 0;
733 continue;
734 }
735
736 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
737 {
738 if (ctx->data_half == 0)
739 {
740 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
741 ctx->data_half = 1;
742 }
743 else
744 {
745 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
746 ctx->data_half = 0;
747 ctx->data_index++;
748 }
749 }
750 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
751 {
752 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
753 ctx->data_index++;
754 }
755 else
756 {
757 /* on a 4-bit port, a packet will be output during two consecutive cycles */
758 if (ctx->data_index > (ctx->trace_depth - 2))
759 return -1;
760
761 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
762 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
763 ctx->data_index += 2;
764 }
765
766 return 0;
767 }
768
769 return -1;
770 }
771
772 static int etmv1_branch_address(etm_context_t *ctx)
773 {
774 int retval;
775 uint8_t packet;
776 int shift = 0;
777 int apo;
778 uint32_t i;
779
780 /* quit analysis if less than two cycles are left in the trace
781 * because we can't extract the APO */
782 if (ctx->data_index > (ctx->trace_depth - 2))
783 return -1;
784
785 /* a BE could be output during an APO cycle, skip the current
786 * and continue with the new one */
787 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
788 return 1;
789 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
790 return 2;
791
792 /* address packet offset encoded in the next two cycles' pipestat bits */
793 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
794 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
795
796 /* count number of tracesync cycles between current pipe_index and data_index
797 * i.e. the number of tracesyncs that data_index already passed by
798 * to subtract them from the APO */
799 for (i = ctx->pipe_index; i < ctx->data_index; i++)
800 {
801 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
802 apo--;
803 }
804
805 /* extract up to four 7-bit packets */
806 do {
807 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
808 return -1;
809 ctx->last_branch &= ~(0x7f << shift);
810 ctx->last_branch |= (packet & 0x7f) << shift;
811 shift += 7;
812 } while ((packet & 0x80) && (shift < 28));
813
814 /* one last packet holding 4 bits of the address, plus the branch reason code */
815 if ((shift == 28) && (packet & 0x80))
816 {
817 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
818 return -1;
819 ctx->last_branch &= 0x0fffffff;
820 ctx->last_branch |= (packet & 0x0f) << 28;
821 ctx->last_branch_reason = (packet & 0x70) >> 4;
822 shift += 4;
823 }
824 else
825 {
826 ctx->last_branch_reason = 0;
827 }
828
829 if (shift == 32)
830 {
831 ctx->pc_ok = 1;
832 }
833
834 /* if a full address was output, we might have branched into Jazelle state */
835 if ((shift == 32) && (packet & 0x80))
836 {
837 ctx->core_state = ARMV4_5_STATE_JAZELLE;
838 }
839 else
840 {
841 /* if we didn't branch into Jazelle state, the current processor state is
842 * encoded in bit 0 of the branch target address */
843 if (ctx->last_branch & 0x1)
844 {
845 ctx->core_state = ARMV4_5_STATE_THUMB;
846 ctx->last_branch &= ~0x1;
847 }
848 else
849 {
850 ctx->core_state = ARMV4_5_STATE_ARM;
851 ctx->last_branch &= ~0x3;
852 }
853 }
854
855 return 0;
856 }
857
858 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
859 {
860 int j;
861 uint8_t buf[4];
862 int retval;
863
864 for (j = 0; j < size; j++)
865 {
866 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
867 return -1;
868 }
869
870 if (size == 8)
871 {
872 LOG_ERROR("TODO: add support for 64-bit values");
873 return -1;
874 }
875 else if (size == 4)
876 *data = target_buffer_get_u32(ctx->target, buf);
877 else if (size == 2)
878 *data = target_buffer_get_u16(ctx->target, buf);
879 else if (size == 1)
880 *data = buf[0];
881 else
882 return -1;
883
884 return 0;
885 }
886
887 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
888 {
889 int retval;
890 struct arm_instruction instruction;
891
892 /* read the trace data if it wasn't read already */
893 if (ctx->trace_depth == 0)
894 ctx->capture_driver->read_trace(ctx);
895
896 /* start at the beginning of the captured trace */
897 ctx->pipe_index = 0;
898 ctx->data_index = 0;
899 ctx->data_half = 0;
900
901 /* neither the PC nor the data pointer are valid */
902 ctx->pc_ok = 0;
903 ctx->ptr_ok = 0;
904
905 while (ctx->pipe_index < ctx->trace_depth)
906 {
907 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
908 uint32_t next_pc = ctx->current_pc;
909 uint32_t old_data_index = ctx->data_index;
910 uint32_t old_data_half = ctx->data_half;
911 uint32_t old_index = ctx->pipe_index;
912 uint32_t last_instruction = ctx->last_instruction;
913 uint32_t cycles = 0;
914 int current_pc_ok = ctx->pc_ok;
915
916 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
917 {
918 command_print(cmd_ctx, "--- trigger ---");
919 }
920
921 /* instructions execute in IE/D or BE/D cycles */
922 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
923 ctx->last_instruction = ctx->pipe_index;
924
925 /* if we don't have a valid pc skip until we reach an indirect branch */
926 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
927 {
928 ctx->pipe_index++;
929 continue;
930 }
931
932 /* any indirect branch could have interrupted instruction flow
933 * - the branch reason code could indicate a trace discontinuity
934 * - a branch to the exception vectors indicates an exception
935 */
936 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
937 {
938 /* backup current data index, to be able to consume the branch address
939 * before examining data address and values
940 */
941 old_data_index = ctx->data_index;
942 old_data_half = ctx->data_half;
943
944 ctx->last_instruction = ctx->pipe_index;
945
946 if ((retval = etmv1_branch_address(ctx)) != 0)
947 {
948 /* negative return value from etmv1_branch_address means we ran out of packets,
949 * quit analysing the trace */
950 if (retval < 0)
951 break;
952
953 /* a positive return values means the current branch was abandoned,
954 * and a new branch was encountered in cycle ctx->pipe_index + retval;
955 */
956 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
957 ctx->pipe_index += retval;
958 continue;
959 }
960
961 /* skip over APO cycles */
962 ctx->pipe_index += 2;
963
964 switch (ctx->last_branch_reason)
965 {
966 case 0x0: /* normal PC change */
967 next_pc = ctx->last_branch;
968 break;
969 case 0x1: /* tracing enabled */
970 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
971 ctx->current_pc = ctx->last_branch;
972 ctx->pipe_index++;
973 continue;
974 break;
975 case 0x2: /* trace restarted after FIFO overflow */
976 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
977 ctx->current_pc = ctx->last_branch;
978 ctx->pipe_index++;
979 continue;
980 break;
981 case 0x3: /* exit from debug state */
982 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
983 ctx->current_pc = ctx->last_branch;
984 ctx->pipe_index++;
985 continue;
986 break;
987 case 0x4: /* periodic synchronization point */
988 next_pc = ctx->last_branch;
989 /* if we had no valid PC prior to this synchronization point,
990 * we have to move on with the next trace cycle
991 */
992 if (!current_pc_ok)
993 {
994 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
995 ctx->current_pc = next_pc;
996 ctx->pipe_index++;
997 continue;
998 }
999 break;
1000 default: /* reserved */
1001 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1002 return ERROR_FAIL;
1003 }
1004
1005 /* if we got here the branch was a normal PC change
1006 * (or a periodic synchronization point, which means the same for that matter)
1007 * if we didn't accquire a complete PC continue with the next cycle
1008 */
1009 if (!ctx->pc_ok)
1010 continue;
1011
1012 /* indirect branch to the exception vector means an exception occured */
1013 if ((ctx->last_branch <= 0x20)
1014 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1015 {
1016 if ((ctx->last_branch & 0xff) == 0x10)
1017 {
1018 command_print(cmd_ctx, "data abort");
1019 }
1020 else
1021 {
1022 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1023 ctx->current_pc = ctx->last_branch;
1024 ctx->pipe_index++;
1025 continue;
1026 }
1027 }
1028 }
1029
1030 /* an instruction was executed (or not, depending on the condition flags)
1031 * retrieve it from the image for displaying */
1032 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1033 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1034 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1035 {
1036 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1037 {
1038 /* can't continue tracing with no image available */
1039 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1040 {
1041 return retval;
1042 }
1043 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1044 {
1045 /* TODO: handle incomplete images
1046 * for now we just quit the analsysis*/
1047 return retval;
1048 }
1049 }
1050
1051 cycles = old_index - last_instruction;
1052 }
1053
1054 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1055 {
1056 uint32_t new_data_index = ctx->data_index;
1057 uint32_t new_data_half = ctx->data_half;
1058
1059 /* in case of a branch with data, the branch target address was consumed before
1060 * we temporarily go back to the saved data index */
1061 if (pipestat == STAT_BD)
1062 {
1063 ctx->data_index = old_data_index;
1064 ctx->data_half = old_data_half;
1065 }
1066
1067 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1068 {
1069 uint8_t packet;
1070 int shift = 0;
1071
1072 do {
1073 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1074 return ERROR_ETM_ANALYSIS_FAILED;
1075 ctx->last_ptr &= ~(0x7f << shift);
1076 ctx->last_ptr |= (packet & 0x7f) << shift;
1077 shift += 7;
1078 } while ((packet & 0x80) && (shift < 32));
1079
1080 if (shift >= 32)
1081 ctx->ptr_ok = 1;
1082
1083 if (ctx->ptr_ok)
1084 {
1085 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1086 }
1087 }
1088
1089 if (ctx->tracemode & ETMV1_TRACE_DATA)
1090 {
1091 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1092 {
1093 int i;
1094 for (i = 0; i < 16; i++)
1095 {
1096 if (instruction.info.load_store_multiple.register_list & (1 << i))
1097 {
1098 uint32_t data;
1099 if (etmv1_data(ctx, 4, &data) != 0)
1100 return ERROR_ETM_ANALYSIS_FAILED;
1101 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1102 }
1103 }
1104 }
1105 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1106 {
1107 uint32_t data;
1108 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1109 return ERROR_ETM_ANALYSIS_FAILED;
1110 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1111 }
1112 }
1113
1114 /* restore data index after consuming BD address and data */
1115 if (pipestat == STAT_BD)
1116 {
1117 ctx->data_index = new_data_index;
1118 ctx->data_half = new_data_half;
1119 }
1120 }
1121
1122 /* adjust PC */
1123 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1124 {
1125 if (((instruction.type == ARM_B) ||
1126 (instruction.type == ARM_BL) ||
1127 (instruction.type == ARM_BLX)) &&
1128 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1129 {
1130 next_pc = instruction.info.b_bl_bx_blx.target_address;
1131 }
1132 else
1133 {
1134 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1135 }
1136 }
1137 else if (pipestat == STAT_IN)
1138 {
1139 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1140 }
1141
1142 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1143 {
1144 char cycles_text[32] = "";
1145
1146 /* if the trace was captured with cycle accurate tracing enabled,
1147 * output the number of cycles since the last executed instruction
1148 */
1149 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1150 {
1151 snprintf(cycles_text, 32, " (%i %s)",
1152 (int)cycles,
1153 (cycles == 1) ? "cycle" : "cycles");
1154 }
1155
1156 command_print(cmd_ctx, "%s%s%s",
1157 instruction.text,
1158 (pipestat == STAT_IN) ? " (not executed)" : "",
1159 cycles_text);
1160
1161 ctx->current_pc = next_pc;
1162
1163 /* packets for an instruction don't start on or before the preceding
1164 * functional pipestat (i.e. other than WT or TD)
1165 */
1166 if (ctx->data_index <= ctx->pipe_index)
1167 {
1168 ctx->data_index = ctx->pipe_index + 1;
1169 ctx->data_half = 0;
1170 }
1171 }
1172
1173 ctx->pipe_index += 1;
1174 }
1175
1176 return ERROR_OK;
1177 }
1178
1179 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1180 etmv1_tracemode_t *mode)
1181 {
1182 etmv1_tracemode_t tracemode;
1183
1184 /* what parts of data access are traced? */
1185 if (strcmp(args[0], "none") == 0)
1186 tracemode = ETMV1_TRACE_NONE;
1187 else if (strcmp(args[0], "data") == 0)
1188 tracemode = ETMV1_TRACE_DATA;
1189 else if (strcmp(args[0], "address") == 0)
1190 tracemode = ETMV1_TRACE_ADDR;
1191 else if (strcmp(args[0], "all") == 0)
1192 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1193 else
1194 {
1195 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1196 return ERROR_INVALID_ARGUMENTS;
1197 }
1198
1199 uint8_t context_id;
1200 COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1201 switch (context_id)
1202 {
1203 case 0:
1204 tracemode |= ETMV1_CONTEXTID_NONE;
1205 break;
1206 case 8:
1207 tracemode |= ETMV1_CONTEXTID_8;
1208 break;
1209 case 16:
1210 tracemode |= ETMV1_CONTEXTID_16;
1211 break;
1212 case 32:
1213 tracemode |= ETMV1_CONTEXTID_32;
1214 break;
1215 default:
1216 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1217 return ERROR_INVALID_ARGUMENTS;
1218 }
1219
1220 if (strcmp(args[2], "enable") == 0)
1221 tracemode |= ETMV1_CYCLE_ACCURATE;
1222 else if (strcmp(args[2], "disable") == 0)
1223 tracemode |= 0;
1224 else
1225 {
1226 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1227 return ERROR_INVALID_ARGUMENTS;
1228 }
1229
1230 if (strcmp(args[3], "enable") == 0)
1231 tracemode |= ETMV1_BRANCH_OUTPUT;
1232 else if (strcmp(args[3], "disable") == 0)
1233 tracemode |= 0;
1234 else
1235 {
1236 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1237 return ERROR_INVALID_ARGUMENTS;
1238 }
1239
1240 /* IGNORED:
1241 * - CPRT tracing (coprocessor register transfers)
1242 * - debug request (causes debug entry on trigger)
1243 * - stall on FIFOFULL (preventing tracedata lossage)
1244 */
1245 *mode = tracemode;
1246
1247 return ERROR_OK;
1248 }
1249
1250 COMMAND_HANDLER(handle_etm_tracemode_command)
1251 {
1252 target_t *target = get_current_target(cmd_ctx);
1253 struct arm *arm = target_to_arm(target);
1254 struct etm *etm;
1255
1256 if (!is_arm(arm)) {
1257 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1258 return ERROR_FAIL;
1259 }
1260
1261 etm = arm->etm;
1262 if (!etm) {
1263 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1264 return ERROR_FAIL;
1265 }
1266
1267 etmv1_tracemode_t tracemode = etm->tracemode;
1268
1269 switch (argc)
1270 {
1271 case 0:
1272 break;
1273 case 4:
1274 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1275 break;
1276 default:
1277 command_print(cmd_ctx, "usage: configure trace mode "
1278 "<none | data | address | all> "
1279 "<context id bits> <cycle accurate> <branch output>");
1280 return ERROR_FAIL;
1281 }
1282
1283 /**
1284 * todo: fail if parameters were invalid for this hardware,
1285 * or couldn't be written; display actual hardware state...
1286 */
1287
1288 command_print(cmd_ctx, "current tracemode configuration:");
1289
1290 switch (tracemode & ETMV1_TRACE_MASK)
1291 {
1292 case ETMV1_TRACE_NONE:
1293 command_print(cmd_ctx, "data tracing: none");
1294 break;
1295 case ETMV1_TRACE_DATA:
1296 command_print(cmd_ctx, "data tracing: data only");
1297 break;
1298 case ETMV1_TRACE_ADDR:
1299 command_print(cmd_ctx, "data tracing: address only");
1300 break;
1301 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1302 command_print(cmd_ctx, "data tracing: address and data");
1303 break;
1304 }
1305
1306 switch (tracemode & ETMV1_CONTEXTID_MASK)
1307 {
1308 case ETMV1_CONTEXTID_NONE:
1309 command_print(cmd_ctx, "contextid tracing: none");
1310 break;
1311 case ETMV1_CONTEXTID_8:
1312 command_print(cmd_ctx, "contextid tracing: 8 bit");
1313 break;
1314 case ETMV1_CONTEXTID_16:
1315 command_print(cmd_ctx, "contextid tracing: 16 bit");
1316 break;
1317 case ETMV1_CONTEXTID_32:
1318 command_print(cmd_ctx, "contextid tracing: 32 bit");
1319 break;
1320 }
1321
1322 if (tracemode & ETMV1_CYCLE_ACCURATE)
1323 {
1324 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1325 }
1326 else
1327 {
1328 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1329 }
1330
1331 if (tracemode & ETMV1_BRANCH_OUTPUT)
1332 {
1333 command_print(cmd_ctx, "full branch address output enabled");
1334 }
1335 else
1336 {
1337 command_print(cmd_ctx, "full branch address output disabled");
1338 }
1339
1340 /* only update ETM_CTRL register if tracemode changed */
1341 if (etm->tracemode != tracemode)
1342 {
1343 reg_t *etm_ctrl_reg;
1344
1345 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1346 if (!etm_ctrl_reg)
1347 return ERROR_FAIL;
1348
1349 etm_get_reg(etm_ctrl_reg);
1350
1351 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1352 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1353 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1354 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1355 etm_store_reg(etm_ctrl_reg);
1356
1357 etm->tracemode = tracemode;
1358
1359 /* invalidate old trace data */
1360 etm->capture_status = TRACE_IDLE;
1361 if (etm->trace_depth > 0)
1362 {
1363 free(etm->trace_data);
1364 etm->trace_data = NULL;
1365 }
1366 etm->trace_depth = 0;
1367 }
1368
1369 return ERROR_OK;
1370 }
1371
1372 COMMAND_HANDLER(handle_etm_config_command)
1373 {
1374 target_t *target;
1375 struct arm *arm;
1376 etm_portmode_t portmode = 0x0;
1377 struct etm *etm_ctx;
1378 int i;
1379
1380 if (argc != 5)
1381 return ERROR_COMMAND_SYNTAX_ERROR;
1382
1383 target = get_target(args[0]);
1384 if (!target)
1385 {
1386 LOG_ERROR("target '%s' not defined", args[0]);
1387 return ERROR_FAIL;
1388 }
1389
1390 arm = target_to_arm(target);
1391 if (!is_arm(arm)) {
1392 command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
1393 target->cmd_name, target_get_name(target));
1394 return ERROR_FAIL;
1395 }
1396
1397 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1398 * version we'll be using!! -- so we can't know how to validate
1399 * params yet. "etm config" should likely be *AFTER* hookup...
1400 *
1401 * - Many more widths might be supported ... and we can easily
1402 * check whether our setting "took".
1403 *
1404 * - The "clock" and "mode" bits are interpreted differently.
1405 * See ARM IHI 0014O table 2-17 for the old behavior, and
1406 * table 2-18 for the new. With ETB it's best to specify
1407 * "normal full" ...
1408 */
1409 uint8_t port_width;
1410 COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1411 switch (port_width)
1412 {
1413 /* before ETMv3.0 */
1414 case 4:
1415 portmode |= ETM_PORT_4BIT;
1416 break;
1417 case 8:
1418 portmode |= ETM_PORT_8BIT;
1419 break;
1420 case 16:
1421 portmode |= ETM_PORT_16BIT;
1422 break;
1423 /* ETMv3.0 and later*/
1424 case 24:
1425 portmode |= ETM_PORT_24BIT;
1426 break;
1427 case 32:
1428 portmode |= ETM_PORT_32BIT;
1429 break;
1430 case 48:
1431 portmode |= ETM_PORT_48BIT;
1432 break;
1433 case 64:
1434 portmode |= ETM_PORT_64BIT;
1435 break;
1436 case 1:
1437 portmode |= ETM_PORT_1BIT;
1438 break;
1439 case 2:
1440 portmode |= ETM_PORT_2BIT;
1441 break;
1442 default:
1443 command_print(cmd_ctx,
1444 "unsupported ETM port width '%s'", args[1]);
1445 return ERROR_FAIL;
1446 }
1447
1448 if (strcmp("normal", args[2]) == 0)
1449 {
1450 portmode |= ETM_PORT_NORMAL;
1451 }
1452 else if (strcmp("multiplexed", args[2]) == 0)
1453 {
1454 portmode |= ETM_PORT_MUXED;
1455 }
1456 else if (strcmp("demultiplexed", args[2]) == 0)
1457 {
1458 portmode |= ETM_PORT_DEMUXED;
1459 }
1460 else
1461 {
1462 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1463 return ERROR_FAIL;
1464 }
1465
1466 if (strcmp("half", args[3]) == 0)
1467 {
1468 portmode |= ETM_PORT_HALF_CLOCK;
1469 }
1470 else if (strcmp("full", args[3]) == 0)
1471 {
1472 portmode |= ETM_PORT_FULL_CLOCK;
1473 }
1474 else
1475 {
1476 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1477 return ERROR_FAIL;
1478 }
1479
1480 etm_ctx = calloc(1, sizeof(etm_context_t));
1481 if (!etm_ctx) {
1482 LOG_DEBUG("out of memory");
1483 return ERROR_FAIL;
1484 }
1485
1486 for (i = 0; etm_capture_drivers[i]; i++)
1487 {
1488 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1489 {
1490 int retval;
1491 if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1492 {
1493 free(etm_ctx);
1494 return retval;
1495 }
1496
1497 etm_ctx->capture_driver = etm_capture_drivers[i];
1498
1499 break;
1500 }
1501 }
1502
1503 if (!etm_capture_drivers[i])
1504 {
1505 /* no supported capture driver found, don't register an ETM */
1506 free(etm_ctx);
1507 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1508 return ERROR_FAIL;
1509 }
1510
1511 etm_ctx->target = target;
1512 etm_ctx->trigger_percent = 50;
1513 etm_ctx->trace_data = NULL;
1514 etm_ctx->portmode = portmode;
1515 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1516
1517 arm->etm = etm_ctx;
1518
1519 return etm_register_user_commands(cmd_ctx);
1520 }
1521
1522 COMMAND_HANDLER(handle_etm_info_command)
1523 {
1524 target_t *target;
1525 struct arm *arm;
1526 etm_context_t *etm;
1527 reg_t *etm_sys_config_reg;
1528 int max_port_size;
1529 uint32_t config;
1530
1531 target = get_current_target(cmd_ctx);
1532 arm = target_to_arm(target);
1533 if (!is_arm(arm))
1534 {
1535 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1536 return ERROR_FAIL;
1537 }
1538
1539 etm = arm->etm;
1540 if (!etm)
1541 {
1542 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1543 return ERROR_FAIL;
1544 }
1545
1546 command_print(cmd_ctx, "ETM v%d.%d",
1547 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1548 command_print(cmd_ctx, "pairs of address comparators: %i",
1549 (int) (etm->config >> 0) & 0x0f);
1550 command_print(cmd_ctx, "data comparators: %i",
1551 (int) (etm->config >> 4) & 0x0f);
1552 command_print(cmd_ctx, "memory map decoders: %i",
1553 (int) (etm->config >> 8) & 0x1f);
1554 command_print(cmd_ctx, "number of counters: %i",
1555 (int) (etm->config >> 13) & 0x07);
1556 command_print(cmd_ctx, "sequencer %spresent",
1557 (int) (etm->config & (1 << 16)) ? "" : "not ");
1558 command_print(cmd_ctx, "number of ext. inputs: %i",
1559 (int) (etm->config >> 17) & 0x07);
1560 command_print(cmd_ctx, "number of ext. outputs: %i",
1561 (int) (etm->config >> 20) & 0x07);
1562 command_print(cmd_ctx, "FIFO full %spresent",
1563 (int) (etm->config & (1 << 23)) ? "" : "not ");
1564 if (etm->bcd_vers < 0x20)
1565 command_print(cmd_ctx, "protocol version: %i",
1566 (int) (etm->config >> 28) & 0x07);
1567 else {
1568 command_print(cmd_ctx,
1569 "coprocessor and memory access %ssupported",
1570 (etm->config & (1 << 26)) ? "" : "not ");
1571 command_print(cmd_ctx, "trace start/stop %spresent",
1572 (etm->config & (1 << 26)) ? "" : "not ");
1573 command_print(cmd_ctx, "number of context comparators: %i",
1574 (int) (etm->config >> 24) & 0x03);
1575 }
1576
1577 /* SYS_CONFIG isn't present before ETMv1.2 */
1578 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1579 if (!etm_sys_config_reg)
1580 return ERROR_OK;
1581
1582 etm_get_reg(etm_sys_config_reg);
1583 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1584
1585 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1586
1587 max_port_size = config & 0x7;
1588 if (etm->bcd_vers >= 0x30)
1589 max_port_size |= (config >> 6) & 0x08;
1590 switch (max_port_size)
1591 {
1592 /* before ETMv3.0 */
1593 case 0:
1594 max_port_size = 4;
1595 break;
1596 case 1:
1597 max_port_size = 8;
1598 break;
1599 case 2:
1600 max_port_size = 16;
1601 break;
1602 /* ETMv3.0 and later*/
1603 case 3:
1604 max_port_size = 24;
1605 break;
1606 case 4:
1607 max_port_size = 32;
1608 break;
1609 case 5:
1610 max_port_size = 48;
1611 break;
1612 case 6:
1613 max_port_size = 64;
1614 break;
1615 case 8:
1616 max_port_size = 1;
1617 break;
1618 case 9:
1619 max_port_size = 2;
1620 break;
1621 default:
1622 LOG_ERROR("Illegal max_port_size");
1623 return ERROR_FAIL;
1624 }
1625 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1626
1627 if (etm->bcd_vers < 0x30) {
1628 command_print(cmd_ctx, "half-rate clocking %ssupported",
1629 (config & (1 << 3)) ? "" : "not ");
1630 command_print(cmd_ctx, "full-rate clocking %ssupported",
1631 (config & (1 << 4)) ? "" : "not ");
1632 command_print(cmd_ctx, "normal trace format %ssupported",
1633 (config & (1 << 5)) ? "" : "not ");
1634 command_print(cmd_ctx, "multiplex trace format %ssupported",
1635 (config & (1 << 6)) ? "" : "not ");
1636 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1637 (config & (1 << 7)) ? "" : "not ");
1638 } else {
1639 /* REVISIT show which size and format are selected ... */
1640 command_print(cmd_ctx, "current port size %ssupported",
1641 (config & (1 << 10)) ? "" : "not ");
1642 command_print(cmd_ctx, "current trace format %ssupported",
1643 (config & (1 << 11)) ? "" : "not ");
1644 }
1645 if (etm->bcd_vers >= 0x21)
1646 command_print(cmd_ctx, "fetch comparisons %ssupported",
1647 (config & (1 << 17)) ? "not " : "");
1648 command_print(cmd_ctx, "FIFO full %ssupported",
1649 (config & (1 << 8)) ? "" : "not ");
1650
1651 return ERROR_OK;
1652 }
1653
1654 COMMAND_HANDLER(handle_etm_status_command)
1655 {
1656 target_t *target;
1657 struct arm *arm;
1658 etm_context_t *etm;
1659 trace_status_t trace_status;
1660
1661 target = get_current_target(cmd_ctx);
1662 arm = target_to_arm(target);
1663 if (!is_arm(arm))
1664 {
1665 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1666 return ERROR_FAIL;
1667 }
1668
1669 etm = arm->etm;
1670 if (!etm)
1671 {
1672 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1673 return ERROR_FAIL;
1674 }
1675
1676 /* ETM status */
1677 if (etm->bcd_vers >= 0x11) {
1678 reg_t *reg;
1679
1680 reg = etm_reg_lookup(etm, ETM_STATUS);
1681 if (!reg)
1682 return ERROR_FAIL;
1683 if (etm_get_reg(reg) == ERROR_OK) {
1684 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1685
1686 command_print(cmd_ctx, "etm: %s%s%s%s",
1687 /* bit(1) == progbit */
1688 (etm->bcd_vers >= 0x12)
1689 ? ((s & (1 << 1))
1690 ? "disabled" : "enabled")
1691 : "?",
1692 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1693 ? " triggered" : "",
1694 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1695 ? " start/stop" : "",
1696 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1697 ? " untraced-overflow" : "");
1698 } /* else ignore and try showing trace port status */
1699 }
1700
1701 /* Trace Port Driver status */
1702 trace_status = etm->capture_driver->status(etm);
1703 if (trace_status == TRACE_IDLE)
1704 {
1705 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1706 }
1707 else
1708 {
1709 static char *completed = " completed";
1710 static char *running = " is running";
1711 static char *overflowed = ", overflowed";
1712 static char *triggered = ", triggered";
1713
1714 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1715 etm->capture_driver->name,
1716 (trace_status & TRACE_RUNNING) ? running : completed,
1717 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1718 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1719
1720 if (etm->trace_depth > 0)
1721 {
1722 command_print(cmd_ctx, "%i frames of trace data read",
1723 (int)(etm->trace_depth));
1724 }
1725 }
1726
1727 return ERROR_OK;
1728 }
1729
1730 COMMAND_HANDLER(handle_etm_image_command)
1731 {
1732 target_t *target;
1733 struct arm *arm;
1734 etm_context_t *etm_ctx;
1735
1736 if (argc < 1)
1737 {
1738 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1739 return ERROR_FAIL;
1740 }
1741
1742 target = get_current_target(cmd_ctx);
1743 arm = target_to_arm(target);
1744 if (!is_arm(arm))
1745 {
1746 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1747 return ERROR_FAIL;
1748 }
1749
1750 etm_ctx = arm->etm;
1751 if (!etm_ctx)
1752 {
1753 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1754 return ERROR_FAIL;
1755 }
1756
1757 if (etm_ctx->image)
1758 {
1759 image_close(etm_ctx->image);
1760 free(etm_ctx->image);
1761 command_print(cmd_ctx, "previously loaded image found and closed");
1762 }
1763
1764 etm_ctx->image = malloc(sizeof(image_t));
1765 etm_ctx->image->base_address_set = 0;
1766 etm_ctx->image->start_address_set = 0;
1767
1768 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1769 if (argc >= 2)
1770 {
1771 etm_ctx->image->base_address_set = 1;
1772 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1773 }
1774 else
1775 {
1776 etm_ctx->image->base_address_set = 0;
1777 }
1778
1779 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1780 {
1781 free(etm_ctx->image);
1782 etm_ctx->image = NULL;
1783 return ERROR_FAIL;
1784 }
1785
1786 return ERROR_OK;
1787 }
1788
1789 COMMAND_HANDLER(handle_etm_dump_command)
1790 {
1791 struct fileio file;
1792 target_t *target;
1793 struct arm *arm;
1794 etm_context_t *etm_ctx;
1795 uint32_t i;
1796
1797 if (argc != 1)
1798 {
1799 command_print(cmd_ctx, "usage: etm dump <file>");
1800 return ERROR_FAIL;
1801 }
1802
1803 target = get_current_target(cmd_ctx);
1804 arm = target_to_arm(target);
1805 if (!is_arm(arm))
1806 {
1807 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1808 return ERROR_FAIL;
1809 }
1810
1811 etm_ctx = arm->etm;
1812 if (!etm_ctx)
1813 {
1814 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1815 return ERROR_FAIL;
1816 }
1817
1818 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1819 {
1820 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1821 return ERROR_OK;
1822 }
1823
1824 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1825 {
1826 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1827 command_print(cmd_ctx, "trace capture not completed");
1828 return ERROR_FAIL;
1829 }
1830
1831 /* read the trace data if it wasn't read already */
1832 if (etm_ctx->trace_depth == 0)
1833 etm_ctx->capture_driver->read_trace(etm_ctx);
1834
1835 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1836 {
1837 return ERROR_FAIL;
1838 }
1839
1840 fileio_write_u32(&file, etm_ctx->capture_status);
1841 fileio_write_u32(&file, etm_ctx->portmode);
1842 fileio_write_u32(&file, etm_ctx->tracemode);
1843 fileio_write_u32(&file, etm_ctx->trace_depth);
1844
1845 for (i = 0; i < etm_ctx->trace_depth; i++)
1846 {
1847 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1848 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1849 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1850 }
1851
1852 fileio_close(&file);
1853
1854 return ERROR_OK;
1855 }
1856
1857 COMMAND_HANDLER(handle_etm_load_command)
1858 {
1859 struct fileio file;
1860 target_t *target;
1861 struct arm *arm;
1862 etm_context_t *etm_ctx;
1863 uint32_t i;
1864
1865 if (argc != 1)
1866 {
1867 command_print(cmd_ctx, "usage: etm load <file>");
1868 return ERROR_FAIL;
1869 }
1870
1871 target = get_current_target(cmd_ctx);
1872 arm = target_to_arm(target);
1873 if (!is_arm(arm))
1874 {
1875 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1876 return ERROR_FAIL;
1877 }
1878
1879 etm_ctx = arm->etm;
1880 if (!etm_ctx)
1881 {
1882 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1883 return ERROR_FAIL;
1884 }
1885
1886 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1887 {
1888 command_print(cmd_ctx, "trace capture running, stop first");
1889 return ERROR_FAIL;
1890 }
1891
1892 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1893 {
1894 return ERROR_FAIL;
1895 }
1896
1897 if (file.size % 4)
1898 {
1899 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1900 fileio_close(&file);
1901 return ERROR_FAIL;
1902 }
1903
1904 if (etm_ctx->trace_depth > 0)
1905 {
1906 free(etm_ctx->trace_data);
1907 etm_ctx->trace_data = NULL;
1908 }
1909
1910 {
1911 uint32_t tmp;
1912 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1913 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1914 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1915 fileio_read_u32(&file, &etm_ctx->trace_depth);
1916 }
1917 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1918 if (etm_ctx->trace_data == NULL)
1919 {
1920 command_print(cmd_ctx, "not enough memory to perform operation");
1921 fileio_close(&file);
1922 return ERROR_FAIL;
1923 }
1924
1925 for (i = 0; i < etm_ctx->trace_depth; i++)
1926 {
1927 uint32_t pipestat, packet, flags;
1928 fileio_read_u32(&file, &pipestat);
1929 fileio_read_u32(&file, &packet);
1930 fileio_read_u32(&file, &flags);
1931 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1932 etm_ctx->trace_data[i].packet = packet & 0xffff;
1933 etm_ctx->trace_data[i].flags = flags;
1934 }
1935
1936 fileio_close(&file);
1937
1938 return ERROR_OK;
1939 }
1940
1941 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1942 {
1943 target_t *target;
1944 struct arm *arm;
1945 etm_context_t *etm_ctx;
1946
1947 target = get_current_target(cmd_ctx);
1948 arm = target_to_arm(target);
1949 if (!is_arm(arm))
1950 {
1951 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1952 return ERROR_FAIL;
1953 }
1954
1955 etm_ctx = arm->etm;
1956 if (!etm_ctx)
1957 {
1958 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1959 return ERROR_FAIL;
1960 }
1961
1962 if (argc > 0)
1963 {
1964 uint32_t new_value;
1965 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1966
1967 if ((new_value < 2) || (new_value > 100))
1968 {
1969 command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1970 }
1971 else
1972 {
1973 etm_ctx->trigger_percent = new_value;
1974 }
1975 }
1976
1977 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1978
1979 return ERROR_OK;
1980 }
1981
1982 COMMAND_HANDLER(handle_etm_start_command)
1983 {
1984 target_t *target;
1985 struct arm *arm;
1986 etm_context_t *etm_ctx;
1987 reg_t *etm_ctrl_reg;
1988
1989 target = get_current_target(cmd_ctx);
1990 arm = target_to_arm(target);
1991 if (!is_arm(arm))
1992 {
1993 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1994 return ERROR_FAIL;
1995 }
1996
1997 etm_ctx = arm->etm;
1998 if (!etm_ctx)
1999 {
2000 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2001 return ERROR_FAIL;
2002 }
2003
2004 /* invalidate old tracing data */
2005 etm_ctx->capture_status = TRACE_IDLE;
2006 if (etm_ctx->trace_depth > 0)
2007 {
2008 free(etm_ctx->trace_data);
2009 etm_ctx->trace_data = NULL;
2010 }
2011 etm_ctx->trace_depth = 0;
2012
2013 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2014 if (!etm_ctrl_reg)
2015 return ERROR_FAIL;
2016
2017 etm_get_reg(etm_ctrl_reg);
2018
2019 /* Clear programming bit (10), set port selection bit (11) */
2020 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2021
2022 etm_store_reg(etm_ctrl_reg);
2023 jtag_execute_queue();
2024
2025 etm_ctx->capture_driver->start_capture(etm_ctx);
2026
2027 return ERROR_OK;
2028 }
2029
2030 COMMAND_HANDLER(handle_etm_stop_command)
2031 {
2032 target_t *target;
2033 struct arm *arm;
2034 etm_context_t *etm_ctx;
2035 reg_t *etm_ctrl_reg;
2036
2037 target = get_current_target(cmd_ctx);
2038 arm = target_to_arm(target);
2039 if (!is_arm(arm))
2040 {
2041 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2042 return ERROR_FAIL;
2043 }
2044
2045 etm_ctx = arm->etm;
2046 if (!etm_ctx)
2047 {
2048 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2049 return ERROR_FAIL;
2050 }
2051
2052 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2053 if (!etm_ctrl_reg)
2054 return ERROR_FAIL;
2055
2056 etm_get_reg(etm_ctrl_reg);
2057
2058 /* Set programming bit (10), clear port selection bit (11) */
2059 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2060
2061 etm_store_reg(etm_ctrl_reg);
2062 jtag_execute_queue();
2063
2064 etm_ctx->capture_driver->stop_capture(etm_ctx);
2065
2066 return ERROR_OK;
2067 }
2068
2069 COMMAND_HANDLER(handle_etm_analyze_command)
2070 {
2071 target_t *target;
2072 struct arm *arm;
2073 etm_context_t *etm_ctx;
2074 int retval;
2075
2076 target = get_current_target(cmd_ctx);
2077 arm = target_to_arm(target);
2078 if (!is_arm(arm))
2079 {
2080 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2081 return ERROR_FAIL;
2082 }
2083
2084 etm_ctx = arm->etm;
2085 if (!etm_ctx)
2086 {
2087 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2088 return ERROR_FAIL;
2089 }
2090
2091 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2092 {
2093 switch (retval)
2094 {
2095 case ERROR_ETM_ANALYSIS_FAILED:
2096 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2097 break;
2098 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2099 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2100 break;
2101 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2102 command_print(cmd_ctx, "no image available for trace analysis");
2103 break;
2104 default:
2105 command_print(cmd_ctx, "unknown error: %i", retval);
2106 }
2107 }
2108
2109 return retval;
2110 }
2111
2112 int etm_register_commands(struct command_context_s *cmd_ctx)
2113 {
2114 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2115
2116 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2117 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2118
2119 return ERROR_OK;
2120 }
2121
2122 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2123 {
2124 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2125 COMMAND_EXEC, "configure/display trace mode: "
2126 "<none | data | address | all> "
2127 "<context_id_bits> <cycle_accurate> <branch_output>");
2128
2129 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2130 COMMAND_EXEC, "display info about the current target's ETM");
2131
2132 register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2133 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2134 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2135 COMMAND_EXEC, "display current target's ETM status");
2136 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2137 COMMAND_EXEC, "start ETM trace collection");
2138 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2139 COMMAND_EXEC, "stop ETM trace collection");
2140
2141 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2142 COMMAND_EXEC, "anaylze collected ETM trace");
2143
2144 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2145 COMMAND_EXEC, "load image from <file> [base address]");
2146
2147 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2148 COMMAND_EXEC, "dump captured trace data <file>");
2149 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2150 COMMAND_EXEC, "load trace data for analysis <file>");
2151
2152 return ERROR_OK;
2153 }
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