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Start cleaning up ETM register handling. On one ARM926 ETM+ETB
[openocd.git] / src / target / etm.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "etm.h"
25 #include "etb.h"
26 #include "image.h"
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
29
30
31 /*
32 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
33 *
34 * ETM modules collect instruction and/or data trace information, compress
35 * it, and transfer it to a debugging host through either a (buffered) trace
36 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
37 *
38 * There are several generations of these modules. Original versions have
39 * JTAG access through a dedicated scan chain. Recent versions have added
40 * access via coprocessor instructions, memory addressing, and the ARM Debug
41 * Interface v5 (ADIv5); and phased out direct JTAG access.
42 *
43 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
44 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
45 * implying non-JTAG connectivity options.
46 *
47 * Relevant documentation includes:
48 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
49 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
50 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
51 */
52
53 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
54
55 enum {
56 RO, /* read/only */
57 WO, /* write/only */
58 RW, /* read/write */
59 };
60
61 struct etm_reg_info {
62 uint8_t addr;
63 uint8_t size; /* low-N of 32 bits */
64 uint8_t mode; /* RO, WO, RW */
65 uint8_t bcd_vers; /* 1.0, 2.0, etc */
66 char *name;
67 };
68
69 /*
70 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
73 */
74 static const struct etm_reg_info reg[] = {
75 /* ETM Trace Registers */
76 { ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
77 { ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
78 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
79 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_ASIC_CTRL", },
80 { ETM_STATUS, 3, RO, 0x11, "ETM_STATUS", },
81 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_SYS_CONFIG", },
82
83 /* TraceEnable configuration */
84 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
85 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
86 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
87 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
88
89 /* FIFOFULL configuration */
90 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
91 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
92
93 /* ViewData configuration (data trace) */
94 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
95 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
96 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
97 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
98
99 /* Address comparator register pairs */
100 #define ADDR_COMPARATOR(i) \
101 { ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
102 "ETM_ADDR_COMPARATOR_VALUE" #i, }, \
103 { ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
104 "ETM_ADDR_ACCESS_TYPE" #i, }
105 ADDR_COMPARATOR(0),
106 ADDR_COMPARATOR(1),
107 ADDR_COMPARATOR(2),
108 ADDR_COMPARATOR(3),
109 ADDR_COMPARATOR(4),
110 ADDR_COMPARATOR(5),
111 ADDR_COMPARATOR(6),
112 ADDR_COMPARATOR(7),
113
114 ADDR_COMPARATOR(8),
115 ADDR_COMPARATOR(9),
116 ADDR_COMPARATOR(10),
117 ADDR_COMPARATOR(11),
118 ADDR_COMPARATOR(12),
119 ADDR_COMPARATOR(13),
120 ADDR_COMPARATOR(14),
121 ADDR_COMPARATOR(15),
122 #undef ADDR_COMPARATOR
123
124 /* Data Value Comparators (NOTE: odd addresses are reserved) */
125 #define DATA_COMPARATOR(i) \
126 { ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
127 "ETM_DATA_COMPARATOR_VALUE" #i, }, \
128 { ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
129 "ETM_DATA_COMPARATOR_MASK" #i, }
130 DATA_COMPARATOR(0),
131 DATA_COMPARATOR(1),
132 DATA_COMPARATOR(2),
133 DATA_COMPARATOR(3),
134 DATA_COMPARATOR(4),
135 DATA_COMPARATOR(5),
136 DATA_COMPARATOR(6),
137 DATA_COMPARATOR(7),
138 #undef DATA_COMPARATOR
139
140 /* Counters */
141 #define COUNTER(i) \
142 { ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
143 "ETM_COUNTER_RELOAD_VALUE" #i, }, \
144 { ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
145 "ETM_COUNTER_ENABLE" #i, }, \
146 { ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
147 "ETM_COUNTER_RELOAD_EVENT" #i, }, \
148 { ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
149 "ETM_COUNTER_VALUE" #i, }
150 COUNTER(0),
151 COUNTER(1),
152 COUNTER(2),
153 COUNTER(3),
154 #undef COUNTER
155
156 /* Sequencers */
157 #define SEQ(i) \
158 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
159 "ETM_SEQUENCER_EVENT" #i, }
160 SEQ(0), /* 1->2 */
161 SEQ(1), /* 2->1 */
162 SEQ(2), /* 2->3 */
163 SEQ(3), /* 3->1 */
164 SEQ(4), /* 3->2 */
165 SEQ(5), /* 1->3 */
166 #undef SEQ
167 /* 0x66 reserved */
168 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_SEQUENCER_STATE", },
169
170 #define OUT(i) \
171 { ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
172 "ETM_EXTERNAL_OUTPUT" #i, }
173
174 OUT(0),
175 OUT(1),
176 OUT(2),
177 OUT(3),
178 #undef OUT
179
180 #if 0
181 /* registers from 0x6c..0x7f were added after ETMv1.3 */
182
183 /* Context ID Comparators */
184 { 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
185 { 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
186 { 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
187 { 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
188
189 { 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
190 { 0x79, 32, RO, 0x20, "ETM_ID", },
191 #endif
192 };
193
194 static int etm_reg_arch_type = -1;
195
196 static int etm_get_reg(reg_t *reg);
197 static int etm_read_reg_w_check(reg_t *reg,
198 uint8_t* check_value, uint8_t* check_mask);
199 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
200 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
201 static int etm_write_reg(reg_t *reg, uint32_t value);
202
203 static command_t *etm_cmd;
204
205
206 /* Look up register by ID ... most ETM instances only
207 * support a subset of the possible registers.
208 */
209 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
210 {
211 reg_cache_t *cache = etm_ctx->reg_cache;
212 int i;
213
214 for (i = 0; i < cache->num_regs; i++) {
215 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
216
217 if (reg->reg_info->addr == id)
218 return &cache->reg_list[i];
219 }
220
221 /* caller asking for nonexistent register is a bug! */
222 /* REVISIT say which of the N targets was involved */
223 LOG_ERROR("ETM: register 0x%02x not available", id);
224 return NULL;
225 }
226
227 reg_cache_t *etm_build_reg_cache(target_t *target,
228 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
229 {
230 reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
231 reg_t *reg_list = NULL;
232 etm_reg_t *arch_info = NULL;
233 int num_regs = ARRAY_SIZE(reg);
234 int i;
235
236 /* register a register arch-type for etm registers only once */
237 if (etm_reg_arch_type == -1)
238 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
239
240 /* the actual registers are kept in two arrays */
241 reg_list = calloc(num_regs, sizeof(reg_t));
242 arch_info = calloc(num_regs, sizeof(etm_reg_t));
243
244 /* fill in values for the reg cache */
245 reg_cache->name = "etm registers";
246 reg_cache->next = NULL;
247 reg_cache->reg_list = reg_list;
248 reg_cache->num_regs = num_regs;
249
250 /* set up registers */
251 for (i = 0; i < num_regs; i++)
252 {
253 const struct etm_reg_info *r = reg + i;
254
255 reg_list[i].name = r->name;
256 reg_list[i].size = r->size;
257 reg_list[i].value = &arch_info[i].value;
258 reg_list[i].arch_info = &arch_info[i];
259 reg_list[i].arch_type = etm_reg_arch_type;
260
261 arch_info[i].reg_info = r;
262 arch_info[i].jtag_info = jtag_info;
263 }
264
265 /* the ETM might have an ETB connected */
266 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
267 {
268 etb_t *etb = etm_ctx->capture_driver_priv;
269
270 if (!etb)
271 {
272 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
273 free(reg_cache);
274 free(arch_info);
275 return ERROR_OK;
276 }
277
278 reg_cache->next = etb_build_reg_cache(etb);
279
280 etb->reg_cache = reg_cache->next;
281 }
282
283
284 return reg_cache;
285 }
286
287 static int etm_read_reg(reg_t *reg)
288 {
289 return etm_read_reg_w_check(reg, NULL, NULL);
290 }
291
292 static int etm_store_reg(reg_t *reg)
293 {
294 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
295 }
296
297 int etm_setup(target_t *target)
298 {
299 int retval;
300 uint32_t etm_ctrl_value;
301 armv4_5_common_t *armv4_5 = target->arch_info;
302 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
303 etm_context_t *etm_ctx = arm7_9->etm_ctx;
304 reg_t *etm_ctrl_reg;
305
306 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
307 if (!etm_ctrl_reg)
308 return ERROR_OK;
309
310 /* initialize some ETM control register settings */
311 etm_get_reg(etm_ctrl_reg);
312 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
313
314 /* clear the ETM powerdown bit (0) */
315 etm_ctrl_value &= ~0x1;
316
317 /* configure port width (6:4), mode (17:16) and clocking (13) */
318 etm_ctrl_value = (etm_ctrl_value &
319 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
320 | etm_ctx->portmode;
321
322 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
323 etm_store_reg(etm_ctrl_reg);
324
325 if ((retval = jtag_execute_queue()) != ERROR_OK)
326 return retval;
327
328 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
329 {
330 LOG_ERROR("ETM capture driver initialization failed");
331 return retval;
332 }
333 return ERROR_OK;
334 }
335
336 static int etm_get_reg(reg_t *reg)
337 {
338 int retval;
339
340 if ((retval = etm_read_reg(reg)) != ERROR_OK)
341 {
342 LOG_ERROR("BUG: error scheduling etm register read");
343 return retval;
344 }
345
346 if ((retval = jtag_execute_queue()) != ERROR_OK)
347 {
348 LOG_ERROR("register read failed");
349 return retval;
350 }
351
352 return ERROR_OK;
353 }
354
355 static int etm_read_reg_w_check(reg_t *reg,
356 uint8_t* check_value, uint8_t* check_mask)
357 {
358 etm_reg_t *etm_reg = reg->arch_info;
359 const struct etm_reg_info *r = etm_reg->reg_info;
360 uint8_t reg_addr = r->addr & 0x7f;
361 scan_field_t fields[3];
362
363 if (etm_reg->reg_info->mode == WO) {
364 LOG_ERROR("BUG: can't read write-only register %s", r->name);
365 return ERROR_INVALID_ARGUMENTS;
366 }
367
368 LOG_DEBUG("%s (%u)", r->name, reg_addr);
369
370 jtag_set_end_state(TAP_IDLE);
371 arm_jtag_scann(etm_reg->jtag_info, 0x6);
372 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
373
374 fields[0].tap = etm_reg->jtag_info->tap;
375 fields[0].num_bits = 32;
376 fields[0].out_value = reg->value;
377 fields[0].in_value = NULL;
378 fields[0].check_value = NULL;
379 fields[0].check_mask = NULL;
380
381 fields[1].tap = etm_reg->jtag_info->tap;
382 fields[1].num_bits = 7;
383 fields[1].out_value = malloc(1);
384 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
385 fields[1].in_value = NULL;
386 fields[1].check_value = NULL;
387 fields[1].check_mask = NULL;
388
389 fields[2].tap = etm_reg->jtag_info->tap;
390 fields[2].num_bits = 1;
391 fields[2].out_value = malloc(1);
392 buf_set_u32(fields[2].out_value, 0, 1, 0);
393 fields[2].in_value = NULL;
394 fields[2].check_value = NULL;
395 fields[2].check_mask = NULL;
396
397 jtag_add_dr_scan(3, fields, jtag_get_end_state());
398
399 fields[0].in_value = reg->value;
400 fields[0].check_value = check_value;
401 fields[0].check_mask = check_mask;
402
403 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
404
405 free(fields[1].out_value);
406 free(fields[2].out_value);
407
408 return ERROR_OK;
409 }
410
411 static int etm_set_reg(reg_t *reg, uint32_t value)
412 {
413 int retval;
414
415 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
416 {
417 LOG_ERROR("BUG: error scheduling etm register write");
418 return retval;
419 }
420
421 buf_set_u32(reg->value, 0, reg->size, value);
422 reg->valid = 1;
423 reg->dirty = 0;
424
425 return ERROR_OK;
426 }
427
428 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
429 {
430 int retval;
431
432 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
433
434 if ((retval = jtag_execute_queue()) != ERROR_OK)
435 {
436 LOG_ERROR("register write failed");
437 return retval;
438 }
439 return ERROR_OK;
440 }
441
442 static int etm_write_reg(reg_t *reg, uint32_t value)
443 {
444 etm_reg_t *etm_reg = reg->arch_info;
445 const struct etm_reg_info *r = etm_reg->reg_info;
446 uint8_t reg_addr = r->addr & 0x7f;
447 scan_field_t fields[3];
448
449 if (etm_reg->reg_info->mode == RO) {
450 LOG_ERROR("BUG: can't write read--only register %s", r->name);
451 return ERROR_INVALID_ARGUMENTS;
452 }
453
454 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
455
456 jtag_set_end_state(TAP_IDLE);
457 arm_jtag_scann(etm_reg->jtag_info, 0x6);
458 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
459
460 fields[0].tap = etm_reg->jtag_info->tap;
461 fields[0].num_bits = 32;
462 uint8_t tmp1[4];
463 fields[0].out_value = tmp1;
464 buf_set_u32(fields[0].out_value, 0, 32, value);
465 fields[0].in_value = NULL;
466
467 fields[1].tap = etm_reg->jtag_info->tap;
468 fields[1].num_bits = 7;
469 uint8_t tmp2;
470 fields[1].out_value = &tmp2;
471 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
472 fields[1].in_value = NULL;
473
474 fields[2].tap = etm_reg->jtag_info->tap;
475 fields[2].num_bits = 1;
476 uint8_t tmp3;
477 fields[2].out_value = &tmp3;
478 buf_set_u32(fields[2].out_value, 0, 1, 1);
479 fields[2].in_value = NULL;
480
481 jtag_add_dr_scan(3, fields, jtag_get_end_state());
482
483 return ERROR_OK;
484 }
485
486
487 /* ETM trace analysis functionality
488 *
489 */
490 extern etm_capture_driver_t etm_dummy_capture_driver;
491 #if BUILD_OOCD_TRACE == 1
492 extern etm_capture_driver_t oocd_trace_capture_driver;
493 #endif
494
495 static etm_capture_driver_t *etm_capture_drivers[] =
496 {
497 &etb_capture_driver,
498 &etm_dummy_capture_driver,
499 #if BUILD_OOCD_TRACE == 1
500 &oocd_trace_capture_driver,
501 #endif
502 NULL
503 };
504
505 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
506 {
507 int i;
508 int section = -1;
509 uint32_t size_read;
510 uint32_t opcode;
511 int retval;
512
513 if (!ctx->image)
514 return ERROR_TRACE_IMAGE_UNAVAILABLE;
515
516 /* search for the section the current instruction belongs to */
517 for (i = 0; i < ctx->image->num_sections; i++)
518 {
519 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
520 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
521 {
522 section = i;
523 break;
524 }
525 }
526
527 if (section == -1)
528 {
529 /* current instruction couldn't be found in the image */
530 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
531 }
532
533 if (ctx->core_state == ARMV4_5_STATE_ARM)
534 {
535 uint8_t buf[4];
536 if ((retval = image_read_section(ctx->image, section,
537 ctx->current_pc - ctx->image->sections[section].base_address,
538 4, buf, &size_read)) != ERROR_OK)
539 {
540 LOG_ERROR("error while reading instruction: %i", retval);
541 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
542 }
543 opcode = target_buffer_get_u32(ctx->target, buf);
544 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
545 }
546 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
547 {
548 uint8_t buf[2];
549 if ((retval = image_read_section(ctx->image, section,
550 ctx->current_pc - ctx->image->sections[section].base_address,
551 2, buf, &size_read)) != ERROR_OK)
552 {
553 LOG_ERROR("error while reading instruction: %i", retval);
554 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
555 }
556 opcode = target_buffer_get_u16(ctx->target, buf);
557 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
558 }
559 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
560 {
561 LOG_ERROR("BUG: tracing of jazelle code not supported");
562 exit(-1);
563 }
564 else
565 {
566 LOG_ERROR("BUG: unknown core state encountered");
567 exit(-1);
568 }
569
570 return ERROR_OK;
571 }
572
573 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
574 {
575 while (ctx->data_index < ctx->trace_depth)
576 {
577 /* if the caller specified an address packet offset, skip until the
578 * we reach the n-th cycle marked with tracesync */
579 if (apo > 0)
580 {
581 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
582 apo--;
583
584 if (apo > 0)
585 {
586 ctx->data_index++;
587 ctx->data_half = 0;
588 }
589 continue;
590 }
591
592 /* no tracedata output during a TD cycle
593 * or in a trigger cycle */
594 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
595 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
596 {
597 ctx->data_index++;
598 ctx->data_half = 0;
599 continue;
600 }
601
602 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
603 {
604 if (ctx->data_half == 0)
605 {
606 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
607 ctx->data_half = 1;
608 }
609 else
610 {
611 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
612 ctx->data_half = 0;
613 ctx->data_index++;
614 }
615 }
616 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
617 {
618 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
619 ctx->data_index++;
620 }
621 else
622 {
623 /* on a 4-bit port, a packet will be output during two consecutive cycles */
624 if (ctx->data_index > (ctx->trace_depth - 2))
625 return -1;
626
627 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
628 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
629 ctx->data_index += 2;
630 }
631
632 return 0;
633 }
634
635 return -1;
636 }
637
638 static int etmv1_branch_address(etm_context_t *ctx)
639 {
640 int retval;
641 uint8_t packet;
642 int shift = 0;
643 int apo;
644 uint32_t i;
645
646 /* quit analysis if less than two cycles are left in the trace
647 * because we can't extract the APO */
648 if (ctx->data_index > (ctx->trace_depth - 2))
649 return -1;
650
651 /* a BE could be output during an APO cycle, skip the current
652 * and continue with the new one */
653 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
654 return 1;
655 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
656 return 2;
657
658 /* address packet offset encoded in the next two cycles' pipestat bits */
659 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
660 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
661
662 /* count number of tracesync cycles between current pipe_index and data_index
663 * i.e. the number of tracesyncs that data_index already passed by
664 * to subtract them from the APO */
665 for (i = ctx->pipe_index; i < ctx->data_index; i++)
666 {
667 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
668 apo--;
669 }
670
671 /* extract up to four 7-bit packets */
672 do {
673 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
674 return -1;
675 ctx->last_branch &= ~(0x7f << shift);
676 ctx->last_branch |= (packet & 0x7f) << shift;
677 shift += 7;
678 } while ((packet & 0x80) && (shift < 28));
679
680 /* one last packet holding 4 bits of the address, plus the branch reason code */
681 if ((shift == 28) && (packet & 0x80))
682 {
683 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
684 return -1;
685 ctx->last_branch &= 0x0fffffff;
686 ctx->last_branch |= (packet & 0x0f) << 28;
687 ctx->last_branch_reason = (packet & 0x70) >> 4;
688 shift += 4;
689 }
690 else
691 {
692 ctx->last_branch_reason = 0;
693 }
694
695 if (shift == 32)
696 {
697 ctx->pc_ok = 1;
698 }
699
700 /* if a full address was output, we might have branched into Jazelle state */
701 if ((shift == 32) && (packet & 0x80))
702 {
703 ctx->core_state = ARMV4_5_STATE_JAZELLE;
704 }
705 else
706 {
707 /* if we didn't branch into Jazelle state, the current processor state is
708 * encoded in bit 0 of the branch target address */
709 if (ctx->last_branch & 0x1)
710 {
711 ctx->core_state = ARMV4_5_STATE_THUMB;
712 ctx->last_branch &= ~0x1;
713 }
714 else
715 {
716 ctx->core_state = ARMV4_5_STATE_ARM;
717 ctx->last_branch &= ~0x3;
718 }
719 }
720
721 return 0;
722 }
723
724 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
725 {
726 int j;
727 uint8_t buf[4];
728 int retval;
729
730 for (j = 0; j < size; j++)
731 {
732 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
733 return -1;
734 }
735
736 if (size == 8)
737 {
738 LOG_ERROR("TODO: add support for 64-bit values");
739 return -1;
740 }
741 else if (size == 4)
742 *data = target_buffer_get_u32(ctx->target, buf);
743 else if (size == 2)
744 *data = target_buffer_get_u16(ctx->target, buf);
745 else if (size == 1)
746 *data = buf[0];
747 else
748 return -1;
749
750 return 0;
751 }
752
753 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
754 {
755 int retval;
756 arm_instruction_t instruction;
757
758 /* read the trace data if it wasn't read already */
759 if (ctx->trace_depth == 0)
760 ctx->capture_driver->read_trace(ctx);
761
762 /* start at the beginning of the captured trace */
763 ctx->pipe_index = 0;
764 ctx->data_index = 0;
765 ctx->data_half = 0;
766
767 /* neither the PC nor the data pointer are valid */
768 ctx->pc_ok = 0;
769 ctx->ptr_ok = 0;
770
771 while (ctx->pipe_index < ctx->trace_depth)
772 {
773 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
774 uint32_t next_pc = ctx->current_pc;
775 uint32_t old_data_index = ctx->data_index;
776 uint32_t old_data_half = ctx->data_half;
777 uint32_t old_index = ctx->pipe_index;
778 uint32_t last_instruction = ctx->last_instruction;
779 uint32_t cycles = 0;
780 int current_pc_ok = ctx->pc_ok;
781
782 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
783 {
784 command_print(cmd_ctx, "--- trigger ---");
785 }
786
787 /* instructions execute in IE/D or BE/D cycles */
788 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
789 ctx->last_instruction = ctx->pipe_index;
790
791 /* if we don't have a valid pc skip until we reach an indirect branch */
792 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
793 {
794 ctx->pipe_index++;
795 continue;
796 }
797
798 /* any indirect branch could have interrupted instruction flow
799 * - the branch reason code could indicate a trace discontinuity
800 * - a branch to the exception vectors indicates an exception
801 */
802 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
803 {
804 /* backup current data index, to be able to consume the branch address
805 * before examining data address and values
806 */
807 old_data_index = ctx->data_index;
808 old_data_half = ctx->data_half;
809
810 ctx->last_instruction = ctx->pipe_index;
811
812 if ((retval = etmv1_branch_address(ctx)) != 0)
813 {
814 /* negative return value from etmv1_branch_address means we ran out of packets,
815 * quit analysing the trace */
816 if (retval < 0)
817 break;
818
819 /* a positive return values means the current branch was abandoned,
820 * and a new branch was encountered in cycle ctx->pipe_index + retval;
821 */
822 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
823 ctx->pipe_index += retval;
824 continue;
825 }
826
827 /* skip over APO cycles */
828 ctx->pipe_index += 2;
829
830 switch (ctx->last_branch_reason)
831 {
832 case 0x0: /* normal PC change */
833 next_pc = ctx->last_branch;
834 break;
835 case 0x1: /* tracing enabled */
836 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
837 ctx->current_pc = ctx->last_branch;
838 ctx->pipe_index++;
839 continue;
840 break;
841 case 0x2: /* trace restarted after FIFO overflow */
842 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
843 ctx->current_pc = ctx->last_branch;
844 ctx->pipe_index++;
845 continue;
846 break;
847 case 0x3: /* exit from debug state */
848 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
849 ctx->current_pc = ctx->last_branch;
850 ctx->pipe_index++;
851 continue;
852 break;
853 case 0x4: /* periodic synchronization point */
854 next_pc = ctx->last_branch;
855 /* if we had no valid PC prior to this synchronization point,
856 * we have to move on with the next trace cycle
857 */
858 if (!current_pc_ok)
859 {
860 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
861 ctx->current_pc = next_pc;
862 ctx->pipe_index++;
863 continue;
864 }
865 break;
866 default: /* reserved */
867 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
868 exit(-1);
869 break;
870 }
871
872 /* if we got here the branch was a normal PC change
873 * (or a periodic synchronization point, which means the same for that matter)
874 * if we didn't accquire a complete PC continue with the next cycle
875 */
876 if (!ctx->pc_ok)
877 continue;
878
879 /* indirect branch to the exception vector means an exception occured */
880 if ((ctx->last_branch <= 0x20)
881 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
882 {
883 if ((ctx->last_branch & 0xff) == 0x10)
884 {
885 command_print(cmd_ctx, "data abort");
886 }
887 else
888 {
889 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
890 ctx->current_pc = ctx->last_branch;
891 ctx->pipe_index++;
892 continue;
893 }
894 }
895 }
896
897 /* an instruction was executed (or not, depending on the condition flags)
898 * retrieve it from the image for displaying */
899 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
900 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
901 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
902 {
903 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
904 {
905 /* can't continue tracing with no image available */
906 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
907 {
908 return retval;
909 }
910 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
911 {
912 /* TODO: handle incomplete images
913 * for now we just quit the analsysis*/
914 return retval;
915 }
916 }
917
918 cycles = old_index - last_instruction;
919 }
920
921 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
922 {
923 uint32_t new_data_index = ctx->data_index;
924 uint32_t new_data_half = ctx->data_half;
925
926 /* in case of a branch with data, the branch target address was consumed before
927 * we temporarily go back to the saved data index */
928 if (pipestat == STAT_BD)
929 {
930 ctx->data_index = old_data_index;
931 ctx->data_half = old_data_half;
932 }
933
934 if (ctx->tracemode & ETMV1_TRACE_ADDR)
935 {
936 uint8_t packet;
937 int shift = 0;
938
939 do {
940 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
941 return ERROR_ETM_ANALYSIS_FAILED;
942 ctx->last_ptr &= ~(0x7f << shift);
943 ctx->last_ptr |= (packet & 0x7f) << shift;
944 shift += 7;
945 } while ((packet & 0x80) && (shift < 32));
946
947 if (shift >= 32)
948 ctx->ptr_ok = 1;
949
950 if (ctx->ptr_ok)
951 {
952 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
953 }
954 }
955
956 if (ctx->tracemode & ETMV1_TRACE_DATA)
957 {
958 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
959 {
960 int i;
961 for (i = 0; i < 16; i++)
962 {
963 if (instruction.info.load_store_multiple.register_list & (1 << i))
964 {
965 uint32_t data;
966 if (etmv1_data(ctx, 4, &data) != 0)
967 return ERROR_ETM_ANALYSIS_FAILED;
968 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
969 }
970 }
971 }
972 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
973 {
974 uint32_t data;
975 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
976 return ERROR_ETM_ANALYSIS_FAILED;
977 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
978 }
979 }
980
981 /* restore data index after consuming BD address and data */
982 if (pipestat == STAT_BD)
983 {
984 ctx->data_index = new_data_index;
985 ctx->data_half = new_data_half;
986 }
987 }
988
989 /* adjust PC */
990 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
991 {
992 if (((instruction.type == ARM_B) ||
993 (instruction.type == ARM_BL) ||
994 (instruction.type == ARM_BLX)) &&
995 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
996 {
997 next_pc = instruction.info.b_bl_bx_blx.target_address;
998 }
999 else
1000 {
1001 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1002 }
1003 }
1004 else if (pipestat == STAT_IN)
1005 {
1006 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1007 }
1008
1009 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1010 {
1011 char cycles_text[32] = "";
1012
1013 /* if the trace was captured with cycle accurate tracing enabled,
1014 * output the number of cycles since the last executed instruction
1015 */
1016 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1017 {
1018 snprintf(cycles_text, 32, " (%i %s)",
1019 (int)cycles,
1020 (cycles == 1) ? "cycle" : "cycles");
1021 }
1022
1023 command_print(cmd_ctx, "%s%s%s",
1024 instruction.text,
1025 (pipestat == STAT_IN) ? " (not executed)" : "",
1026 cycles_text);
1027
1028 ctx->current_pc = next_pc;
1029
1030 /* packets for an instruction don't start on or before the preceding
1031 * functional pipestat (i.e. other than WT or TD)
1032 */
1033 if (ctx->data_index <= ctx->pipe_index)
1034 {
1035 ctx->data_index = ctx->pipe_index + 1;
1036 ctx->data_half = 0;
1037 }
1038 }
1039
1040 ctx->pipe_index += 1;
1041 }
1042
1043 return ERROR_OK;
1044 }
1045
1046 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1047 {
1048 target_t *target;
1049 armv4_5_common_t *armv4_5;
1050 arm7_9_common_t *arm7_9;
1051 etmv1_tracemode_t tracemode;
1052
1053 target = get_current_target(cmd_ctx);
1054
1055 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1056 {
1057 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1058 return ERROR_OK;
1059 }
1060
1061 if (!arm7_9->etm_ctx)
1062 {
1063 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1064 return ERROR_OK;
1065 }
1066
1067 tracemode = arm7_9->etm_ctx->tracemode;
1068
1069 if (argc == 4)
1070 {
1071 if (strcmp(args[0], "none") == 0)
1072 {
1073 tracemode = ETMV1_TRACE_NONE;
1074 }
1075 else if (strcmp(args[0], "data") == 0)
1076 {
1077 tracemode = ETMV1_TRACE_DATA;
1078 }
1079 else if (strcmp(args[0], "address") == 0)
1080 {
1081 tracemode = ETMV1_TRACE_ADDR;
1082 }
1083 else if (strcmp(args[0], "all") == 0)
1084 {
1085 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1086 }
1087 else
1088 {
1089 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1090 return ERROR_OK;
1091 }
1092
1093 switch (strtol(args[1], NULL, 0))
1094 {
1095 case 0:
1096 tracemode |= ETMV1_CONTEXTID_NONE;
1097 break;
1098 case 8:
1099 tracemode |= ETMV1_CONTEXTID_8;
1100 break;
1101 case 16:
1102 tracemode |= ETMV1_CONTEXTID_16;
1103 break;
1104 case 32:
1105 tracemode |= ETMV1_CONTEXTID_32;
1106 break;
1107 default:
1108 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1109 return ERROR_OK;
1110 }
1111
1112 if (strcmp(args[2], "enable") == 0)
1113 {
1114 tracemode |= ETMV1_CYCLE_ACCURATE;
1115 }
1116 else if (strcmp(args[2], "disable") == 0)
1117 {
1118 tracemode |= 0;
1119 }
1120 else
1121 {
1122 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1123 return ERROR_OK;
1124 }
1125
1126 if (strcmp(args[3], "enable") == 0)
1127 {
1128 tracemode |= ETMV1_BRANCH_OUTPUT;
1129 }
1130 else if (strcmp(args[3], "disable") == 0)
1131 {
1132 tracemode |= 0;
1133 }
1134 else
1135 {
1136 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1137 return ERROR_OK;
1138 }
1139 }
1140 else if (argc != 0)
1141 {
1142 command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1143 return ERROR_OK;
1144 }
1145
1146 command_print(cmd_ctx, "current tracemode configuration:");
1147
1148 switch (tracemode & ETMV1_TRACE_MASK)
1149 {
1150 case ETMV1_TRACE_NONE:
1151 command_print(cmd_ctx, "data tracing: none");
1152 break;
1153 case ETMV1_TRACE_DATA:
1154 command_print(cmd_ctx, "data tracing: data only");
1155 break;
1156 case ETMV1_TRACE_ADDR:
1157 command_print(cmd_ctx, "data tracing: address only");
1158 break;
1159 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1160 command_print(cmd_ctx, "data tracing: address and data");
1161 break;
1162 }
1163
1164 switch (tracemode & ETMV1_CONTEXTID_MASK)
1165 {
1166 case ETMV1_CONTEXTID_NONE:
1167 command_print(cmd_ctx, "contextid tracing: none");
1168 break;
1169 case ETMV1_CONTEXTID_8:
1170 command_print(cmd_ctx, "contextid tracing: 8 bit");
1171 break;
1172 case ETMV1_CONTEXTID_16:
1173 command_print(cmd_ctx, "contextid tracing: 16 bit");
1174 break;
1175 case ETMV1_CONTEXTID_32:
1176 command_print(cmd_ctx, "contextid tracing: 32 bit");
1177 break;
1178 }
1179
1180 if (tracemode & ETMV1_CYCLE_ACCURATE)
1181 {
1182 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1183 }
1184 else
1185 {
1186 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1187 }
1188
1189 if (tracemode & ETMV1_BRANCH_OUTPUT)
1190 {
1191 command_print(cmd_ctx, "full branch address output enabled");
1192 }
1193 else
1194 {
1195 command_print(cmd_ctx, "full branch address output disabled");
1196 }
1197
1198 /* only update ETM_CTRL register if tracemode changed */
1199 if (arm7_9->etm_ctx->tracemode != tracemode)
1200 {
1201 reg_t *etm_ctrl_reg;
1202
1203 etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
1204 if (!etm_ctrl_reg)
1205 return ERROR_OK;
1206
1207 etm_get_reg(etm_ctrl_reg);
1208
1209 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1210 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1211 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1212 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1213 etm_store_reg(etm_ctrl_reg);
1214
1215 arm7_9->etm_ctx->tracemode = tracemode;
1216
1217 /* invalidate old trace data */
1218 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1219 if (arm7_9->etm_ctx->trace_depth > 0)
1220 {
1221 free(arm7_9->etm_ctx->trace_data);
1222 arm7_9->etm_ctx->trace_data = NULL;
1223 }
1224 arm7_9->etm_ctx->trace_depth = 0;
1225 }
1226
1227 return ERROR_OK;
1228 }
1229
1230 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1231 {
1232 target_t *target;
1233 armv4_5_common_t *armv4_5;
1234 arm7_9_common_t *arm7_9;
1235 etm_portmode_t portmode = 0x0;
1236 etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1237 int i;
1238
1239 if (argc != 5)
1240 {
1241 free(etm_ctx);
1242 return ERROR_COMMAND_SYNTAX_ERROR;
1243 }
1244
1245 target = get_target(args[0]);
1246 if (!target)
1247 {
1248 LOG_ERROR("target '%s' not defined", args[0]);
1249 free(etm_ctx);
1250 return ERROR_FAIL;
1251 }
1252
1253 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1254 {
1255 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1256 free(etm_ctx);
1257 return ERROR_FAIL;
1258 }
1259
1260 switch (strtoul(args[1], NULL, 0))
1261 {
1262 case 4:
1263 portmode |= ETM_PORT_4BIT;
1264 break;
1265 case 8:
1266 portmode |= ETM_PORT_8BIT;
1267 break;
1268 case 16:
1269 portmode |= ETM_PORT_16BIT;
1270 break;
1271 default:
1272 command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1273 free(etm_ctx);
1274 return ERROR_FAIL;
1275 }
1276
1277 if (strcmp("normal", args[2]) == 0)
1278 {
1279 portmode |= ETM_PORT_NORMAL;
1280 }
1281 else if (strcmp("multiplexed", args[2]) == 0)
1282 {
1283 portmode |= ETM_PORT_MUXED;
1284 }
1285 else if (strcmp("demultiplexed", args[2]) == 0)
1286 {
1287 portmode |= ETM_PORT_DEMUXED;
1288 }
1289 else
1290 {
1291 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1292 free(etm_ctx);
1293 return ERROR_FAIL;
1294 }
1295
1296 if (strcmp("half", args[3]) == 0)
1297 {
1298 portmode |= ETM_PORT_HALF_CLOCK;
1299 }
1300 else if (strcmp("full", args[3]) == 0)
1301 {
1302 portmode |= ETM_PORT_FULL_CLOCK;
1303 }
1304 else
1305 {
1306 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1307 free(etm_ctx);
1308 return ERROR_FAIL;
1309 }
1310
1311 for (i = 0; etm_capture_drivers[i]; i++)
1312 {
1313 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1314 {
1315 int retval;
1316 if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1317 {
1318 free(etm_ctx);
1319 return retval;
1320 }
1321
1322 etm_ctx->capture_driver = etm_capture_drivers[i];
1323
1324 break;
1325 }
1326 }
1327
1328 if (!etm_capture_drivers[i])
1329 {
1330 /* no supported capture driver found, don't register an ETM */
1331 free(etm_ctx);
1332 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1333 return ERROR_FAIL;
1334 }
1335
1336 etm_ctx->target = target;
1337 etm_ctx->trigger_percent = 50;
1338 etm_ctx->trace_data = NULL;
1339 etm_ctx->trace_depth = 0;
1340 etm_ctx->portmode = portmode;
1341 etm_ctx->tracemode = 0x0;
1342 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1343 etm_ctx->image = NULL;
1344 etm_ctx->pipe_index = 0;
1345 etm_ctx->data_index = 0;
1346 etm_ctx->current_pc = 0x0;
1347 etm_ctx->pc_ok = 0;
1348 etm_ctx->last_branch = 0x0;
1349 etm_ctx->last_branch_reason = 0x0;
1350 etm_ctx->last_ptr = 0x0;
1351 etm_ctx->ptr_ok = 0x0;
1352 etm_ctx->last_instruction = 0;
1353
1354 arm7_9->etm_ctx = etm_ctx;
1355
1356 return etm_register_user_commands(cmd_ctx);
1357 }
1358
1359 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1360 char *cmd, char **args, int argc)
1361 {
1362 target_t *target;
1363 armv4_5_common_t *armv4_5;
1364 arm7_9_common_t *arm7_9;
1365 reg_t *etm_config_reg;
1366 reg_t *etm_sys_config_reg;
1367
1368 int max_port_size;
1369
1370 target = get_current_target(cmd_ctx);
1371
1372 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1373 {
1374 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1375 return ERROR_OK;
1376 }
1377
1378 if (!arm7_9->etm_ctx)
1379 {
1380 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1381 return ERROR_OK;
1382 }
1383
1384 etm_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CONFIG);
1385 if (!etm_config_reg)
1386 return ERROR_OK;
1387 etm_sys_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_SYS_CONFIG);
1388 if (!etm_sys_config_reg)
1389 return ERROR_OK;
1390
1391 etm_get_reg(etm_config_reg);
1392 command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
1393 command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4));
1394 command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5));
1395 command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3));
1396 command_print(cmd_ctx, "sequencer %spresent",
1397 (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1398 command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3));
1399 command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3));
1400 command_print(cmd_ctx, "FIFO full %spresent",
1401 (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1402 command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3));
1403
1404 etm_get_reg(etm_sys_config_reg);
1405
1406 switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1407 {
1408 case 0:
1409 max_port_size = 4;
1410 break;
1411 case 1:
1412 max_port_size = 8;
1413 break;
1414 case 2:
1415 max_port_size = 16;
1416 break;
1417 default:
1418 LOG_ERROR("Illegal max_port_size");
1419 exit(-1);
1420 }
1421 command_print(cmd_ctx, "max. port size: %i", max_port_size);
1422
1423 command_print(cmd_ctx, "half-rate clocking %ssupported",
1424 (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1425 command_print(cmd_ctx, "full-rate clocking %ssupported",
1426 (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1427 command_print(cmd_ctx, "normal trace format %ssupported",
1428 (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1429 command_print(cmd_ctx, "multiplex trace format %ssupported",
1430 (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1431 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1432 (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1433 command_print(cmd_ctx, "FIFO full %ssupported",
1434 (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1435
1436 return ERROR_OK;
1437 }
1438
1439 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1440 {
1441 target_t *target;
1442 armv4_5_common_t *armv4_5;
1443 arm7_9_common_t *arm7_9;
1444 trace_status_t trace_status;
1445
1446 target = get_current_target(cmd_ctx);
1447
1448 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1449 {
1450 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1451 return ERROR_OK;
1452 }
1453
1454 if (!arm7_9->etm_ctx)
1455 {
1456 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1457 return ERROR_OK;
1458 }
1459
1460 trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1461
1462 if (trace_status == TRACE_IDLE)
1463 {
1464 command_print(cmd_ctx, "tracing is idle");
1465 }
1466 else
1467 {
1468 static char *completed = " completed";
1469 static char *running = " is running";
1470 static char *overflowed = ", trace overflowed";
1471 static char *triggered = ", trace triggered";
1472
1473 command_print(cmd_ctx, "trace collection%s%s%s",
1474 (trace_status & TRACE_RUNNING) ? running : completed,
1475 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1476 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1477
1478 if (arm7_9->etm_ctx->trace_depth > 0)
1479 {
1480 command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
1481 }
1482 }
1483
1484 return ERROR_OK;
1485 }
1486
1487 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1488 {
1489 target_t *target;
1490 armv4_5_common_t *armv4_5;
1491 arm7_9_common_t *arm7_9;
1492 etm_context_t *etm_ctx;
1493
1494 if (argc < 1)
1495 {
1496 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1497 return ERROR_OK;
1498 }
1499
1500 target = get_current_target(cmd_ctx);
1501
1502 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1503 {
1504 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1505 return ERROR_OK;
1506 }
1507
1508 if (!(etm_ctx = arm7_9->etm_ctx))
1509 {
1510 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1511 return ERROR_OK;
1512 }
1513
1514 if (etm_ctx->image)
1515 {
1516 image_close(etm_ctx->image);
1517 free(etm_ctx->image);
1518 command_print(cmd_ctx, "previously loaded image found and closed");
1519 }
1520
1521 etm_ctx->image = malloc(sizeof(image_t));
1522 etm_ctx->image->base_address_set = 0;
1523 etm_ctx->image->start_address_set = 0;
1524
1525 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1526 if (argc >= 2)
1527 {
1528 etm_ctx->image->base_address_set = 1;
1529 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1530 }
1531 else
1532 {
1533 etm_ctx->image->base_address_set = 0;
1534 }
1535
1536 if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1537 {
1538 free(etm_ctx->image);
1539 etm_ctx->image = NULL;
1540 return ERROR_OK;
1541 }
1542
1543 return ERROR_OK;
1544 }
1545
1546 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1547 {
1548 fileio_t file;
1549 target_t *target;
1550 armv4_5_common_t *armv4_5;
1551 arm7_9_common_t *arm7_9;
1552 etm_context_t *etm_ctx;
1553 uint32_t i;
1554
1555 if (argc != 1)
1556 {
1557 command_print(cmd_ctx, "usage: etm dump <file>");
1558 return ERROR_OK;
1559 }
1560
1561 target = get_current_target(cmd_ctx);
1562
1563 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1564 {
1565 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1566 return ERROR_OK;
1567 }
1568
1569 if (!(etm_ctx = arm7_9->etm_ctx))
1570 {
1571 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1572 return ERROR_OK;
1573 }
1574
1575 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1576 {
1577 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1578 return ERROR_OK;
1579 }
1580
1581 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1582 {
1583 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1584 command_print(cmd_ctx, "trace capture not completed");
1585 return ERROR_OK;
1586 }
1587
1588 /* read the trace data if it wasn't read already */
1589 if (etm_ctx->trace_depth == 0)
1590 etm_ctx->capture_driver->read_trace(etm_ctx);
1591
1592 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1593 {
1594 return ERROR_OK;
1595 }
1596
1597 fileio_write_u32(&file, etm_ctx->capture_status);
1598 fileio_write_u32(&file, etm_ctx->portmode);
1599 fileio_write_u32(&file, etm_ctx->tracemode);
1600 fileio_write_u32(&file, etm_ctx->trace_depth);
1601
1602 for (i = 0; i < etm_ctx->trace_depth; i++)
1603 {
1604 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1605 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1606 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1607 }
1608
1609 fileio_close(&file);
1610
1611 return ERROR_OK;
1612 }
1613
1614 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1615 {
1616 fileio_t file;
1617 target_t *target;
1618 armv4_5_common_t *armv4_5;
1619 arm7_9_common_t *arm7_9;
1620 etm_context_t *etm_ctx;
1621 uint32_t i;
1622
1623 if (argc != 1)
1624 {
1625 command_print(cmd_ctx, "usage: etm load <file>");
1626 return ERROR_OK;
1627 }
1628
1629 target = get_current_target(cmd_ctx);
1630
1631 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1632 {
1633 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1634 return ERROR_OK;
1635 }
1636
1637 if (!(etm_ctx = arm7_9->etm_ctx))
1638 {
1639 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1640 return ERROR_OK;
1641 }
1642
1643 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1644 {
1645 command_print(cmd_ctx, "trace capture running, stop first");
1646 return ERROR_OK;
1647 }
1648
1649 if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1650 {
1651 return ERROR_OK;
1652 }
1653
1654 if (file.size % 4)
1655 {
1656 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1657 fileio_close(&file);
1658 return ERROR_OK;
1659 }
1660
1661 if (etm_ctx->trace_depth > 0)
1662 {
1663 free(etm_ctx->trace_data);
1664 etm_ctx->trace_data = NULL;
1665 }
1666
1667 {
1668 uint32_t tmp;
1669 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1670 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1671 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1672 fileio_read_u32(&file, &etm_ctx->trace_depth);
1673 }
1674 etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1675 if (etm_ctx->trace_data == NULL)
1676 {
1677 command_print(cmd_ctx, "not enough memory to perform operation");
1678 fileio_close(&file);
1679 return ERROR_OK;
1680 }
1681
1682 for (i = 0; i < etm_ctx->trace_depth; i++)
1683 {
1684 uint32_t pipestat, packet, flags;
1685 fileio_read_u32(&file, &pipestat);
1686 fileio_read_u32(&file, &packet);
1687 fileio_read_u32(&file, &flags);
1688 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1689 etm_ctx->trace_data[i].packet = packet & 0xffff;
1690 etm_ctx->trace_data[i].flags = flags;
1691 }
1692
1693 fileio_close(&file);
1694
1695 return ERROR_OK;
1696 }
1697
1698 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1699 {
1700 target_t *target;
1701 armv4_5_common_t *armv4_5;
1702 arm7_9_common_t *arm7_9;
1703 etm_context_t *etm_ctx;
1704
1705 target = get_current_target(cmd_ctx);
1706
1707 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1708 {
1709 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1710 return ERROR_OK;
1711 }
1712
1713 if (!(etm_ctx = arm7_9->etm_ctx))
1714 {
1715 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1716 return ERROR_OK;
1717 }
1718
1719 if (argc > 0)
1720 {
1721 uint32_t new_value = strtoul(args[0], NULL, 0);
1722
1723 if ((new_value < 2) || (new_value > 100))
1724 {
1725 command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1726 }
1727 else
1728 {
1729 etm_ctx->trigger_percent = new_value;
1730 }
1731 }
1732
1733 command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1734
1735 return ERROR_OK;
1736 }
1737
1738 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1739 {
1740 target_t *target;
1741 armv4_5_common_t *armv4_5;
1742 arm7_9_common_t *arm7_9;
1743 etm_context_t *etm_ctx;
1744 reg_t *etm_ctrl_reg;
1745
1746 target = get_current_target(cmd_ctx);
1747
1748 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1749 {
1750 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1751 return ERROR_OK;
1752 }
1753
1754 if (!(etm_ctx = arm7_9->etm_ctx))
1755 {
1756 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1757 return ERROR_OK;
1758 }
1759
1760 /* invalidate old tracing data */
1761 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1762 if (arm7_9->etm_ctx->trace_depth > 0)
1763 {
1764 free(arm7_9->etm_ctx->trace_data);
1765 arm7_9->etm_ctx->trace_data = NULL;
1766 }
1767 arm7_9->etm_ctx->trace_depth = 0;
1768
1769 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1770 if (!etm_ctrl_reg)
1771 return ERROR_OK;
1772
1773 etm_get_reg(etm_ctrl_reg);
1774
1775 /* Clear programming bit (10), set port selection bit (11) */
1776 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1777
1778 etm_store_reg(etm_ctrl_reg);
1779 jtag_execute_queue();
1780
1781 etm_ctx->capture_driver->start_capture(etm_ctx);
1782
1783 return ERROR_OK;
1784 }
1785
1786 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1787 {
1788 target_t *target;
1789 armv4_5_common_t *armv4_5;
1790 arm7_9_common_t *arm7_9;
1791 etm_context_t *etm_ctx;
1792 reg_t *etm_ctrl_reg;
1793
1794 target = get_current_target(cmd_ctx);
1795
1796 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1797 {
1798 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1799 return ERROR_OK;
1800 }
1801
1802 if (!(etm_ctx = arm7_9->etm_ctx))
1803 {
1804 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1805 return ERROR_OK;
1806 }
1807
1808 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1809 if (!etm_ctrl_reg)
1810 return ERROR_OK;
1811
1812 etm_get_reg(etm_ctrl_reg);
1813
1814 /* Set programming bit (10), clear port selection bit (11) */
1815 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1816
1817 etm_store_reg(etm_ctrl_reg);
1818 jtag_execute_queue();
1819
1820 etm_ctx->capture_driver->stop_capture(etm_ctx);
1821
1822 return ERROR_OK;
1823 }
1824
1825 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1826 {
1827 target_t *target;
1828 armv4_5_common_t *armv4_5;
1829 arm7_9_common_t *arm7_9;
1830 etm_context_t *etm_ctx;
1831 int retval;
1832
1833 target = get_current_target(cmd_ctx);
1834
1835 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1836 {
1837 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1838 return ERROR_OK;
1839 }
1840
1841 if (!(etm_ctx = arm7_9->etm_ctx))
1842 {
1843 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1844 return ERROR_OK;
1845 }
1846
1847 if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1848 {
1849 switch (retval)
1850 {
1851 case ERROR_ETM_ANALYSIS_FAILED:
1852 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1853 break;
1854 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1855 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1856 break;
1857 case ERROR_TRACE_IMAGE_UNAVAILABLE:
1858 command_print(cmd_ctx, "no image available for trace analysis");
1859 break;
1860 default:
1861 command_print(cmd_ctx, "unknown error: %i", retval);
1862 }
1863 }
1864
1865 return ERROR_OK;
1866 }
1867
1868 int etm_register_commands(struct command_context_s *cmd_ctx)
1869 {
1870 etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1871
1872 register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
1873 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1874
1875 return ERROR_OK;
1876 }
1877
1878 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
1879 {
1880 register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1881 COMMAND_EXEC, "configure/display trace mode: "
1882 "<none | data | address | all> "
1883 "<context_id_bits> <cycle_accurate> <branch_output>");
1884
1885 register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1886 COMMAND_EXEC, "display info about the current target's ETM");
1887
1888 register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
1889 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1890 register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1891 COMMAND_EXEC, "display current target's ETM status");
1892 register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1893 COMMAND_EXEC, "start ETM trace collection");
1894 register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1895 COMMAND_EXEC, "stop ETM trace collection");
1896
1897 register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1898 COMMAND_EXEC, "anaylze collected ETM trace");
1899
1900 register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1901 COMMAND_EXEC, "load image from <file> [base address]");
1902
1903 register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1904 COMMAND_EXEC, "dump captured trace data <file>");
1905 register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1906 COMMAND_EXEC, "load trace data for analysis <file>");
1907
1908 return ERROR_OK;
1909 }
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|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)