1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
30 #include "arm7_9_common.h"
31 #include "arm_disassembler.h"
32 #include "arm_simulator.h"
37 #include "binarybuffer.h"
45 /* ETM register access functionality
49 bitfield_desc_t etm_comms_ctrl_bitfield_desc
[] =
57 int etm_reg_arch_info
[] =
59 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
60 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
61 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
62 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
63 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
64 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
65 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
66 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
67 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
68 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
69 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
70 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
71 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
72 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
75 int etm_reg_arch_size_info
[] =
77 32, 32, 17, 8, 3, 9, 32, 16,
78 17, 26, 25, 8, 17, 32, 32, 17,
79 32, 32, 32, 32, 32, 32, 32, 32,
80 32, 32, 32, 32, 32, 32, 32, 32,
81 7, 7, 7, 7, 7, 7, 7, 7,
82 7, 7, 7, 7, 7, 7, 7, 7,
83 32, 32, 32, 32, 32, 32, 32, 32,
84 32, 32, 32, 32, 32, 32, 32, 32,
85 32, 32, 32, 32, 32, 32, 32, 32,
86 32, 32, 32, 32, 32, 32, 32, 32,
87 16, 16, 16, 16, 18, 18, 18, 18,
88 17, 17, 17, 17, 16, 16, 16, 16,
89 17, 17, 17, 17, 17, 17, 2,
90 17, 17, 17, 17, 32, 32, 32, 32
93 char* etm_reg_list
[] =
101 "ETM_TRACE_RESOURCE_CTRL",
102 "ETM_TRACE_EN_CTRL2",
103 "ETM_TRACE_EN_EVENT",
104 "ETM_TRACE_EN_CTRL1",
105 "ETM_FIFOFULL_REGION",
106 "ETM_FIFOFULL_LEVEL",
107 "ETM_VIEWDATA_EVENT",
108 "ETM_VIEWDATA_CTRL1",
109 "ETM_VIEWDATA_CTRL2",
110 "ETM_VIEWDATA_CTRL3",
111 "ETM_ADDR_COMPARATOR_VALUE1",
112 "ETM_ADDR_COMPARATOR_VALUE2",
113 "ETM_ADDR_COMPARATOR_VALUE3",
114 "ETM_ADDR_COMPARATOR_VALUE4",
115 "ETM_ADDR_COMPARATOR_VALUE5",
116 "ETM_ADDR_COMPARATOR_VALUE6",
117 "ETM_ADDR_COMPARATOR_VALUE7",
118 "ETM_ADDR_COMPARATOR_VALUE8",
119 "ETM_ADDR_COMPARATOR_VALUE9",
120 "ETM_ADDR_COMPARATOR_VALUE10",
121 "ETM_ADDR_COMPARATOR_VALUE11",
122 "ETM_ADDR_COMPARATOR_VALUE12",
123 "ETM_ADDR_COMPARATOR_VALUE13",
124 "ETM_ADDR_COMPARATOR_VALUE14",
125 "ETM_ADDR_COMPARATOR_VALUE15",
126 "ETM_ADDR_COMPARATOR_VALUE16",
127 "ETM_ADDR_ACCESS_TYPE1",
128 "ETM_ADDR_ACCESS_TYPE2",
129 "ETM_ADDR_ACCESS_TYPE3",
130 "ETM_ADDR_ACCESS_TYPE4",
131 "ETM_ADDR_ACCESS_TYPE5",
132 "ETM_ADDR_ACCESS_TYPE6",
133 "ETM_ADDR_ACCESS_TYPE7",
134 "ETM_ADDR_ACCESS_TYPE8",
135 "ETM_ADDR_ACCESS_TYPE9",
136 "ETM_ADDR_ACCESS_TYPE10",
137 "ETM_ADDR_ACCESS_TYPE11",
138 "ETM_ADDR_ACCESS_TYPE12",
139 "ETM_ADDR_ACCESS_TYPE13",
140 "ETM_ADDR_ACCESS_TYPE14",
141 "ETM_ADDR_ACCESS_TYPE15",
142 "ETM_ADDR_ACCESS_TYPE16",
143 "ETM_DATA_COMPARATOR_VALUE1",
144 "ETM_DATA_COMPARATOR_VALUE2",
145 "ETM_DATA_COMPARATOR_VALUE3",
146 "ETM_DATA_COMPARATOR_VALUE4",
147 "ETM_DATA_COMPARATOR_VALUE5",
148 "ETM_DATA_COMPARATOR_VALUE6",
149 "ETM_DATA_COMPARATOR_VALUE7",
150 "ETM_DATA_COMPARATOR_VALUE8",
151 "ETM_DATA_COMPARATOR_VALUE9",
152 "ETM_DATA_COMPARATOR_VALUE10",
153 "ETM_DATA_COMPARATOR_VALUE11",
154 "ETM_DATA_COMPARATOR_VALUE12",
155 "ETM_DATA_COMPARATOR_VALUE13",
156 "ETM_DATA_COMPARATOR_VALUE14",
157 "ETM_DATA_COMPARATOR_VALUE15",
158 "ETM_DATA_COMPARATOR_VALUE16",
159 "ETM_DATA_COMPARATOR_MASK1",
160 "ETM_DATA_COMPARATOR_MASK2",
161 "ETM_DATA_COMPARATOR_MASK3",
162 "ETM_DATA_COMPARATOR_MASK4",
163 "ETM_DATA_COMPARATOR_MASK5",
164 "ETM_DATA_COMPARATOR_MASK6",
165 "ETM_DATA_COMPARATOR_MASK7",
166 "ETM_DATA_COMPARATOR_MASK8",
167 "ETM_DATA_COMPARATOR_MASK9",
168 "ETM_DATA_COMPARATOR_MASK10",
169 "ETM_DATA_COMPARATOR_MASK11",
170 "ETM_DATA_COMPARATOR_MASK12",
171 "ETM_DATA_COMPARATOR_MASK13",
172 "ETM_DATA_COMPARATOR_MASK14",
173 "ETM_DATA_COMPARATOR_MASK15",
174 "ETM_DATA_COMPARATOR_MASK16",
175 "ETM_COUNTER_INITAL_VALUE1",
176 "ETM_COUNTER_INITAL_VALUE2",
177 "ETM_COUNTER_INITAL_VALUE3",
178 "ETM_COUNTER_INITAL_VALUE4",
179 "ETM_COUNTER_ENABLE1",
180 "ETM_COUNTER_ENABLE2",
181 "ETM_COUNTER_ENABLE3",
182 "ETM_COUNTER_ENABLE4",
183 "ETM_COUNTER_RELOAD_VALUE1",
184 "ETM_COUNTER_RELOAD_VALUE2",
185 "ETM_COUNTER_RELOAD_VALUE3",
186 "ETM_COUNTER_RELOAD_VALUE4",
187 "ETM_COUNTER_VALUE1",
188 "ETM_COUNTER_VALUE2",
189 "ETM_COUNTER_VALUE3",
190 "ETM_COUNTER_VALUE4",
191 "ETM_SEQUENCER_CTRL1",
192 "ETM_SEQUENCER_CTRL2",
193 "ETM_SEQUENCER_CTRL3",
194 "ETM_SEQUENCER_CTRL4",
195 "ETM_SEQUENCER_CTRL5",
196 "ETM_SEQUENCER_CTRL6",
197 "ETM_SEQUENCER_STATE",
198 "ETM_EXTERNAL_OUTPUT1",
199 "ETM_EXTERNAL_OUTPUT2",
200 "ETM_EXTERNAL_OUTPUT3",
201 "ETM_EXTERNAL_OUTPUT4",
202 "ETM_CONTEXTID_COMPARATOR_VALUE1",
203 "ETM_CONTEXTID_COMPARATOR_VALUE2",
204 "ETM_CONTEXTID_COMPARATOR_VALUE3",
205 "ETM_CONTEXTID_COMPARATOR_MASK"
208 int etm_reg_arch_type
= -1;
210 int etm_get_reg(reg_t
*reg
);
211 int etm_set_reg(reg_t
*reg
, u32 value
);
212 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
214 int etm_write_reg(reg_t
*reg
, u32 value
);
215 int etm_read_reg(reg_t
*reg
);
217 command_t
*etm_cmd
= NULL
;
219 reg_cache_t
* etm_build_reg_cache(target_t
*target
, arm_jtag_t
*jtag_info
, etm_context_t
*etm_ctx
)
221 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
222 reg_t
*reg_list
= NULL
;
223 etm_reg_t
*arch_info
= NULL
;
224 int num_regs
= sizeof(etm_reg_arch_info
)/sizeof(int);
228 /* register a register arch-type for etm registers only once */
229 if (etm_reg_arch_type
== -1)
230 etm_reg_arch_type
= register_reg_arch_type(etm_get_reg
, etm_set_reg_w_exec
);
232 /* the actual registers are kept in two arrays */
233 reg_list
= calloc(num_regs
, sizeof(reg_t
));
234 arch_info
= calloc(num_regs
, sizeof(etm_reg_t
));
236 /* fill in values for the reg cache */
237 reg_cache
->name
= "etm registers";
238 reg_cache
->next
= NULL
;
239 reg_cache
->reg_list
= reg_list
;
240 reg_cache
->num_regs
= num_regs
;
242 /* set up registers */
243 for (i
= 0; i
< num_regs
; i
++)
245 reg_list
[i
].name
= etm_reg_list
[i
];
246 reg_list
[i
].size
= 32;
247 reg_list
[i
].dirty
= 0;
248 reg_list
[i
].valid
= 0;
249 reg_list
[i
].bitfield_desc
= NULL
;
250 reg_list
[i
].num_bitfields
= 0;
251 reg_list
[i
].value
= calloc(1, 4);
252 reg_list
[i
].arch_info
= &arch_info
[i
];
253 reg_list
[i
].arch_type
= etm_reg_arch_type
;
254 reg_list
[i
].size
= etm_reg_arch_size_info
[i
];
255 arch_info
[i
].addr
= etm_reg_arch_info
[i
];
256 arch_info
[i
].jtag_info
= jtag_info
;
259 /* initialize some ETM control register settings */
260 etm_get_reg(®_list
[ETM_CTRL
]);
261 etm_ctrl_value
= buf_get_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
);
263 /* clear the ETM powerdown bit (0) */
264 etm_ctrl_value
&= ~0x1;
266 /* configure port width (6:4), mode (17:16) and clocking (13) */
267 etm_ctrl_value
= (etm_ctrl_value
&
268 ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK
)
271 buf_set_u32(reg_list
[ETM_CTRL
].value
, 0, reg_list
[ETM_CTRL
].size
, etm_ctrl_value
);
272 etm_store_reg(®_list
[ETM_CTRL
]);
274 /* the ETM might have an ETB connected */
275 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0)
277 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
281 ERROR("etb selected as etm capture driver, but no ETB configured");
285 reg_cache
->next
= etb_build_reg_cache(etb
);
287 etb
->reg_cache
= reg_cache
->next
;
289 if (etm_ctx
->capture_driver
->init(etm_ctx
) != ERROR_OK
)
291 ERROR("ETM capture driver initialization failed");
299 int etm_get_reg(reg_t
*reg
)
301 if (etm_read_reg(reg
) != ERROR_OK
)
303 ERROR("BUG: error scheduling etm register read");
307 if (jtag_execute_queue() != ERROR_OK
)
309 ERROR("register read failed");
315 int etm_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
317 etm_reg_t
*etm_reg
= reg
->arch_info
;
318 u8 reg_addr
= etm_reg
->addr
& 0x7f;
319 scan_field_t fields
[3];
321 DEBUG("%i", etm_reg
->addr
);
323 jtag_add_end_state(TAP_RTI
);
324 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
325 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
327 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
328 fields
[0].num_bits
= 32;
329 fields
[0].out_value
= reg
->value
;
330 fields
[0].out_mask
= NULL
;
331 fields
[0].in_value
= NULL
;
332 fields
[0].in_check_value
= NULL
;
333 fields
[0].in_check_mask
= NULL
;
334 fields
[0].in_handler
= NULL
;
335 fields
[0].in_handler_priv
= NULL
;
337 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
338 fields
[1].num_bits
= 7;
339 fields
[1].out_value
= malloc(1);
340 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
341 fields
[1].out_mask
= NULL
;
342 fields
[1].in_value
= NULL
;
343 fields
[1].in_check_value
= NULL
;
344 fields
[1].in_check_mask
= NULL
;
345 fields
[1].in_handler
= NULL
;
346 fields
[1].in_handler_priv
= NULL
;
348 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
349 fields
[2].num_bits
= 1;
350 fields
[2].out_value
= malloc(1);
351 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
352 fields
[2].out_mask
= NULL
;
353 fields
[2].in_value
= NULL
;
354 fields
[2].in_check_value
= NULL
;
355 fields
[2].in_check_mask
= NULL
;
356 fields
[2].in_handler
= NULL
;
357 fields
[2].in_handler_priv
= NULL
;
359 jtag_add_dr_scan(3, fields
, -1, NULL
);
361 fields
[0].in_value
= reg
->value
;
362 fields
[0].in_check_value
= check_value
;
363 fields
[0].in_check_mask
= check_mask
;
365 jtag_add_dr_scan(3, fields
, -1, NULL
);
367 free(fields
[1].out_value
);
368 free(fields
[2].out_value
);
373 int etm_read_reg(reg_t
*reg
)
375 return etm_read_reg_w_check(reg
, NULL
, NULL
);
378 int etm_set_reg(reg_t
*reg
, u32 value
)
380 if (etm_write_reg(reg
, value
) != ERROR_OK
)
382 ERROR("BUG: error scheduling etm register write");
386 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
393 int etm_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
395 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
397 if (jtag_execute_queue() != ERROR_OK
)
399 ERROR("register write failed");
405 int etm_write_reg(reg_t
*reg
, u32 value
)
407 etm_reg_t
*etm_reg
= reg
->arch_info
;
408 u8 reg_addr
= etm_reg
->addr
& 0x7f;
409 scan_field_t fields
[3];
411 DEBUG("%i: 0x%8.8x", etm_reg
->addr
, value
);
413 jtag_add_end_state(TAP_RTI
);
414 arm_jtag_scann(etm_reg
->jtag_info
, 0x6);
415 arm_jtag_set_instr(etm_reg
->jtag_info
, etm_reg
->jtag_info
->intest_instr
, NULL
);
417 fields
[0].device
= etm_reg
->jtag_info
->chain_pos
;
418 fields
[0].num_bits
= 32;
419 fields
[0].out_value
= malloc(4);
420 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
421 fields
[0].out_mask
= NULL
;
422 fields
[0].in_value
= NULL
;
423 fields
[0].in_check_value
= NULL
;
424 fields
[0].in_check_mask
= NULL
;
425 fields
[0].in_handler
= NULL
;
426 fields
[0].in_handler_priv
= NULL
;
428 fields
[1].device
= etm_reg
->jtag_info
->chain_pos
;
429 fields
[1].num_bits
= 7;
430 fields
[1].out_value
= malloc(1);
431 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
432 fields
[1].out_mask
= NULL
;
433 fields
[1].in_value
= NULL
;
434 fields
[1].in_check_value
= NULL
;
435 fields
[1].in_check_mask
= NULL
;
436 fields
[1].in_handler
= NULL
;
437 fields
[1].in_handler_priv
= NULL
;
439 fields
[2].device
= etm_reg
->jtag_info
->chain_pos
;
440 fields
[2].num_bits
= 1;
441 fields
[2].out_value
= malloc(1);
442 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
443 fields
[2].out_mask
= NULL
;
444 fields
[2].in_value
= NULL
;
445 fields
[2].in_check_value
= NULL
;
446 fields
[2].in_check_mask
= NULL
;
447 fields
[2].in_handler
= NULL
;
448 fields
[2].in_handler_priv
= NULL
;
450 jtag_add_dr_scan(3, fields
, -1, NULL
);
452 free(fields
[0].out_value
);
453 free(fields
[1].out_value
);
454 free(fields
[2].out_value
);
459 int etm_store_reg(reg_t
*reg
)
461 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
464 /* ETM trace analysis functionality
467 extern etm_capture_driver_t etb_capture_driver
;
469 etm_capture_driver_t
*etm_capture_drivers
[] =
475 char *etmv1v1_branch_reason_strings
[] =
479 "trace restarted after overflow",
481 "periodic synchronization",
487 int etm_read_instruction(etm_context_t
*ctx
, arm_instruction_t
*instruction
)
496 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
498 /* search for the section the current instruction belongs to */
499 for (i
= 0; i
< ctx
->image
->num_sections
; i
++)
501 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
502 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
> ctx
->current_pc
))
511 /* current instruction couldn't be found in the image */
512 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
515 if (ctx
->core_state
== ARMV4_5_STATE_ARM
)
518 if ((retval
= image_read_section(ctx
->image
, section
,
519 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
520 4, buf
, &size_read
)) != ERROR_OK
)
522 ERROR("error while reading instruction: %i", retval
);
523 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
525 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
526 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
528 else if (ctx
->core_state
== ARMV4_5_STATE_THUMB
)
531 if ((retval
= image_read_section(ctx
->image
, section
,
532 ctx
->current_pc
- ctx
->image
->sections
[section
].base_address
,
533 2, buf
, &size_read
)) != ERROR_OK
)
535 ERROR("error while reading instruction: %i", retval
);
536 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
538 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
539 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
541 else if (ctx
->core_state
== ARMV4_5_STATE_JAZELLE
)
543 ERROR("BUG: tracing of jazelle code not supported");
548 ERROR("BUG: unknown core state encountered");
555 int etmv1_next_packet(etm_context_t
*ctx
, u8
*packet
, int apo
)
557 while (ctx
->data_index
< ctx
->trace_depth
)
559 /* if the caller specified an address packet offset, skip until the
560 * we reach the n-th cycle marked with tracesync */
563 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
574 /* no tracedata output during a TD cycle
575 * or in a trigger cycle */
576 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
577 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
))
584 if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
)
586 if (ctx
->data_half
== 0)
588 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
593 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
598 else if ((ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
600 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
605 /* on a 4-bit port, a packet will be output during two consecutive cycles */
606 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
609 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
610 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
611 ctx
->data_index
+= 2;
620 int etmv1_branch_address(etm_context_t
*ctx
)
628 /* quit analysis if less than two cycles are left in the trace
629 * because we can't extract the APO */
630 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
633 /* a BE could be output during an APO cycle, skip the current
634 * and continue with the new one */
635 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
637 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
640 /* address packet offset encoded in the next two cycles' pipestat bits */
641 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
642 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
644 /* count number of tracesync cycles between current pipe_index and data_index
645 * i.e. the number of tracesyncs that data_index already passed by
646 * to subtract them from the APO */
647 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++)
649 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
653 /* extract up to four 7-bit packets */
655 if ((retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0)) != 0)
657 ctx
->last_branch
&= ~(0x7f << shift
);
658 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
660 } while ((packet
& 0x80) && (shift
< 28));
662 /* one last packet holding 4 bits of the address, plus the branch reason code */
663 if ((shift
== 28) && (packet
& 0x80))
665 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
667 ctx
->last_branch
&= 0x0fffffff;
668 ctx
->last_branch
|= (packet
& 0x0f) << 28;
669 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
674 ctx
->last_branch_reason
= 0;
682 /* if a full address was output, we might have branched into Jazelle state */
683 if ((shift
== 32) && (packet
& 0x80))
685 ctx
->core_state
= ARMV4_5_STATE_JAZELLE
;
689 /* if we didn't branch into Jazelle state, the current processor state is
690 * encoded in bit 0 of the branch target address */
691 if (ctx
->last_branch
& 0x1)
693 ctx
->core_state
= ARMV4_5_STATE_THUMB
;
694 ctx
->last_branch
&= ~0x1;
698 ctx
->core_state
= ARMV4_5_STATE_ARM
;
699 ctx
->last_branch
&= ~0x3;
706 int etmv1_data(etm_context_t
*ctx
, int size
, u32
*data
)
712 for (j
= 0; j
< size
; j
++)
714 if ((retval
= etmv1_next_packet(ctx
, &buf
[j
], 0)) != 0)
719 ERROR("TODO: add support for 64-bit values");
721 *data
= target_buffer_get_u32(ctx
->target
, buf
);
723 *data
= target_buffer_get_u16(ctx
->target
, buf
);
730 int etmv1_analyze_trace(etm_context_t
*ctx
, struct command_context_s
*cmd_ctx
)
733 arm_instruction_t instruction
;
735 /* read the trace data if it wasn't read already */
736 if (ctx
->trace_depth
== 0)
737 ctx
->capture_driver
->read_trace(ctx
);
739 /* start at the beginning of the captured trace */
744 /* neither the PC nor the data pointer are valid */
748 while (ctx
->pipe_index
< ctx
->trace_depth
)
750 u8 pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
751 u32 next_pc
= ctx
->current_pc
;
752 u32 old_data_index
= ctx
->data_index
;
753 u32 old_data_half
= ctx
->data_half
;
755 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
757 command_print(cmd_ctx
, "--- trigger ---");
760 /* if we don't have a valid pc skip until we reach an indirect branch */
761 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
))
767 /* any indirect branch could have interrupted instruction flow
768 * - the branch reason code could indicate a trace discontinuity
769 * - a branch to the exception vectors indicates an exception
771 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
))
773 /* backup current data index, to be able to consume the branch address
774 * before examining data address and values
776 old_data_index
= ctx
->data_index
;
777 old_data_half
= ctx
->data_half
;
779 if ((retval
= etmv1_branch_address(ctx
)) != 0)
781 /* negative return value from etmv1_branch_address means we ran out of packets,
782 * quit analysing the trace */
786 /* a positive return values means the current branch was abandoned,
787 * and a new branch was encountered in cycle ctx->pipe_index + retval;
789 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
790 ctx
->pipe_index
+= retval
;
794 /* skip over APO cycles */
795 ctx
->pipe_index
+= 2;
797 switch (ctx
->last_branch_reason
)
799 case 0x0: /* normal PC change */
800 next_pc
= ctx
->last_branch
;
802 case 0x1: /* tracing enabled */
803 command_print(cmd_ctx
, "--- tracing enabled at 0x%8.8x ---", ctx
->last_branch
);
804 ctx
->current_pc
= ctx
->last_branch
;
808 case 0x2: /* trace restarted after FIFO overflow */
809 command_print(cmd_ctx
, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx
->last_branch
);
810 ctx
->current_pc
= ctx
->last_branch
;
814 case 0x3: /* exit from debug state */
815 command_print(cmd_ctx
, "--- exit from debug state at 0x%8.8x ---", ctx
->last_branch
);
816 ctx
->current_pc
= ctx
->last_branch
;
820 case 0x4: /* periodic synchronization point */
821 next_pc
= ctx
->last_branch
;
823 default: /* reserved */
824 ERROR("BUG: branch reason code 0x%x is reserved", ctx
->last_branch_reason
);
829 /* if we got here the branch was a normal PC change
830 * (or a periodic synchronization point, which means the same for that matter)
831 * if we didn't accquire a complete PC continue with the next cycle
836 /* indirect branch to the exception vector means an exception occured */
837 if (((ctx
->last_branch
>= 0x0) && (ctx
->last_branch
<= 0x20))
838 || ((ctx
->last_branch
>= 0xffff0000) && (ctx
->last_branch
<= 0xffff0020)))
840 if ((ctx
->last_branch
& 0xff) == 0x10)
842 command_print(cmd_ctx
, "data abort");
846 command_print(cmd_ctx
, "exception vector 0x%2.2x", ctx
->last_branch
);
847 ctx
->current_pc
= ctx
->last_branch
;
854 /* an instruction was executed (or not, depending on the condition flags)
855 * retrieve it from the image for displaying */
856 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
857 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
858 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4))))
860 if ((retval
= etm_read_instruction(ctx
, &instruction
)) != ERROR_OK
)
862 /* can't continue tracing with no image available */
863 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
867 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
)
869 /* TODO: handle incomplete images */
874 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
))
876 u32 new_data_index
= ctx
->data_index
;
877 u32 new_data_half
= ctx
->data_half
;
879 /* in case of a branch with data, the branch target address was consumed before
880 * we temporarily go back to the saved data index */
881 if (pipestat
== STAT_BD
)
883 ctx
->data_index
= old_data_index
;
884 ctx
->data_half
= old_data_half
;
887 if (ctx
->tracemode
& ETMV1_TRACE_ADDR
)
893 if ((retval
= etmv1_next_packet(ctx
, &packet
, 0)) != 0)
895 ctx
->last_ptr
&= ~(0x7f << shift
);
896 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
898 } while ((packet
& 0x80) && (shift
< 32));
905 command_print(cmd_ctx
, "address: 0x%8.8x", ctx
->last_ptr
);
909 if (ctx
->tracemode
& ETMV1_TRACE_DATA
)
911 if ((instruction
.type
== ARM_LDM
) || (instruction
.type
== ARM_STM
))
914 for (i
= 0; i
< 16; i
++)
916 if (instruction
.info
.load_store_multiple
.register_list
& (1 << i
))
919 if (etmv1_data(ctx
, 4, &data
) != 0)
921 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
925 else if ((instruction
.type
>= ARM_LDR
) && (instruction
.type
<= ARM_STRH
))
928 if (etmv1_data(ctx
, arm_access_size(&instruction
), &data
) != 0)
930 command_print(cmd_ctx
, "data: 0x%8.8x", data
);
934 /* restore data index after consuming BD address and data */
935 if (pipestat
== STAT_BD
)
937 ctx
->data_index
= new_data_index
;
938 ctx
->data_half
= new_data_half
;
943 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
945 if (((instruction
.type
== ARM_B
) ||
946 (instruction
.type
== ARM_BL
) ||
947 (instruction
.type
== ARM_BLX
)) &&
948 (instruction
.info
.b_bl_bx_blx
.target_address
!= -1))
950 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
954 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
957 else if (pipestat
== STAT_IN
)
959 next_pc
+= (ctx
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2;
962 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
))
964 command_print(cmd_ctx
, "%s%s",
965 instruction
.text
, (pipestat
== STAT_IN
) ? " (not executed)" : "");
967 ctx
->current_pc
= next_pc
;
969 /* packets for an instruction don't start on or before the preceding
970 * functional pipestat (i.e. other than WT or TD)
972 if (ctx
->data_index
<= ctx
->pipe_index
)
974 ctx
->data_index
= ctx
->pipe_index
+ 1;
979 ctx
->pipe_index
+= 1;
985 int handle_etm_tracemode_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
988 armv4_5_common_t
*armv4_5
;
989 arm7_9_common_t
*arm7_9
;
990 etmv1_tracemode_t tracemode
;
992 target
= get_current_target(cmd_ctx
);
994 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
996 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1000 if (!arm7_9
->etm_ctx
)
1002 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1006 tracemode
= arm7_9
->etm_ctx
->tracemode
;
1010 if (strcmp(args
[0], "none") == 0)
1012 tracemode
= ETMV1_TRACE_NONE
;
1014 else if (strcmp(args
[0], "data") == 0)
1016 tracemode
= ETMV1_TRACE_DATA
;
1018 else if (strcmp(args
[0], "address") == 0)
1020 tracemode
= ETMV1_TRACE_ADDR
;
1022 else if (strcmp(args
[0], "all") == 0)
1024 tracemode
= ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
;
1028 command_print(cmd_ctx
, "invalid option '%s'", args
[0]);
1032 switch (strtol(args
[1], NULL
, 0))
1035 tracemode
|= ETMV1_CONTEXTID_NONE
;
1038 tracemode
|= ETMV1_CONTEXTID_8
;
1041 tracemode
|= ETMV1_CONTEXTID_16
;
1044 tracemode
|= ETMV1_CONTEXTID_32
;
1047 command_print(cmd_ctx
, "invalid option '%s'", args
[1]);
1051 if (strcmp(args
[2], "enable") == 0)
1053 tracemode
|= ETMV1_CYCLE_ACCURATE
;
1055 else if (strcmp(args
[2], "disable") == 0)
1061 command_print(cmd_ctx
, "invalid option '%s'", args
[2]);
1067 command_print(cmd_ctx
, "usage: configure trace mode <none|data|address|all> <context id bits> <enable|disable cycle accurate>");
1071 command_print(cmd_ctx
, "current tracemode configuration:");
1073 switch (tracemode
& ETMV1_TRACE_MASK
)
1075 case ETMV1_TRACE_NONE
:
1076 command_print(cmd_ctx
, "data tracing: none");
1078 case ETMV1_TRACE_DATA
:
1079 command_print(cmd_ctx
, "data tracing: data only");
1081 case ETMV1_TRACE_ADDR
:
1082 command_print(cmd_ctx
, "data tracing: address only");
1084 case ETMV1_TRACE_DATA
| ETMV1_TRACE_ADDR
:
1085 command_print(cmd_ctx
, "data tracing: address and data");
1089 switch (tracemode
& ETMV1_CONTEXTID_MASK
)
1091 case ETMV1_CONTEXTID_NONE
:
1092 command_print(cmd_ctx
, "contextid tracing: none");
1094 case ETMV1_CONTEXTID_8
:
1095 command_print(cmd_ctx
, "contextid tracing: 8 bit");
1097 case ETMV1_CONTEXTID_16
:
1098 command_print(cmd_ctx
, "contextid tracing: 16 bit");
1100 case ETMV1_CONTEXTID_32
:
1101 command_print(cmd_ctx
, "contextid tracing: 32 bit");
1105 if (tracemode
& ETMV1_CYCLE_ACCURATE
)
1107 command_print(cmd_ctx
, "cycle-accurate tracing enabled");
1111 command_print(cmd_ctx
, "cycle-accurate tracing disabled");
1114 /* only update ETM_CTRL register if tracemode changed */
1115 if (arm7_9
->etm_ctx
->tracemode
!= tracemode
)
1117 reg_t
*etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1119 etm_get_reg(etm_ctrl_reg
);
1121 buf_set_u32(etm_ctrl_reg
->value
, 2, 2, tracemode
& ETMV1_TRACE_MASK
);
1122 buf_set_u32(etm_ctrl_reg
->value
, 14, 2, (tracemode
& ETMV1_CONTEXTID_MASK
) >> 4);
1123 buf_set_u32(etm_ctrl_reg
->value
, 12, 1, (tracemode
& ETMV1_CYCLE_ACCURATE
) >> 8);
1125 etm_store_reg(etm_ctrl_reg
);
1127 arm7_9
->etm_ctx
->tracemode
= tracemode
;
1129 /* invalidate old trace data */
1130 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1131 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1133 free(arm7_9
->etm_ctx
->trace_data
);
1135 arm7_9
->etm_ctx
->trace_depth
= 0;
1141 int handle_etm_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1144 armv4_5_common_t
*armv4_5
;
1145 arm7_9_common_t
*arm7_9
;
1146 etm_portmode_t portmode
= 0x0;
1147 etm_context_t
*etm_ctx
= malloc(sizeof(etm_context_t
));
1152 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1156 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
1160 ERROR("target number '%s' not defined", args
[0]);
1164 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1166 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1170 switch (strtoul(args
[1], NULL
, 0))
1173 portmode
|= ETM_PORT_4BIT
;
1176 portmode
|= ETM_PORT_8BIT
;
1179 portmode
|= ETM_PORT_16BIT
;
1182 command_print(cmd_ctx
, "unsupported ETM port width '%s', must be 4, 8 or 16", args
[1]);
1186 if (strcmp("normal", args
[2]) == 0)
1188 portmode
|= ETM_PORT_NORMAL
;
1190 else if (strcmp("multiplexed", args
[2]) == 0)
1192 portmode
|= ETM_PORT_MUXED
;
1194 else if (strcmp("demultiplexed", args
[2]) == 0)
1196 portmode
|= ETM_PORT_DEMUXED
;
1200 command_print(cmd_ctx
, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args
[2]);
1204 if (strcmp("half", args
[3]) == 0)
1206 portmode
|= ETM_PORT_HALF_CLOCK
;
1208 else if (strcmp("full", args
[3]) == 0)
1210 portmode
|= ETM_PORT_FULL_CLOCK
;
1214 command_print(cmd_ctx
, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args
[3]);
1218 for (i
=0; etm_capture_drivers
[i
]; i
++)
1220 if (strcmp(args
[4], etm_capture_drivers
[i
]->name
) == 0)
1222 if (etm_capture_drivers
[i
]->register_commands(cmd_ctx
) != ERROR_OK
)
1228 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1234 if (!etm_capture_drivers
[i
])
1236 /* no supported capture driver found, don't register an ETM */
1238 ERROR("trace capture driver '%s' not found", args
[4]);
1242 etm_ctx
->target
= target
;
1243 etm_ctx
->trace_data
= NULL
;
1244 etm_ctx
->trace_depth
= 0;
1245 etm_ctx
->portmode
= portmode
;
1246 etm_ctx
->tracemode
= 0x0;
1247 etm_ctx
->core_state
= ARMV4_5_STATE_ARM
;
1248 etm_ctx
->image
= NULL
;
1249 etm_ctx
->pipe_index
= 0;
1250 etm_ctx
->data_index
= 0;
1251 etm_ctx
->current_pc
= 0x0;
1253 etm_ctx
->last_branch
= 0x0;
1254 etm_ctx
->last_branch_reason
= 0x0;
1255 etm_ctx
->last_ptr
= 0x0;
1256 etm_ctx
->ptr_ok
= 0x0;
1257 etm_ctx
->context_id
= 0x0;
1259 arm7_9
->etm_ctx
= etm_ctx
;
1261 etm_register_user_commands(cmd_ctx
);
1266 int handle_etm_status_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1269 armv4_5_common_t
*armv4_5
;
1270 arm7_9_common_t
*arm7_9
;
1271 trace_status_t trace_status
;
1273 target
= get_current_target(cmd_ctx
);
1275 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1277 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1281 if (!arm7_9
->etm_ctx
)
1283 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1287 trace_status
= arm7_9
->etm_ctx
->capture_driver
->status(arm7_9
->etm_ctx
);
1289 if (trace_status
== TRACE_IDLE
)
1291 command_print(cmd_ctx
, "tracing is idle");
1295 static char *completed
= " completed";
1296 static char *running
= " is running";
1297 static char *overflowed
= ", trace overflowed";
1298 static char *triggered
= ", trace triggered";
1300 command_print(cmd_ctx
, "trace collection%s%s%s",
1301 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1302 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1303 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1305 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1307 command_print(cmd_ctx
, "%i frames of trace data read", arm7_9
->etm_ctx
->trace_depth
);
1314 int handle_etm_image_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1317 armv4_5_common_t
*armv4_5
;
1318 arm7_9_common_t
*arm7_9
;
1319 etm_context_t
*etm_ctx
;
1324 command_print(cmd_ctx
, "usage: etm image <file> [base address] [type]");
1328 target
= get_current_target(cmd_ctx
);
1330 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1332 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1336 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1338 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1344 image_close(etm_ctx
->image
);
1345 free(etm_ctx
->image
);
1346 command_print(cmd_ctx
, "previously loaded image found and closed");
1349 etm_ctx
->image
= malloc(sizeof(image_t
));
1350 etm_ctx
->image
->base_address_set
= 0;
1351 etm_ctx
->image
->start_address_set
= 0;
1353 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1356 etm_ctx
->image
->base_address_set
= 1;
1357 etm_ctx
->image
->base_address
= strtoul(args
[1], NULL
, 0);
1361 etm_ctx
->image
->base_address_set
= 0;
1364 if (image_open(etm_ctx
->image
, args
[0], (argc
>= 3) ? args
[2] : NULL
) != ERROR_OK
)
1366 command_print(cmd_ctx
, "image opening error: %s", etm_ctx
->image
->error_str
);
1367 free(etm_ctx
->image
);
1368 etm_ctx
->image
= NULL
;
1375 int handle_etm_dump_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1379 armv4_5_common_t
*armv4_5
;
1380 arm7_9_common_t
*arm7_9
;
1381 etm_context_t
*etm_ctx
;
1386 command_print(cmd_ctx
, "usage: etm dump <file>");
1390 target
= get_current_target(cmd_ctx
);
1392 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1394 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1398 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1400 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1404 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
)
1406 command_print(cmd_ctx
, "trace capture wasn't enabled, no trace data captured");
1410 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1412 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1413 command_print(cmd_ctx
, "trace capture not completed");
1417 /* read the trace data if it wasn't read already */
1418 if (etm_ctx
->trace_depth
== 0)
1419 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1421 if (fileio_open(&file
, args
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1423 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1427 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1428 fileio_write_u32(&file
, etm_ctx
->portmode
);
1429 fileio_write_u32(&file
, etm_ctx
->tracemode
);
1430 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1432 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1434 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1435 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1436 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1439 fileio_close(&file
);
1444 int handle_etm_load_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1448 armv4_5_common_t
*armv4_5
;
1449 arm7_9_common_t
*arm7_9
;
1450 etm_context_t
*etm_ctx
;
1455 command_print(cmd_ctx
, "usage: etm load <file>");
1459 target
= get_current_target(cmd_ctx
);
1461 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1463 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1467 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1469 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1473 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
)
1475 command_print(cmd_ctx
, "trace capture running, stop first");
1479 if (fileio_open(&file
, args
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1481 command_print(cmd_ctx
, "file open error: %s", file
.error_str
);
1487 command_print(cmd_ctx
, "size isn't a multiple of 4, no valid trace data");
1491 if (etm_ctx
->trace_depth
> 0)
1493 free(etm_ctx
->trace_data
);
1496 fileio_read_u32(&file
, &etm_ctx
->capture_status
);
1497 fileio_read_u32(&file
, &etm_ctx
->portmode
);
1498 fileio_read_u32(&file
, &etm_ctx
->tracemode
);
1499 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1501 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
1503 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++)
1505 fileio_read_u32(&file
, &etm_ctx
->trace_data
[i
].pipestat
);
1506 fileio_read_u32(&file
, &etm_ctx
->trace_data
[i
].packet
);
1507 fileio_read_u32(&file
, &etm_ctx
->trace_data
[i
].flags
);
1510 fileio_close(&file
);
1515 int handle_etm_start_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1518 armv4_5_common_t
*armv4_5
;
1519 arm7_9_common_t
*arm7_9
;
1520 etm_context_t
*etm_ctx
;
1521 reg_t
*etm_ctrl_reg
;
1523 target
= get_current_target(cmd_ctx
);
1525 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1527 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1531 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1533 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1537 /* invalidate old tracing data */
1538 arm7_9
->etm_ctx
->capture_status
= TRACE_IDLE
;
1539 if (arm7_9
->etm_ctx
->trace_depth
> 0)
1541 free(arm7_9
->etm_ctx
->trace_data
);
1543 arm7_9
->etm_ctx
->trace_depth
= 0;
1545 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1546 etm_get_reg(etm_ctrl_reg
);
1548 /* Clear programming bit (10), set port selection bit (11) */
1549 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1551 etm_store_reg(etm_ctrl_reg
);
1552 jtag_execute_queue();
1554 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1559 int handle_etm_stop_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1562 armv4_5_common_t
*armv4_5
;
1563 arm7_9_common_t
*arm7_9
;
1564 etm_context_t
*etm_ctx
;
1565 reg_t
*etm_ctrl_reg
;
1567 target
= get_current_target(cmd_ctx
);
1569 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1571 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1575 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1577 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1581 etm_ctrl_reg
= &arm7_9
->etm_ctx
->reg_cache
->reg_list
[ETM_CTRL
];
1582 etm_get_reg(etm_ctrl_reg
);
1584 /* Set programming bit (10), clear port selection bit (11) */
1585 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1587 etm_store_reg(etm_ctrl_reg
);
1588 jtag_execute_queue();
1590 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1595 int handle_etm_analyze_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1598 armv4_5_common_t
*armv4_5
;
1599 arm7_9_common_t
*arm7_9
;
1600 etm_context_t
*etm_ctx
;
1602 target
= get_current_target(cmd_ctx
);
1604 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
1606 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
1610 if (!(etm_ctx
= arm7_9
->etm_ctx
))
1612 command_print(cmd_ctx
, "current target doesn't have an ETM configured");
1616 etmv1_analyze_trace(etm_ctx
, cmd_ctx
);
1621 int etm_register_commands(struct command_context_s
*cmd_ctx
)
1623 etm_cmd
= register_command(cmd_ctx
, NULL
, "etm", NULL
, COMMAND_ANY
, "Embedded Trace Macrocell");
1625 register_command(cmd_ctx
, etm_cmd
, "config", handle_etm_config_command
, COMMAND_CONFIG
, NULL
);
1630 int etm_register_user_commands(struct command_context_s
*cmd_ctx
)
1632 register_command(cmd_ctx
, etm_cmd
, "tracemode", handle_etm_tracemode_command
,
1633 COMMAND_EXEC
, "configure trace mode <none|data|address|all> <context id bits> <enable|disable cycle accurate>");
1635 register_command(cmd_ctx
, etm_cmd
, "status", handle_etm_status_command
,
1636 COMMAND_EXEC
, "display current target's ETM status");
1637 register_command(cmd_ctx
, etm_cmd
, "start", handle_etm_start_command
,
1638 COMMAND_EXEC
, "start ETM trace collection");
1639 register_command(cmd_ctx
, etm_cmd
, "stop", handle_etm_stop_command
,
1640 COMMAND_EXEC
, "stop ETM trace collection");
1642 register_command(cmd_ctx
, etm_cmd
, "analyze", handle_etm_analyze_command
,
1643 COMMAND_EXEC
, "anaylze collected ETM trace");
1645 register_command(cmd_ctx
, etm_cmd
, "image", handle_etm_image_command
,
1646 COMMAND_EXEC
, "load image from <file> [base address]");
1648 register_command(cmd_ctx
, etm_cmd
, "dump", handle_etm_dump_command
,
1649 COMMAND_EXEC
, "dump captured trace data <file>");
1650 register_command(cmd_ctx
, etm_cmd
, "load", handle_etm_load_command
,
1651 COMMAND_EXEC
, "load trace data for analysis <file>");
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