src/target/event/eir-sam7se512_reset.script

   1 # WDT_MR, disable watchdog
   2 mww 0xFFFFFD44 0x00008000
   3
   4 # RSTC_MR, enable user reset
   5 mww 0xfffffd08 0xa5000001
   6
   7 # CKGR_MOR
   8 mww 0xFFFFFC20 0x00000601
   9 sleep 10
  10
  11 # CKGR_PLLR
  12 mww 0xFFFFFC2C 0x00481c0e
  13 sleep 10
  14
  15 # PMC_MCKR
  16 mww 0xFFFFFC30 0x00000007
  17 sleep 10
  18
  19 # PMC_IER
  20 mww 0xFFFFFF60 0x00480100
  21
  22 #
  23 # Enable SDRAM interface.
  24 #
  25
  26 # Enable SDRAM control at PIO A.
  27 mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
  28 mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
  29
  30 # Enable address bus (A0, A2-A11, A13-A17) at PIO B
  31 mww 0xfffff674 0x0003effd # PIO_BSR_OFF
  32 mww 0xfffff604 0x0003effd # PIO_PDR_OFF
  33
  34 # Enable 16 bit data bus at PIO C
  35 mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
  36 mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
  37
  38 # Enable SDRAM chip select
  39 mww 0xffffff80 0x00000002 # EBI_CSA_OFF
  40
  41 # Set SDRAM characteristics in configuration register.
  42 # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
  43 mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
  44 sleep 10
  45
  46 # Issue 16 bit SDRAM command: NOP
  47 mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
  48 mww 0x20000000 0x00000000
  49
  50 # Issue 16 bit SDRAM command: Precharge all
  51 mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
  52 mww 0x20000000 0x00000000
  53
  54 # Issue 8 auto-refresh cycles
  55 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  56 mww 0x20000000 0x00000000
  57 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  58 mww 0x20000000 0x00000000
  59 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  60 mww 0x20000000 0x00000000
  61 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  62 mww 0x20000000 0x00000000
  63 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  64 mww 0x20000000 0x00000000
  65 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  66 mww 0x20000000 0x00000000
  67 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  68 mww 0x20000000 0x00000000
  69 mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
  70 mww 0x20000000 0x00000000
  71
  72 # Issue 16 bit SDRAM command: Set mode register
  73 mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
  74 mww 0x20000014 0xcafedede
  75
  76 # Set refresh rate count ???
  77 mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
  78
  79 # Issue 16 bit SDRAM command: Normal mode
  80 mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
  81 mww 0x20000000 0x00000180
  82
  83 #
  84 # Enable external reset key.
  85 #
  86 mww 0xfffffd08 0xa5000001
  87