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cross compile fix
[openocd.git] / src / target / event / pxa255_reset.script
1 #configuration file for PXA250 Evaluation Board
2 # -----------------------------------------------------
3 #
4 xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
5 #
6 # setup GPIO
7 #
8 mww 0x40E00018 0x00008000 #CPSR0
9 sleep 20
10 mww 0x40E0001C 0x00000002 #GPSR1
11 sleep 20
12 mww 0x40E00020 0x00000008 #GPSR2
13 sleep 20
14 mww 0x40E0000C 0x00008000 #GPDR0
15 sleep 20
16 mww 0x40E00054 0x80000000 #GAFR0_L
17 sleep 20
18 mww 0x40E00058 0x00188010 #GAFR0_H
19 sleep 20
20 mww 0x40E0005C 0x60908018 #GAFR1_L
21 sleep 20
22 mww 0x40E0000C 0x0280E000 #GPDR0
23 sleep 20
24 mww 0x40E00010 0x821C88B2 #GPDR1
25 sleep 20
26 mww 0x40E00014 0x000F03DB #GPDR2
27 sleep 20
28 mww 0x40E00000 0x000F03DB #GPLR0
29 sleep 20
30
31
32 mww 0x40F00004 0x00000020 #PSSR
33 sleep 20
34
35 #
36 # setup memory controller
37 #
38 mww 0x48000008 0x01111998 #MSC0
39 sleep 20
40 mww 0x48000010 0x00047ff0 #MSC2
41 sleep 20
42 mww 0x48000014 0x00000000 #MECR
43 sleep 20
44 mww 0x48000028 0x00010504 #MCMEM0
45 sleep 20
46 mww 0x4800002C 0x00010504 #MCMEM1
47 sleep 20
48 mww 0x48000030 0x00010504 #MCATT0
49 sleep 20
50 mww 0x48000034 0x00010504 #MCATT1
51 sleep 20
52 mww 0x48000038 0x00004715 #MCIO0
53 sleep 20
54 mww 0x4800003C 0x00004715 #MCIO1
55 sleep 20
56 #
57 mww 0x48000004 0x03CA4018 #MDREF
58 sleep 20
59 mww 0x48000004 0x004B4018 #MDREF
60 sleep 20
61 mww 0x48000004 0x000B4018 #MDREF
62 sleep 20
63 mww 0x48000004 0x000BC018 #MDREF
64 sleep 20
65 mww 0x48000000 0x00001AC8 #MDCNFG
66 sleep 20
67
68 sleep 20
69
70 mww 0x48000000 0x00001AC9 #MDCNFG
71 sleep 20
72 mww 0x48000040 0x00000000 #MDMRS
73 sleep 20
74
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