1d389287179bd02d8be8a8a5051e41ea3e32606d
[openocd.git] / src / target / event / sam7s256_reset.script
1 #
2 # Init - taken form the script openocd_at91sam7_ecr.script
3 #
4 # I take this script from the following page:
5 #
6 # http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
7 #
8 # disable watchdog
9 mww 0xfffffd44 0x00008000
10 # enable user reset
11 mww 0xfffffd08 0xa5000001
12 # CKGR_MOR : enable the main oscillator
13 mww 0xfffffc20 0x00000601
14 sleep 10
15 # CKGR_PLLR: 96.1097 MHz
16 mww 0xfffffc2c 0x00481c0e
17 sleep 10
18 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
19 mww 0xfffffc30 0x00000007
20 sleep 10
21 # MC_FMR: flash mode (FWS=1,FMCN=60)
22 mww 0xffffff60 0x003c0100
23 sleep 100

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+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)