1 mww 0xFFFFFD44, 0x00008000 #Disable watchdog
2 mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
4 mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
8 # -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
9 # when the bank 0 is the boot bank, then enable the Bank 1. */
11 mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
12 mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
13 mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
14 mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
15 mww 0x54000018, 0x18 #Enable CS on both banks
17 # -- Enable 96K RAM */
18 mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
19 arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
21 flash protect 0 0 7 off
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)