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target: remove legacy target events
[openocd.git] / src / target / feroceon.c
1 /***************************************************************************
2 * Copyright (C) 2008-2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico@marvell.com> *
4 * *
5 * Copyright (C) 2008 by Hongtao Zheng *
6 * hontor@126.com *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 /*
25 * Marvell Feroceon/Dragonite support.
26 *
27 * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others,
28 * mimics the ARM926 ICE interface with the following differences:
29 *
30 * - the MOE (method of entry) reporting is not implemented
31 *
32 * - breakpoint/watchpoint comparator #1 is seemingly not implemented
33 *
34 * - due to a different pipeline implementation, some injected debug
35 * instruction sequences have to be somewhat different
36 *
37 * Other issues:
38 *
39 * - asserting DBGRQ doesn't work if target is looping on the undef vector
40 *
41 * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
42 * not at the top, and rather meaningless due to existing discrepencies
43 *
44 * - the DCC channel is half duplex (only one FIFO for both directions) with
45 * seemingly no proper flow control.
46 *
47 * The Dragonite core is the non-mmu version based on the ARM966 model, and
48 * it shares the above issues as well.
49 */
50
51 #ifdef HAVE_CONFIG_H
52 #include "config.h"
53 #endif
54
55 #include "arm926ejs.h"
56 #include "arm966e.h"
57 #include "target_type.h"
58 #include "register.h"
59 #include "arm_opcodes.h"
60
61 static int feroceon_assert_reset(struct target *target)
62 {
63 struct arm *arm = target->arch_info;
64 struct arm7_9_common *arm7_9 = arm->arch_info;
65 int ud = arm7_9->use_dbgrq;
66
67 arm7_9->use_dbgrq = 0;
68 if (target->reset_halt)
69 arm7_9_halt(target);
70 arm7_9->use_dbgrq = ud;
71 return arm7_9_assert_reset(target);
72 }
73
74 static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
75 {
76 struct scan_field fields[3];
77 uint8_t out_buf[4];
78 uint8_t instr_buf[4];
79 uint8_t sysspeed_buf = 0x0;
80 int retval;
81
82 /* prepare buffer */
83 buf_set_u32(out_buf, 0, 32, 0);
84
85 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
86
87 retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
88 if (retval != ERROR_OK)
89 return retval;
90
91 retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
92 if (retval != ERROR_OK)
93 return retval;
94
95 fields[0].num_bits = 32;
96 fields[0].out_value = out_buf;
97 fields[0].in_value = NULL;
98
99 fields[1].num_bits = 3;
100 fields[1].out_value = &sysspeed_buf;
101 fields[1].in_value = NULL;
102
103 fields[2].num_bits = 32;
104 fields[2].out_value = instr_buf;
105 fields[2].in_value = NULL;
106
107 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
108
109 /* no jtag_add_runtest(0, TAP_DRPAUSE) here */
110
111 return ERROR_OK;
112 }
113
114 static void feroceon_change_to_arm(struct target *target, uint32_t *r0,
115 uint32_t *pc)
116 {
117 struct arm *arm = target->arch_info;
118 struct arm7_9_common *arm7_9 = arm->arch_info;
119 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
120
121 /*
122 * save r0 before using it and put system in ARM state
123 * to allow common handling of ARM and THUMB debugging
124 */
125
126 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
127 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
128 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
129
130 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
131 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
132 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
133 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
134 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
135 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
136
137 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
138 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
139 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
140 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
141 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
142 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
143 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
144
145 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(15), 0, NULL, 0);
146 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
147 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
148 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
149 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
150
151 jtag_execute_queue();
152
153 /*
154 * fix program counter:
155 * MOV R0, PC was the 7th instruction (+12)
156 * reading PC in Thumb state gives address of instruction + 4
157 */
158 *pc -= (12 + 4);
159 }
160
161 static void feroceon_read_core_regs(struct target *target,
162 uint32_t mask, uint32_t *core_regs[16])
163 {
164 int i;
165 struct arm *arm = target->arch_info;
166 struct arm7_9_common *arm7_9 = arm->arch_info;
167 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
168
169 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
170 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
171 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
172
173 for (i = 0; i <= 15; i++)
174 if (mask & (1 << i))
175 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
176
177 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
178 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
179 }
180
181 static void feroceon_read_core_regs_target_buffer(struct target *target,
182 uint32_t mask, void *buffer, int size)
183 {
184 int i;
185 struct arm *arm = target->arch_info;
186 struct arm7_9_common *arm7_9 = arm->arch_info;
187 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
188 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
189 uint32_t *buf_u32 = buffer;
190 uint16_t *buf_u16 = buffer;
191 uint8_t *buf_u8 = buffer;
192
193 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
194 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
195 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
196
197 for (i = 0; i <= 15; i++) {
198 if (mask & (1 << i)) {
199 switch (size) {
200 case 4:
201 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
202 break;
203 case 2:
204 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
205 break;
206 case 1:
207 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
208 break;
209 }
210 }
211 }
212
213 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
214 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
215 }
216
217 static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
218 {
219 struct arm *arm = target->arch_info;
220 struct arm7_9_common *arm7_9 = arm->arch_info;
221 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
222
223 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
224 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
225 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
226 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
227 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
228 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
229 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
230
231 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
232 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
233 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
234 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
235
236 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
237 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
238 }
239
240 static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
241 {
242 struct arm *arm = target->arch_info;
243 struct arm7_9_common *arm7_9 = arm->arch_info;
244 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
245
246 LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
247
248 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
249 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
250 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
251 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
252 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
253 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
254 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
255
256 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
257 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
258 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
259 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
260 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
261 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
262 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
263
264 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
265 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
266 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
267 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
268 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
269 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
270 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
271
272 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
273 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
274 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
275 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
276 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
277 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
278 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
279 }
280
281 static void feroceon_write_xpsr_im8(struct target *target,
282 uint8_t xpsr_im, int rot, int spsr)
283 {
284 struct arm *arm = target->arch_info;
285 struct arm7_9_common *arm7_9 = arm->arch_info;
286 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
287
288 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
289
290 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
291 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
293 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
294 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
295 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
296 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
297 }
298
299 static void feroceon_write_core_regs(struct target *target,
300 uint32_t mask, uint32_t core_regs[16])
301 {
302 int i;
303 struct arm *arm = target->arch_info;
304 struct arm7_9_common *arm7_9 = arm->arch_info;
305 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
306
307 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
308 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
309 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
310
311 for (i = 0; i <= 15; i++)
312 if (mask & (1 << i))
313 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
314
315 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
316 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
317 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
318 }
319
320 static void feroceon_branch_resume(struct target *target)
321 {
322 struct arm *arm = target->arch_info;
323 struct arm7_9_common *arm7_9 = arm->arch_info;
324 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
325
326 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
327 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
328 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
329 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0);
330 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
331
332 arm7_9->need_bypass_before_restart = 1;
333 }
334
335 static void feroceon_branch_resume_thumb(struct target *target)
336 {
337 LOG_DEBUG("-");
338
339 struct arm *arm = target->arch_info;
340 struct arm7_9_common *arm7_9 = arm->arch_info;
341 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
342 uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
343 uint32_t pc = buf_get_u32(arm->pc->value, 0, 32);
344
345 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
346 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
347 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
348 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
349
350 arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,pc,#1 */
351 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
352 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
353 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
354
355 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0);
356 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
357 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
358
359 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
360 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
361 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
362
363 pc = (pc & 2) >> 1;
364 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0);
365 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1);
366
367 arm7_9->need_bypass_before_restart = 1;
368 }
369
370 static int feroceon_read_cp15(struct target *target, uint32_t op1,
371 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
372 {
373 struct arm *arm = target->arch_info;
374 struct arm7_9_common *arm7_9 = arm->arch_info;
375 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
376 int err;
377
378 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
379 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
380 err = arm7_9_execute_sys_speed(target);
381 if (err != ERROR_OK)
382 return err;
383
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
387 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, value, 0);
388 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
390 return jtag_execute_queue();
391 }
392
393 static int feroceon_write_cp15(struct target *target, uint32_t op1,
394 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
395 {
396 struct arm *arm = target->arch_info;
397 struct arm7_9_common *arm7_9 = arm->arch_info;
398 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
399
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
403 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, value, NULL, 0);
404 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
406 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
407
408 arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
410 return arm7_9_execute_sys_speed(target);
411 }
412
413 static void feroceon_set_dbgrq(struct target *target)
414 {
415 struct arm *arm = target->arch_info;
416 struct arm7_9_common *arm7_9 = arm->arch_info;
417 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
418
419 buf_set_u32(dbg_ctrl->value, 0, 8, 2);
420 embeddedice_store_reg(dbg_ctrl);
421 }
422
423 static void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
424 {
425 struct arm *arm = target->arch_info;
426 struct arm7_9_common *arm7_9 = arm->arch_info;
427
428 /* set a breakpoint there */
429 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
430 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
431 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
432 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
433 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
434 }
435
436 static void feroceon_disable_single_step(struct target *target)
437 {
438 struct arm *arm = target->arch_info;
439 struct arm7_9_common *arm7_9 = arm->arch_info;
440
441 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
442 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
443 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
444 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
445 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
446 }
447
448 static int feroceon_examine_debug_reason(struct target *target)
449 {
450 /* the MOE is not implemented */
451 if (target->debug_reason != DBG_REASON_SINGLESTEP)
452 target->debug_reason = DBG_REASON_DBGRQ;
453
454 return ERROR_OK;
455 }
456
457 static int feroceon_bulk_write_memory(struct target *target,
458 uint32_t address, uint32_t count, const uint8_t *buffer)
459 {
460 int retval;
461 struct arm *arm = target->arch_info;
462 struct arm7_9_common *arm7_9 = arm->arch_info;
463 enum arm_state core_state = arm->core_state;
464 uint32_t x, flip, shift, save[7];
465 uint32_t i;
466
467 /*
468 * We can't use the dcc flow control bits, so let's transfer data
469 * with 31 bits and flip the MSB each time a new data word is sent.
470 */
471 static uint32_t dcc_code[] = {
472 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
473 0xe3a0301e, /* 1: mov r3, #30 */
474 0xe3a04002, /* mov r4, #2 */
475 0xee111e10, /* 2: mrc p14, 0, r1, c1, c0, 0 */
476 0xe1310005, /* teq r1, r5 */
477 0x0afffffc, /* beq 1b */
478 0xe1a05001, /* mov r5, r1 */
479 0xe1a01081, /* mov r1, r1, lsl #1 */
480 0xee112e10, /* 3: mrc p14, 0, r2, c1, c0, 0 */
481 0xe1320005, /* teq r2, r5 */
482 0x0afffffc, /* beq 3b */
483 0xe1a05002, /* mov r5, r2 */
484 0xe3c22102, /* bic r2, r2, #0x80000000 */
485 0xe1811332, /* orr r1, r1, r2, lsr r3 */
486 0xe2533001, /* subs r3, r3, #1 */
487 0xe4801004, /* str r1, [r0], #4 */
488 0xe1a01412, /* mov r1, r2, lsl r4 */
489 0xe2844001, /* add r4, r4, #1 */
490 0x4affffed, /* bmi 1b */
491 0xeafffff3, /* b 3b */
492 };
493
494 uint32_t dcc_size = sizeof(dcc_code);
495
496 if (!arm7_9->dcc_downloads)
497 return target_write_memory(target, address, 4, count, buffer);
498
499 /* regrab previously allocated working_area, or allocate a new one */
500 if (!arm7_9->dcc_working_area) {
501 uint8_t dcc_code_buf[dcc_size];
502
503 /* make sure we have a working area */
504 if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) {
505 LOG_INFO("no working area available, falling back to memory writes");
506 return target_write_memory(target, address, 4, count, buffer);
507 }
508
509 /* copy target instructions to target endianness */
510 for (i = 0; i < dcc_size/4; i++)
511 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
512
513 /* write DCC code to working area */
514 retval = target_write_memory(target,
515 arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf);
516 if (retval != ERROR_OK)
517 return retval;
518 }
519
520 /* backup clobbered processor state */
521 for (i = 0; i <= 5; i++)
522 save[i] = buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32);
523 save[i] = buf_get_u32(arm->pc->value, 0, 32);
524
525 /* set up target address in r0 */
526 buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
527 arm->core_cache->reg_list[0].valid = 1;
528 arm->core_cache->reg_list[0].dirty = 1;
529 arm->core_state = ARM_STATE_ARM;
530
531 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
532 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
533
534 /* send data over */
535 x = 0;
536 flip = 0;
537 shift = 1;
538 for (i = 0; i < count; i++) {
539 uint32_t y = target_buffer_get_u32(target, buffer);
540 uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
541 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
542 x = y << (32 - shift);
543 if (++shift >= 32 || i + 1 >= count) {
544 z = (x >> 1) | (flip ^= 0x80000000);
545 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
546 x = 0;
547 shift = 1;
548 }
549 buffer += 4;
550 }
551
552 retval = target_halt(target);
553 if (retval == ERROR_OK)
554 retval = target_wait_state(target, TARGET_HALTED, 500);
555 if (retval == ERROR_OK) {
556 uint32_t endaddress =
557 buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
558 if (endaddress != address + count*4) {
559 LOG_ERROR("DCC write failed,"
560 " expected end address 0x%08" PRIx32
561 " got 0x%0" PRIx32 "",
562 address + count*4, endaddress);
563 retval = ERROR_FAIL;
564 }
565 }
566
567 /* restore target state */
568 for (i = 0; i <= 5; i++) {
569 buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
570 arm->core_cache->reg_list[i].valid = 1;
571 arm->core_cache->reg_list[i].dirty = 1;
572 }
573 buf_set_u32(arm->pc->value, 0, 32, save[i]);
574 arm->pc->valid = 1;
575 arm->pc->dirty = 1;
576 arm->core_state = core_state;
577
578 return retval;
579 }
580
581 static int feroceon_init_target(struct command_context *cmd_ctx,
582 struct target *target)
583 {
584 arm9tdmi_init_target(cmd_ctx, target);
585 return ERROR_OK;
586 }
587
588 static void feroceon_common_setup(struct target *target)
589 {
590 struct arm *arm = target->arch_info;
591 struct arm7_9_common *arm7_9 = arm->arch_info;
592
593 /* override some insn sequence functions */
594 arm7_9->change_to_arm = feroceon_change_to_arm;
595 arm7_9->read_core_regs = feroceon_read_core_regs;
596 arm7_9->read_core_regs_target_buffer = feroceon_read_core_regs_target_buffer;
597 arm7_9->read_xpsr = feroceon_read_xpsr;
598 arm7_9->write_xpsr = feroceon_write_xpsr;
599 arm7_9->write_xpsr_im8 = feroceon_write_xpsr_im8;
600 arm7_9->write_core_regs = feroceon_write_core_regs;
601 arm7_9->branch_resume = feroceon_branch_resume;
602 arm7_9->branch_resume_thumb = feroceon_branch_resume_thumb;
603
604 /* must be implemented with only one comparator */
605 arm7_9->enable_single_step = feroceon_enable_single_step;
606 arm7_9->disable_single_step = feroceon_disable_single_step;
607
608 /* MOE is not implemented */
609 arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
610
611 /* Note: asserting DBGRQ might not win over the undef exception.
612 If that happens then just use "arm7_9 dbgrq disable". */
613 arm7_9->use_dbgrq = 1;
614 arm7_9->set_special_dbgrq = feroceon_set_dbgrq;
615
616 /* only one working comparator */
617 arm7_9->wp_available_max = 1;
618 arm7_9->wp1_used_default = -1;
619 }
620
621 static int feroceon_target_create(struct target *target, Jim_Interp *interp)
622 {
623 struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common));
624
625 arm926ejs_init_arch_info(target, arm926ejs, target->tap);
626 feroceon_common_setup(target);
627
628 /* the standard ARM926 methods don't always work (don't ask...) */
629 arm926ejs->read_cp15 = feroceon_read_cp15;
630 arm926ejs->write_cp15 = feroceon_write_cp15;
631
632 return ERROR_OK;
633 }
634
635 static int dragonite_target_create(struct target *target, Jim_Interp *interp)
636 {
637 struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common));
638
639 arm966e_init_arch_info(target, arm966e, target->tap);
640 feroceon_common_setup(target);
641
642 return ERROR_OK;
643 }
644
645 static int feroceon_examine(struct target *target)
646 {
647 struct arm *arm;
648 struct arm7_9_common *arm7_9;
649 int retval;
650
651 retval = arm7_9_examine(target);
652 if (retval != ERROR_OK)
653 return retval;
654
655 arm = target->arch_info;
656 arm7_9 = arm->arch_info;
657
658 /* the COMMS_CTRL bits are all contiguous */
659 if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
660 LOG_ERROR("unexpected Feroceon EICE version signature");
661
662 arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
663 arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
664 arm7_9->has_monitor_mode = 1;
665
666 /* vector catch reg is not initialized on reset */
667 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
668
669 /* clear monitor mode, enable comparators */
670 embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
671 jtag_execute_queue();
672 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
673 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
674 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
675
676 return ERROR_OK;
677 }
678
679 struct target_type feroceon_target = {
680 .name = "feroceon",
681
682 .poll = arm7_9_poll,
683 .arch_state = arm926ejs_arch_state,
684
685 .target_request_data = arm7_9_target_request_data,
686
687 .halt = arm7_9_halt,
688 .resume = arm7_9_resume,
689 .step = arm7_9_step,
690
691 .assert_reset = feroceon_assert_reset,
692 .deassert_reset = arm7_9_deassert_reset,
693 .soft_reset_halt = arm926ejs_soft_reset_halt,
694
695 .get_gdb_reg_list = arm_get_gdb_reg_list,
696
697 .read_memory = arm7_9_read_memory,
698 .write_memory = arm926ejs_write_memory,
699 .bulk_write_memory = feroceon_bulk_write_memory,
700
701 .checksum_memory = arm_checksum_memory,
702 .blank_check_memory = arm_blank_check_memory,
703
704 .run_algorithm = armv4_5_run_algorithm,
705
706 .add_breakpoint = arm7_9_add_breakpoint,
707 .remove_breakpoint = arm7_9_remove_breakpoint,
708 .add_watchpoint = arm7_9_add_watchpoint,
709 .remove_watchpoint = arm7_9_remove_watchpoint,
710
711 .commands = arm926ejs_command_handlers,
712 .target_create = feroceon_target_create,
713 .init_target = feroceon_init_target,
714 .examine = feroceon_examine,
715 };
716
717 struct target_type dragonite_target = {
718 .name = "dragonite",
719
720 .poll = arm7_9_poll,
721 .arch_state = arm_arch_state,
722
723 .target_request_data = arm7_9_target_request_data,
724
725 .halt = arm7_9_halt,
726 .resume = arm7_9_resume,
727 .step = arm7_9_step,
728
729 .assert_reset = feroceon_assert_reset,
730 .deassert_reset = arm7_9_deassert_reset,
731 .soft_reset_halt = arm7_9_soft_reset_halt,
732
733 .get_gdb_reg_list = arm_get_gdb_reg_list,
734
735 .read_memory = arm7_9_read_memory,
736 .write_memory = arm7_9_write_memory,
737 .bulk_write_memory = feroceon_bulk_write_memory,
738
739 .checksum_memory = arm_checksum_memory,
740 .blank_check_memory = arm_blank_check_memory,
741
742 .run_algorithm = armv4_5_run_algorithm,
743
744 .add_breakpoint = arm7_9_add_breakpoint,
745 .remove_breakpoint = arm7_9_remove_breakpoint,
746 .add_watchpoint = arm7_9_add_watchpoint,
747 .remove_watchpoint = arm7_9_remove_watchpoint,
748
749 .commands = arm966e_command_handlers,
750 .target_create = dragonite_target_create,
751 .init_target = feroceon_init_target,
752 .examine = feroceon_examine,
753 };
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