Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
- fix mips issues with newer versions of gdb
[openocd.git] / src / target / mips32.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "mips32.h"
30 #include "jtag.h"
31 #include "log.h"
32
33 #include <stdlib.h>
34 #include <string.h>
35
36 char* mips32_core_reg_list[] =
37 {
38 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
39 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
40 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
41 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
42 "status", "lo", "hi", "badvaddr", "cause", "pc"
43 };
44
45 mips32_core_reg_t mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
46 {
47 {0, NULL, NULL},
48 {1, NULL, NULL},
49 {2, NULL, NULL},
50 {3, NULL, NULL},
51 {4, NULL, NULL},
52 {5, NULL, NULL},
53 {6, NULL, NULL},
54 {7, NULL, NULL},
55 {8, NULL, NULL},
56 {9, NULL, NULL},
57 {10, NULL, NULL},
58 {11, NULL, NULL},
59 {12, NULL, NULL},
60 {13, NULL, NULL},
61 {14, NULL, NULL},
62 {15, NULL, NULL},
63 {16, NULL, NULL},
64 {17, NULL, NULL},
65 {18, NULL, NULL},
66 {19, NULL, NULL},
67 {20, NULL, NULL},
68 {21, NULL, NULL},
69 {22, NULL, NULL},
70 {23, NULL, NULL},
71 {24, NULL, NULL},
72 {25, NULL, NULL},
73 {26, NULL, NULL},
74 {27, NULL, NULL},
75 {28, NULL, NULL},
76 {29, NULL, NULL},
77 {30, NULL, NULL},
78 {31, NULL, NULL},
79
80 {32, NULL, NULL},
81 {33, NULL, NULL},
82 {34, NULL, NULL},
83 {35, NULL, NULL},
84 {36, NULL, NULL},
85 {37, NULL, NULL},
86 };
87
88 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
89 * we also add 18 unknown registers to handle gdb requests */
90
91 #define MIPS32NUMFPREGS 34 + 18
92
93 u8 mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
94
95 reg_t mips32_gdb_dummy_fp_reg =
96 {
97 "GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0
98 };
99
100 int mips32_core_reg_arch_type = -1;
101
102 int mips32_get_core_reg(reg_t *reg)
103 {
104 int retval;
105 mips32_core_reg_t *mips32_reg = reg->arch_info;
106 target_t *target = mips32_reg->target;
107 mips32_common_t *mips32_target = target->arch_info;
108
109 if (target->state != TARGET_HALTED)
110 {
111 return ERROR_TARGET_NOT_HALTED;
112 }
113
114 retval = mips32_target->read_core_reg(target, mips32_reg->num);
115
116 return retval;
117 }
118
119 int mips32_set_core_reg(reg_t *reg, u8 *buf)
120 {
121 mips32_core_reg_t *mips32_reg = reg->arch_info;
122 target_t *target = mips32_reg->target;
123 u32 value = buf_get_u32(buf, 0, 32);
124
125 if (target->state != TARGET_HALTED)
126 {
127 return ERROR_TARGET_NOT_HALTED;
128 }
129
130 buf_set_u32(reg->value, 0, 32, value);
131 reg->dirty = 1;
132 reg->valid = 1;
133
134 return ERROR_OK;
135 }
136
137 int mips32_read_core_reg(struct target_s *target, int num)
138 {
139 u32 reg_value;
140 mips32_core_reg_t *mips_core_reg;
141
142 /* get pointers to arch-specific information */
143 mips32_common_t *mips32 = target->arch_info;
144
145 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
146 return ERROR_INVALID_ARGUMENTS;
147
148 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
149 reg_value = mips32->core_regs[num];
150 buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
151 mips32->core_cache->reg_list[num].valid = 1;
152 mips32->core_cache->reg_list[num].dirty = 0;
153
154 return ERROR_OK;
155 }
156
157 int mips32_write_core_reg(struct target_s *target, int num)
158 {
159 u32 reg_value;
160 mips32_core_reg_t *mips_core_reg;
161
162 /* get pointers to arch-specific information */
163 mips32_common_t *mips32 = target->arch_info;
164
165 if ((num < 0) || (num >= MIPS32NUMCOREREGS))
166 return ERROR_INVALID_ARGUMENTS;
167
168 reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
169 mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
170 mips32->core_regs[num] = reg_value;
171 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
172 mips32->core_cache->reg_list[num].valid = 1;
173 mips32->core_cache->reg_list[num].dirty = 0;
174
175 return ERROR_OK;
176 }
177
178 int mips32_invalidate_core_regs(target_t *target)
179 {
180 /* get pointers to arch-specific information */
181 mips32_common_t *mips32 = target->arch_info;
182 int i;
183
184 for (i = 0; i < mips32->core_cache->num_regs; i++)
185 {
186 mips32->core_cache->reg_list[i].valid = 0;
187 mips32->core_cache->reg_list[i].dirty = 0;
188 }
189
190 return ERROR_OK;
191 }
192
193 int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
194 {
195 /* get pointers to arch-specific information */
196 mips32_common_t *mips32 = target->arch_info;
197 int i;
198
199 /* include floating point registers */
200 *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
201 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
202
203 for (i = 0; i < MIPS32NUMCOREREGS; i++)
204 {
205 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
206 }
207
208 /* add dummy floating points regs */
209 for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
210 {
211 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
212 }
213
214 return ERROR_OK;
215 }
216
217 int mips32_save_context(target_t *target)
218 {
219 int i;
220
221 /* get pointers to arch-specific information */
222 mips32_common_t *mips32 = target->arch_info;
223 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
224
225 /* read core registers */
226 mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
227
228 for (i = 0; i < MIPS32NUMCOREREGS; i++)
229 {
230 if (!mips32->core_cache->reg_list[i].valid)
231 {
232 mips32->read_core_reg(target, i);
233 }
234 }
235
236 return ERROR_OK;
237 }
238
239 int mips32_restore_context(target_t *target)
240 {
241 int i;
242
243 /* get pointers to arch-specific information */
244 mips32_common_t *mips32 = target->arch_info;
245 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
246
247 for (i = 0; i < MIPS32NUMCOREREGS; i++)
248 {
249 if (mips32->core_cache->reg_list[i].dirty)
250 {
251 mips32->write_core_reg(target, i);
252 }
253 }
254
255 /* write core regs */
256 mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
257
258 return ERROR_OK;
259 }
260
261 int mips32_arch_state(struct target_s *target)
262 {
263 mips32_common_t *mips32 = target->arch_info;
264
265 if (mips32->common_magic != MIPS32_COMMON_MAGIC)
266 {
267 LOG_ERROR("BUG: called for a non-MIPS32 target");
268 exit(-1);
269 }
270
271 LOG_USER("target halted due to %s, pc: 0x%8.8x",
272 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
273 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
274
275 return ERROR_OK;
276 }
277
278 reg_cache_t *mips32_build_reg_cache(target_t *target)
279 {
280 /* get pointers to arch-specific information */
281 mips32_common_t *mips32 = target->arch_info;
282
283 int num_regs = MIPS32NUMCOREREGS;
284 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
285 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
286 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
287 mips32_core_reg_t *arch_info = malloc(sizeof(mips32_core_reg_t) * num_regs);
288 int i;
289
290 if (mips32_core_reg_arch_type == -1)
291 mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
292
293 register_init_dummy(&mips32_gdb_dummy_fp_reg);
294
295 /* Build the process context cache */
296 cache->name = "mips32 registers";
297 cache->next = NULL;
298 cache->reg_list = reg_list;
299 cache->num_regs = num_regs;
300 (*cache_p) = cache;
301 mips32->core_cache = cache;
302
303 for (i = 0; i < num_regs; i++)
304 {
305 arch_info[i] = mips32_core_reg_list_arch_info[i];
306 arch_info[i].target = target;
307 arch_info[i].mips32_common = mips32;
308 reg_list[i].name = mips32_core_reg_list[i];
309 reg_list[i].size = 32;
310 reg_list[i].value = calloc(1, 4);
311 reg_list[i].dirty = 0;
312 reg_list[i].valid = 0;
313 reg_list[i].bitfield_desc = NULL;
314 reg_list[i].num_bitfields = 0;
315 reg_list[i].arch_type = mips32_core_reg_arch_type;
316 reg_list[i].arch_info = &arch_info[i];
317 }
318
319 return cache;
320 }
321
322 int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap)
323 {
324 target->arch_info = mips32;
325 mips32->common_magic = MIPS32_COMMON_MAGIC;
326
327 /* has breakpoint/watchpint unit been scanned */
328 mips32->bp_scanned = 0;
329 mips32->data_break_list = NULL;
330
331 mips32->ejtag_info.tap = tap;
332 mips32->read_core_reg = mips32_read_core_reg;
333 mips32->write_core_reg = mips32_write_core_reg;
334
335 return ERROR_OK;
336 }
337
338 int mips32_register_commands(struct command_context_s *cmd_ctx)
339 {
340 return ERROR_OK;
341 }
342
343 int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
344 {
345 /*TODO*/
346 return ERROR_OK;
347 }
348
349 int mips32_examine(struct target_s *target)
350 {
351 mips32_common_t *mips32 = target->arch_info;
352
353 if (!target->type->examined)
354 {
355 target->type->examined = 1;
356
357 /* we will configure later */
358 mips32->bp_scanned = 0;
359 mips32->num_inst_bpoints = 0;
360 mips32->num_data_bpoints = 0;
361 mips32->num_inst_bpoints_avail = 0;
362 mips32->num_data_bpoints_avail = 0;
363 }
364
365 return ERROR_OK;
366 }
367
368 int mips32_configure_break_unit(struct target_s *target)
369 {
370 /* get pointers to arch-specific information */
371 mips32_common_t *mips32 = target->arch_info;
372 int retval;
373 u32 dcr, bpinfo;
374 int i;
375
376 if (mips32->bp_scanned)
377 return ERROR_OK;
378
379 /* get info about breakpoint support */
380 if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
381 return retval;
382
383 if (dcr & (1 << 16))
384 {
385 /* get number of inst breakpoints */
386 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
387 return retval;
388
389 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
390 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
391 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(mips32_comparator_t));
392 for (i = 0; i < mips32->num_inst_bpoints; i++)
393 {
394 mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
395 }
396
397 /* clear IBIS reg */
398 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
399 return retval;
400 }
401
402 if (dcr & (1 << 17))
403 {
404 /* get number of data breakpoints */
405 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
406 return retval;
407
408 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
409 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
410 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(mips32_comparator_t));
411 for (i = 0; i < mips32->num_data_bpoints; i++)
412 {
413 mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
414 }
415
416 /* clear DBIS reg */
417 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
418 return retval;
419 }
420
421 LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
422
423 mips32->bp_scanned = 1;
424
425 return ERROR_OK;
426 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)