src/target/mips_ejtag.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "mips32.h"
  30 #include "mips_ejtag.h"
  31
  32 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
  33 {
  34         struct jtag_tap *tap;
  35
  36         tap = ejtag_info->tap;
  37         assert(tap != NULL);
  38
  39         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
  40                 struct scan_field field;
  41                 uint8_t t[4];
  42
  43                 field.num_bits = tap->ir_length;
  44                 field.out_value = t;
  45                 buf_set_u32(t, 0, field.num_bits, new_instr);
  46                 field.in_value = NULL;
  47
  48                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  49         }
  50 }
  51
  52 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  53 {
  54         struct scan_field field;
  55         uint8_t r[4];
  56
  57         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
  58
  59         field.num_bits = 32;
  60         field.out_value = NULL;
  61         field.in_value = r;
  62
  63         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  64
  65         int retval;
  66         retval = jtag_execute_queue();
  67         if (retval != ERROR_OK) {
  68                 LOG_ERROR("register read failed");
  69                 return retval;
  70         }
  71
  72         *idcode = buf_get_u32(field.in_value, 0, 32);
  73
  74         return ERROR_OK;
  75 }
  76
  77 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  78 {
  79         struct scan_field field;
  80         uint8_t r[4];
  81
  82         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
  83
  84         field.num_bits = 32;
  85         field.out_value = NULL;
  86         field.in_value = r;
  87
  88         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  89
  90         int retval;
  91         retval = jtag_execute_queue();
  92         if (retval != ERROR_OK) {
  93                 LOG_ERROR("register read failed");
  94                 return retval;
  95         }
  96
  97         *impcode = buf_get_u32(field.in_value, 0, 32);
  98
  99         return ERROR_OK;
 100 }
 101
 102 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
 103 {
 104         assert(ejtag_info->tap != NULL);
 105         struct jtag_tap *tap = ejtag_info->tap;
 106
 107         struct scan_field field;
 108         uint8_t out_scan[12];
 109
 110         /* processor access "all" register 96 bit */
 111         field.num_bits = 96;
 112
 113         field.out_value = out_scan;
 114         buf_set_u32(out_scan, 0, 32, ctrl);
 115         buf_set_u32(out_scan + 4, 0, 32, data);
 116         buf_set_u32(out_scan + 8, 0, 32, 0);
 117
 118         field.in_value = in_scan_buf;
 119
 120         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 121
 122         keep_alive();
 123 }
 124
 125 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 126 {
 127         struct jtag_tap *tap;
 128         tap  = ejtag_info->tap;
 129         assert(tap != NULL);
 130
 131         struct scan_field field;
 132         uint8_t t[4], r[4];
 133         int retval;
 134
 135         field.num_bits = 32;
 136         field.out_value = t;
 137         buf_set_u32(t, 0, field.num_bits, *data);
 138         field.in_value = r;
 139
 140         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 141
 142         retval = jtag_execute_queue();
 143         if (retval != ERROR_OK) {
 144                 LOG_ERROR("register read failed");
 145                 return retval;
 146         }
 147
 148         *data = buf_get_u32(field.in_value, 0, 32);
 149
 150         keep_alive();
 151
 152         return ERROR_OK;
 153 }
 154
 155 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
 156 {
 157         uint8_t t[4];
 158         struct jtag_tap *tap;
 159         tap  = ejtag_info->tap;
 160         assert(tap != NULL);
 161
 162         struct scan_field field;
 163
 164         field.num_bits = 32;
 165         field.out_value = t;
 166         buf_set_u32(t, 0, field.num_bits, data);
 167
 168         field.in_value = NULL;
 169
 170         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 171 }
 172
 173 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 174 {
 175         struct jtag_tap *tap;
 176         tap  = ejtag_info->tap;
 177         assert(tap != NULL);
 178
 179         struct scan_field field;
 180         uint8_t t[4] = {0, 0, 0, 0}, r[4];
 181         int retval;
 182
 183         field.num_bits = 8;
 184         field.out_value = t;
 185         buf_set_u32(t, 0, field.num_bits, *data);
 186         field.in_value = r;
 187
 188         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 189
 190         retval = jtag_execute_queue();
 191         if (retval != ERROR_OK) {
 192                 LOG_ERROR("register read failed");
 193                 return retval;
 194         }
 195
 196         *data = buf_get_u32(field.in_value, 0, 32);
 197
 198         return ERROR_OK;
 199 }
 200
 201 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
 202 {
 203         struct jtag_tap *tap;
 204         tap  = ejtag_info->tap;
 205         assert(tap != NULL);
 206
 207         struct scan_field field;
 208
 209         field.num_bits = 8;
 210         field.out_value = &data;
 211         field.in_value = NULL;
 212
 213         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 214 }
 215
 216 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
 217 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 218 {
 219         int code_len = enable_step ? 6 : 7;
 220
 221         uint32_t *code = malloc(code_len * sizeof(uint32_t));
 222         if (code == NULL) {
 223                 LOG_ERROR("Out of memory");
 224                 return ERROR_FAIL;
 225         }
 226         uint32_t *code_p = code;
 227
 228         *code_p++ = MIPS32_MTC0(1, 31, 0);                      /* move $1 to COP0 DeSave */
 229         *code_p++ = MIPS32_MFC0(1, 23, 0),                      /* move COP0 Debug to $1 */
 230         *code_p++ = MIPS32_ORI(1, 1, 0x0100);                   /* set SSt bit in debug reg */
 231         if (!enable_step)
 232                 *code_p++ = MIPS32_XORI(1, 1, 0x0100);          /* clear SSt bit in debug reg */
 233
 234         *code_p++ = MIPS32_MTC0(1, 23, 0);                      /* move $1 to COP0 Debug */
 235         *code_p++ = MIPS32_B(NEG16((code_len - 1)));            /* jump to start */
 236         *code_p = MIPS32_MFC0(1, 31, 0);                        /* move COP0 DeSave to $1 */
 237
 238         int retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, 0, NULL, 1);
 239
 240         free(code);
 241         return retval;
 242 }
 243
 244 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 245 {
 246         uint32_t ejtag_ctrl;
 247         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 248
 249         /* set debug break bit */
 250         ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 251         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 252
 253         /* break bit will be cleared by hardware */
 254         ejtag_ctrl = ejtag_info->ejtag_ctrl;
 255         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 256         LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
 257         if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) {
 258                 LOG_ERROR("Failed to enter Debug Mode!");
 259                 return ERROR_FAIL;
 260         }
 261
 262         return ERROR_OK;
 263 }
 264
 265 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 266 {
 267         uint32_t inst;
 268         inst = MIPS32_DRET;
 269
 270         /* execute our dret instruction */
 271         int retval = mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
 272
 273         /* pic32mx workaround, false pending at low core clock */
 274         jtag_add_sleep(1000);
 275
 276         return retval;
 277 }
 278
 279 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 280 {
 281         uint32_t ejtag_version;
 282         int retval;
 283
 284         retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
 285         if (retval != ERROR_OK)
 286                 return retval;
 287         LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
 288
 289         /* get ejtag version */
 290         ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
 291
 292         switch (ejtag_version) {
 293                 case 0:
 294                         LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
 295                         break;
 296                 case 1:
 297                         LOG_DEBUG("EJTAG: Version 2.5 Detected");
 298                         break;
 299                 case 2:
 300                         LOG_DEBUG("EJTAG: Version 2.6 Detected");
 301                         break;
 302                 case 3:
 303                         LOG_DEBUG("EJTAG: Version 3.1 Detected");
 304                         break;
 305                 case 4:
 306                         LOG_DEBUG("EJTAG: Version 4.1 Detected");
 307                         break;
 308                 case 5:
 309                         LOG_DEBUG("EJTAG: Version 5.1 Detected");
 310                         break;
 311                 default:
 312                         LOG_DEBUG("EJTAG: Unknown Version Detected");
 313                         break;
 314         }
 315         LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
 316                 ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
 317                 ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
 318                 ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
 319                 ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
 320                 ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
 321                 ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
 322                 ejtag_info->impcode & EJTAG_DCR_MIPS64  ? " MIPS64" : " MIPS32");
 323
 324         if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
 325                 LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 326
 327         /* set initial state for ejtag control reg */
 328         ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
 329         ejtag_info->fast_access_save = -1;
 330
 331         return ERROR_OK;
 332 }
 333
 334 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
 335 {
 336         struct jtag_tap *tap;
 337
 338         tap = ejtag_info->tap;
 339         assert(tap != NULL);
 340
 341         struct scan_field fields[2];
 342         uint8_t spracc = 0;
 343         uint8_t t[4] = {0, 0, 0, 0};
 344
 345         /* fastdata 1-bit register */
 346         fields[0].num_bits = 1;
 347         fields[0].out_value = &spracc;
 348         fields[0].in_value = NULL;
 349
 350         /* processor access data register 32 bit */
 351         fields[1].num_bits = 32;
 352         fields[1].out_value = t;
 353
 354         if (write_t) {
 355                 fields[1].in_value = NULL;
 356                 buf_set_u32(t, 0, 32, *data);
 357         } else
 358                 fields[1].in_value = (void *) data;
 359
 360         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 361
 362         if (!write_t && data)
 363                 jtag_add_callback(mips_le_to_h_u32,
 364                         (jtag_callback_data_t) data);
 365
 366         keep_alive();
 367
 368         return ERROR_OK;
 369 }