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[openocd.git] / src / target / mips_ejtag.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "mips32.h"
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
30
31 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
32 {
33 assert(ejtag_info->tap != NULL);
34 struct jtag_tap *tap = ejtag_info->tap;
35
36 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
37
38 struct scan_field field;
39 field.num_bits = tap->ir_length;
40
41 uint8_t t[4];
42 field.out_value = t;
43 buf_set_u32(t, 0, field.num_bits, new_instr);
44
45 field.in_value = NULL;
46
47 jtag_add_ir_scan(tap, &field, TAP_IDLE);
48 }
49 }
50
51 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
52 {
53 struct scan_field field;
54 uint8_t r[4];
55
56 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
57
58 field.num_bits = 32;
59 field.out_value = NULL;
60 field.in_value = r;
61
62 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
63
64 int retval;
65 retval = jtag_execute_queue();
66 if (retval != ERROR_OK) {
67 LOG_ERROR("register read failed");
68 return retval;
69 }
70
71 *idcode = buf_get_u32(field.in_value, 0, 32);
72
73 return ERROR_OK;
74 }
75
76 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
77 {
78 struct scan_field field;
79 uint8_t r[4];
80
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
82
83 field.num_bits = 32;
84 field.out_value = NULL;
85 field.in_value = r;
86
87 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
88
89 int retval;
90 retval = jtag_execute_queue();
91 if (retval != ERROR_OK) {
92 LOG_ERROR("register read failed");
93 return retval;
94 }
95
96 *impcode = buf_get_u32(field.in_value, 0, 32);
97
98 return ERROR_OK;
99 }
100
101 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
102 {
103 assert(ejtag_info->tap != NULL);
104 struct jtag_tap *tap = ejtag_info->tap;
105
106 struct scan_field field;
107 uint8_t out_scan[12];
108
109 /* processor access "all" register 96 bit */
110 field.num_bits = 96;
111
112 field.out_value = out_scan;
113 buf_set_u32(out_scan, 0, 32, ctrl);
114 buf_set_u32(out_scan + 4, 0, 32, data);
115 buf_set_u32(out_scan + 8, 0, 32, 0);
116
117 field.in_value = in_scan_buf;
118
119 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
120
121 keep_alive();
122 }
123
124 void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
125 {
126 assert(ejtag_info->tap != NULL);
127 struct jtag_tap *tap = ejtag_info->tap;
128
129 struct scan_field field;
130 field.num_bits = 32;
131
132 uint8_t scan_out[4];
133 field.out_value = scan_out;
134 buf_set_u32(scan_out, 0, field.num_bits, data_out);
135
136 field.in_value = data_in;
137 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
138
139 keep_alive();
140 }
141
142 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
143 {
144 uint8_t scan_in[4];
145 mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
146
147 int retval = jtag_execute_queue();
148 if (retval != ERROR_OK) {
149 LOG_ERROR("register read failed");
150 return retval;
151 }
152
153 *data = buf_get_u32(scan_in, 0, 32);
154 return ERROR_OK;
155 }
156
157 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
158 {
159 mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
160 }
161
162 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
163 {
164 assert(ejtag_info->tap != NULL);
165 struct jtag_tap *tap = ejtag_info->tap;
166
167 struct scan_field field;
168 field.num_bits = 8;
169
170 field.out_value = data;
171 field.in_value = data;
172
173 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
174
175 int retval = jtag_execute_queue();
176 if (retval != ERROR_OK) {
177 LOG_ERROR("register read failed");
178 return retval;
179 }
180 return ERROR_OK;
181 }
182
183 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
184 {
185 assert(ejtag_info->tap != NULL);
186 struct jtag_tap *tap = ejtag_info->tap;
187
188 struct scan_field field;
189 field.num_bits = 8;
190
191 field.out_value = &data;
192 field.in_value = NULL;
193
194 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
195 }
196
197 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
198 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
199 {
200 struct pracc_queue_info ctx = {.max_code = 7};
201 pracc_queue_init(&ctx);
202 if (ctx.retval != ERROR_OK)
203 goto exit;
204
205 pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
206 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
207 if (!enable_step)
208 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
209
210 pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
211 pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
212 pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
213 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
214
215 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
216 exit:
217 pracc_queue_free(&ctx);
218 return ctx.retval;
219 }
220
221 /*
222 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
223 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
224 * For example bcm7401 and others. At leas on some
225 * CPUs, DebugMode wont start if this bit is not removed.
226 */
227 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
228 {
229 uint32_t dcr;
230 int retval;
231
232 retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
233 if (retval != ERROR_OK)
234 goto error;
235
236 dcr &= ~EJTAG_DCR_MP;
237 retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
238 if (retval != ERROR_OK)
239 goto error;
240 return ERROR_OK;
241 error:
242 LOG_ERROR("Failed to remove DCR MPbit!");
243 return retval;
244 }
245
246 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
247 {
248 uint32_t ejtag_ctrl;
249 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
250
251 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
252 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
253 goto error;
254 }
255
256 /* set debug break bit */
257 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
258 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
259
260 /* break bit will be cleared by hardware */
261 ejtag_ctrl = ejtag_info->ejtag_ctrl;
262 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
263 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
264 if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
265 goto error;
266
267 return ERROR_OK;
268 error:
269 LOG_ERROR("Failed to enter Debug Mode!");
270 return ERROR_FAIL;
271 }
272
273 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
274 {
275 pa_list pracc_list = {.instr = MIPS32_DRET, .addr = 0};
276 struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0};
277
278 /* execute our dret instruction */
279 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
280
281 /* pic32mx workaround, false pending at low core clock */
282 jtag_add_sleep(1000);
283 return ctx.retval;
284 }
285
286 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
287 * on EJTAG version.
288 */
289 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
290 {
291 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
292 ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS;
293 ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0;
294 ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS;
295 ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS;
296
297 ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS;
298 ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0;
299 ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS;
300 ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
301 ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
302
303 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
304 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
305 } else {
306 ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
307 ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
308 ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS;
309 ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS;
310 ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS;
311
312 ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS;
313 ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0;
314 ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS;
315 ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS;
316 ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
317 ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
318
319 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
320 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
321 }
322 }
323
324 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
325 {
326 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
327 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
328 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
329 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
330 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
331 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
332 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
333 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
334 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
335 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
336 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
337 EJTAG_V20_IMP_BCHANNELS_MASK));
338 }
339
340 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
341 {
342 LOG_DEBUG("EJTAG v2.6: features:%s%s",
343 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
344 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
345 }
346
347 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
348 {
349 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
350 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
351 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
352 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
353 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
354 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
355
356 switch (ejtag_info->ejtag_version) {
357 case EJTAG_VERSION_20:
358 ejtag_v20_print_imp(ejtag_info);
359 break;
360 case EJTAG_VERSION_25:
361 case EJTAG_VERSION_26:
362 case EJTAG_VERSION_31:
363 case EJTAG_VERSION_41:
364 case EJTAG_VERSION_51:
365 ejtag_v26_print_imp(ejtag_info);
366 break;
367 default:
368 break;
369 }
370 }
371
372 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
373 {
374 int retval;
375
376 retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
377 if (retval != ERROR_OK)
378 return retval;
379 LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
380
381 /* get ejtag version */
382 ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
383
384 switch (ejtag_info->ejtag_version) {
385 case EJTAG_VERSION_20:
386 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
387 break;
388 case EJTAG_VERSION_25:
389 LOG_DEBUG("EJTAG: Version 2.5 Detected");
390 break;
391 case EJTAG_VERSION_26:
392 LOG_DEBUG("EJTAG: Version 2.6 Detected");
393 break;
394 case EJTAG_VERSION_31:
395 LOG_DEBUG("EJTAG: Version 3.1 Detected");
396 break;
397 case EJTAG_VERSION_41:
398 LOG_DEBUG("EJTAG: Version 4.1 Detected");
399 break;
400 case EJTAG_VERSION_51:
401 LOG_DEBUG("EJTAG: Version 5.1 Detected");
402 break;
403 default:
404 LOG_DEBUG("EJTAG: Unknown Version Detected");
405 break;
406 }
407 ejtag_main_print_imp(ejtag_info);
408
409 if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
410 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
411 "workaround current broken code.");
412 ejtag_info->impcode |= EJTAG_IMP_NODMA;
413 }
414
415 ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
416
417 if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
418 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
419
420 ejtag_info->fast_access_save = -1;
421
422 mips_ejtag_init_mmr(ejtag_info);
423
424 return ERROR_OK;
425 }
426
427 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
428 {
429 assert(ejtag_info->tap != NULL);
430 struct jtag_tap *tap = ejtag_info->tap;
431
432 struct scan_field fields[2];
433
434 /* fastdata 1-bit register */
435 fields[0].num_bits = 1;
436
437 uint8_t spracc = 0;
438 fields[0].out_value = &spracc;
439 fields[0].in_value = NULL;
440
441 /* processor access data register 32 bit */
442 fields[1].num_bits = 32;
443
444 uint8_t t[4] = {0, 0, 0, 0};
445 fields[1].out_value = t;
446
447 if (write_t) {
448 fields[1].in_value = NULL;
449 buf_set_u32(t, 0, 32, *data);
450 } else
451 fields[1].in_value = (uint8_t *) data;
452
453 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
454
455 if (!write_t && data)
456 jtag_add_callback(mips_le_to_h_u32,
457 (jtag_callback_data_t) data);
458
459 keep_alive();
460
461 return ERROR_OK;
462 }
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