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[openocd.git] / src / target / mips_ejtag.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
22
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "mips32.h"
28 #include "mips_ejtag.h"
29 #include "mips32_dmaacc.h"
30
31 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
32 {
33 assert(ejtag_info->tap != NULL);
34 struct jtag_tap *tap = ejtag_info->tap;
35
36 if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
37
38 struct scan_field field;
39 field.num_bits = tap->ir_length;
40
41 uint8_t t[4];
42 field.out_value = t;
43 buf_set_u32(t, 0, field.num_bits, new_instr);
44
45 field.in_value = NULL;
46
47 jtag_add_ir_scan(tap, &field, TAP_IDLE);
48 }
49 }
50
51 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
52 {
53 struct scan_field field;
54 uint8_t r[4];
55
56 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
57
58 field.num_bits = 32;
59 field.out_value = NULL;
60 field.in_value = r;
61
62 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
63
64 int retval;
65 retval = jtag_execute_queue();
66 if (retval != ERROR_OK) {
67 LOG_ERROR("register read failed");
68 return retval;
69 }
70
71 *idcode = buf_get_u32(field.in_value, 0, 32);
72
73 return ERROR_OK;
74 }
75
76 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
77 {
78 struct scan_field field;
79 uint8_t r[4];
80
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
82
83 field.num_bits = 32;
84 field.out_value = NULL;
85 field.in_value = r;
86
87 jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
88
89 int retval;
90 retval = jtag_execute_queue();
91 if (retval != ERROR_OK) {
92 LOG_ERROR("register read failed");
93 return retval;
94 }
95
96 *impcode = buf_get_u32(field.in_value, 0, 32);
97
98 return ERROR_OK;
99 }
100
101 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
102 {
103 assert(ejtag_info->tap != NULL);
104 struct jtag_tap *tap = ejtag_info->tap;
105
106 struct scan_field field;
107 uint8_t out_scan[12];
108
109 /* processor access "all" register 96 bit */
110 field.num_bits = 96;
111
112 field.out_value = out_scan;
113 buf_set_u32(out_scan, 0, 32, ctrl);
114 buf_set_u32(out_scan + 4, 0, 32, data);
115 buf_set_u32(out_scan + 8, 0, 32, 0);
116
117 field.in_value = in_scan_buf;
118
119 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
120
121 keep_alive();
122 }
123
124 void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
125 {
126 assert(ejtag_info->tap != NULL);
127 struct jtag_tap *tap = ejtag_info->tap;
128
129 struct scan_field field;
130 field.num_bits = 32;
131
132 uint8_t scan_out[4];
133 field.out_value = scan_out;
134 buf_set_u32(scan_out, 0, field.num_bits, data_out);
135
136 field.in_value = data_in;
137 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
138
139 keep_alive();
140 }
141
142 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
143 {
144 uint8_t scan_in[4];
145 mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
146
147 int retval = jtag_execute_queue();
148 if (retval != ERROR_OK) {
149 LOG_ERROR("register read failed");
150 return retval;
151 }
152
153 *data = buf_get_u32(scan_in, 0, 32);
154 return ERROR_OK;
155 }
156
157 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
158 {
159 mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
160 }
161
162 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
163 {
164 assert(ejtag_info->tap != NULL);
165 struct jtag_tap *tap = ejtag_info->tap;
166
167 struct scan_field field;
168 field.num_bits = 8;
169
170 field.out_value = data;
171 field.in_value = data;
172
173 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
174
175 int retval = jtag_execute_queue();
176 if (retval != ERROR_OK) {
177 LOG_ERROR("register read failed");
178 return retval;
179 }
180 return ERROR_OK;
181 }
182
183 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
184 {
185 assert(ejtag_info->tap != NULL);
186 struct jtag_tap *tap = ejtag_info->tap;
187
188 struct scan_field field;
189 field.num_bits = 8;
190
191 field.out_value = &data;
192 field.in_value = NULL;
193
194 jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
195 }
196
197 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
198 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
199 {
200 struct pracc_queue_info ctx;
201 pracc_queue_init(&ctx);
202
203 pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0)); /* move COP0 Debug to $8 */
204 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100)); /* set SSt bit in debug reg */
205 if (!enable_step)
206 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100)); /* clear SSt bit in debug reg */
207
208 pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0)); /* move $8 to COP0 Debug */
209 pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
210 pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1)))); /* jump to start */
211 pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
212
213 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
214 pracc_queue_free(&ctx);
215 return ctx.retval;
216 }
217
218 /*
219 * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
220 * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
221 * For example bcm7401 and others. At leas on some
222 * CPUs, DebugMode wont start if this bit is not removed.
223 */
224 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
225 {
226 uint32_t dcr;
227 int retval;
228
229 retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
230 if (retval != ERROR_OK)
231 goto error;
232
233 dcr &= ~EJTAG_DCR_MP;
234 retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
235 if (retval != ERROR_OK)
236 goto error;
237 return ERROR_OK;
238 error:
239 LOG_ERROR("Failed to remove DCR MPbit!");
240 return retval;
241 }
242
243 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
244 {
245 uint32_t ejtag_ctrl;
246 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
247
248 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
249 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
250 goto error;
251 }
252
253 /* set debug break bit */
254 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
255 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
256
257 /* break bit will be cleared by hardware */
258 ejtag_ctrl = ejtag_info->ejtag_ctrl;
259 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
260 LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
261 if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
262 goto error;
263
264 return ERROR_OK;
265 error:
266 LOG_ERROR("Failed to enter Debug Mode!");
267 return ERROR_FAIL;
268 }
269
270 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
271 {
272 pa_list pracc_list = {.instr = MIPS32_DRET, .addr = 0};
273 struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0};
274
275 /* execute our dret instruction */
276 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 0);
277
278 /* pic32mx workaround, false pending at low core clock */
279 jtag_add_sleep(1000);
280 return ctx.retval;
281 }
282
283 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
284 * on EJTAG version.
285 */
286 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
287 {
288 if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
289 ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS;
290 ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0;
291 ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS;
292 ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS;
293
294 ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS;
295 ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0;
296 ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS;
297 ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
298 ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
299
300 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
301 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
302 } else {
303 ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
304 ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
305 ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS;
306 ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS;
307 ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS;
308
309 ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS;
310 ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0;
311 ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS;
312 ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS;
313 ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
314 ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
315
316 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
317 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
318 }
319 }
320
321 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
322 {
323 LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
324 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
325 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
326 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
327 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
328 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
329 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
330 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
331 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
332 LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
333 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
334 EJTAG_V20_IMP_BCHANNELS_MASK));
335 }
336
337 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
338 {
339 LOG_DEBUG("EJTAG v2.6: features:%s%s",
340 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
341 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
342 }
343
344 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
345 {
346 LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
347 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
348 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
349 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
350 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
351 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
352
353 switch (ejtag_info->ejtag_version) {
354 case EJTAG_VERSION_20:
355 ejtag_v20_print_imp(ejtag_info);
356 break;
357 case EJTAG_VERSION_25:
358 case EJTAG_VERSION_26:
359 case EJTAG_VERSION_31:
360 case EJTAG_VERSION_41:
361 case EJTAG_VERSION_51:
362 ejtag_v26_print_imp(ejtag_info);
363 break;
364 default:
365 break;
366 }
367 }
368
369 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
370 {
371 int retval;
372
373 retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
374 if (retval != ERROR_OK)
375 return retval;
376 LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
377
378 /* get ejtag version */
379 ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
380
381 switch (ejtag_info->ejtag_version) {
382 case EJTAG_VERSION_20:
383 LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
384 break;
385 case EJTAG_VERSION_25:
386 LOG_DEBUG("EJTAG: Version 2.5 Detected");
387 break;
388 case EJTAG_VERSION_26:
389 LOG_DEBUG("EJTAG: Version 2.6 Detected");
390 break;
391 case EJTAG_VERSION_31:
392 LOG_DEBUG("EJTAG: Version 3.1 Detected");
393 break;
394 case EJTAG_VERSION_41:
395 LOG_DEBUG("EJTAG: Version 4.1 Detected");
396 break;
397 case EJTAG_VERSION_51:
398 LOG_DEBUG("EJTAG: Version 5.1 Detected");
399 break;
400 default:
401 LOG_DEBUG("EJTAG: Unknown Version Detected");
402 break;
403 }
404 ejtag_main_print_imp(ejtag_info);
405
406 if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
407 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
408 "workaround current broken code.");
409 ejtag_info->impcode |= EJTAG_IMP_NODMA;
410 }
411
412 ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
413
414 if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
415 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
416
417 ejtag_info->fast_access_save = -1;
418
419 mips_ejtag_init_mmr(ejtag_info);
420
421 return ERROR_OK;
422 }
423
424 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
425 {
426 assert(ejtag_info->tap != NULL);
427 struct jtag_tap *tap = ejtag_info->tap;
428
429 struct scan_field fields[2];
430
431 /* fastdata 1-bit register */
432 fields[0].num_bits = 1;
433
434 uint8_t spracc = 0;
435 fields[0].out_value = &spracc;
436 fields[0].in_value = NULL;
437
438 /* processor access data register 32 bit */
439 fields[1].num_bits = 32;
440
441 uint8_t t[4] = {0, 0, 0, 0};
442 fields[1].out_value = t;
443
444 if (write_t) {
445 fields[1].in_value = NULL;
446 buf_set_u32(t, 0, 32, *data);
447 } else
448 fields[1].in_value = (uint8_t *) data;
449
450 jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
451
452 if (!write_t && data)
453 jtag_add_callback(mips_le_to_h_u32,
454 (jtag_callback_data_t) data);
455
456 keep_alive();
457
458 return ERROR_OK;
459 }
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