src/target/mips_ejtag.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  19  ***************************************************************************/
  20
  21 #ifndef OPENOCD_TARGET_MIPS_EJTAG_H
  22 #define OPENOCD_TARGET_MIPS_EJTAG_H
  23
  24 #include <jtag/jtag.h>
  25
  26 /* tap instructions */
  27 #define EJTAG_INST_IDCODE               0x01
  28 #define EJTAG_INST_IMPCODE              0x03
  29 #define EJTAG_INST_ADDRESS              0x08
  30 #define EJTAG_INST_DATA                 0x09
  31 #define EJTAG_INST_CONTROL              0x0A
  32 #define EJTAG_INST_ALL                  0x0B
  33 #define EJTAG_INST_EJTAGBOOT    0x0C
  34 #define EJTAG_INST_NORMALBOOT   0x0D
  35 #define EJTAG_INST_FASTDATA             0x0E
  36 #define EJTAG_INST_TCBCONTROLA  0x10
  37 #define EJTAG_INST_TCBCONTROLB  0x11
  38 #define EJTAG_INST_TCBDATA              0x12
  39 #define EJTAG_INST_BYPASS               0xFF
  40
  41 /* microchip PIC32MX specific instructions */
  42 #define MTAP_SW_MTAP                    0x04
  43 #define MTAP_SW_ETAP                    0x05
  44 #define MTAP_COMMAND                    0x07
  45
  46 /* microchip specific cmds */
  47 #define MCHP_ASERT_RST                  0xd1
  48 #define MCHP_DE_ASSERT_RST              0xd0
  49 #define MCHP_ERASE                              0xfc
  50 #define MCHP_STATUS                             0x00
  51
  52 /* ejtag control register bits ECR */
  53 #define EJTAG_CTRL_TOF                  (1 << 1)
  54 #define EJTAG_CTRL_TIF                  (1 << 2)
  55 #define EJTAG_CTRL_BRKST                (1 << 3)
  56 #define EJTAG_CTRL_DLOCK                (1 << 5)
  57 #define EJTAG_CTRL_DRWN                 (1 << 9)
  58 #define EJTAG_CTRL_DERR                 (1 << 10)
  59 #define EJTAG_CTRL_DSTRT                (1 << 11)
  60 #define EJTAG_CTRL_JTAGBRK              (1 << 12)
  61 #define EJTAG_CTRL_SETDEV               (1 << 14)
  62 #define EJTAG_CTRL_PROBEN               (1 << 15)
  63 #define EJTAG_CTRL_PRRST                (1 << 16)
  64 #define EJTAG_CTRL_DMAACC               (1 << 17)
  65 #define EJTAG_CTRL_PRACC                (1 << 18)
  66 #define EJTAG_CTRL_PRNW                 (1 << 19)
  67 #define EJTAG_CTRL_PERRST               (1 << 20)
  68 #define EJTAG_CTRL_SYNC                 (1 << 23)
  69 #define EJTAG_CTRL_DNM                  (1 << 28)
  70 #define EJTAG_CTRL_ROCC                 (1 << 31)
  71
  72 /* Debug Register (CP0 Register 23, Select 0) */
  73
  74 #define EJTAG_DEBUG_DSS                 (1 << 0)
  75 #define EJTAG_DEBUG_DBP                 (1 << 1)
  76 #define EJTAG_DEBUG_DDBL                (1 << 2)
  77 #define EJTAG_DEBUG_DDBS                (1 << 3)
  78 #define EJTAG_DEBUG_DIB                 (1 << 4)
  79 #define EJTAG_DEBUG_DINT                (1 << 5)
  80 #define EJTAG_DEBUG_OFFLINE             (1 << 7)
  81 #define EJTAG_DEBUG_SST                 (1 << 8)
  82 #define EJTAG_DEBUG_NOSST               (1 << 9)
  83 #define EJTAG_DEBUG_DDBLIMPR    (1 << 18)
  84 #define EJTAG_DEBUG_DDBSIMPR    (1 << 19)
  85 #define EJTAG_DEBUG_IEXI                (1 << 20)
  86 #define EJTAG_DEBUG_DBUSEP              (1 << 21)
  87 #define EJTAG_DEBUG_CACHEEP             (1 << 22)
  88 #define EJTAG_DEBUG_MCHECKP             (1 << 23)
  89 #define EJTAG_DEBUG_IBUSEP              (1 << 24)
  90 #define EJTAG_DEBUG_COUNTDM             (1 << 25)
  91 #define EJTAG_DEBUG_HALT                (1 << 26)
  92 #define EJTAG_DEBUG_DOZE                (1 << 27)
  93 #define EJTAG_DEBUG_LSNM                (1 << 28)
  94 #define EJTAG_DEBUG_NODCR               (1 << 29)
  95 #define EJTAG_DEBUG_DM                  (1 << 30)
  96 #define EJTAG_DEBUG_DBD                 (1 << 31)
  97
  98 /* implementation MIPS register bits.
  99  * Bits marked with V20 or v2.0 mean that, this registers supported only
 100  * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
 101  * official EJATG.
 102  * NOTE: Lexra or BMIPS use EJTAG v2.0 */
 103
 104 #define EJTAG_IMP_HAS(x)                        (ejtag_info->impcode & (x))
 105 /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
 106  * overlaps with version bit of MIPS EJTAG specification. */
 107 #define EJTAG_V26_IMP_R3K               (1 << 28)
 108 /* v2.0 - 24:25 - 2’b00- No profiling support */
 109 #define EJTAG_V26_IMP_DINT              (1 << 24)
 110 #define EJTAG_V20_IMP_SDBBP             (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
 111 #define EJTAG_IMP_ASID8                 (1 << 22)
 112 #define EJTAG_IMP_ASID6                 (1 << 21)
 113 #define EJTAG_V20_IMP_COMPLEX_BREAK     (1 << 20) /* Complex Breaks supported*/
 114 #define EJTAG_V20_IMP_EADDR_NO32BIT     (1 << 19) /* EJTAG_ADDR > 32 bits wide */
 115 #define EJTAG_V20_IMP_DCACHE_COH        (1 << 18) /* DCache does keep DMA coherent */
 116 #define EJTAG_V20_IMP_ICACHE_COH        (1 << 17) /* DCache does keep DMA coherent */
 117 #define EJTAG_IMP_MIPS16                (1 << 16)
 118 #define EJTAG_IMP_NODMA                 (1 << 14)
 119 /* v2.0 - 11:13 external PC trace. Trace PC Width. */
 120 /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
 121 #define EJTAG_V20_IMP_NOPB              (1 << 7) /* no processor breaks */
 122 #define EJTAG_V20_IMP_NODB              (1 << 6) /* no data breaks */
 123 #define EJTAG_V20_IMP_NOIB              (1 << 5) /* no instruction breaks implemented */
 124 /* v2.0 - 1:4 Number of Break Channels. */
 125 #define EJTAG_V20_IMP_BCHANNELS_MASK    0xf
 126 #define EJTAG_V20_IMP_BCHANNELS_SHIFT   1
 127 #define EJTAG_DCR_MIPS64                (1 << 0)
 128
 129 /* Debug Control Register DCR */
 130 #define EJTAG_DCR                               0xFF300000
 131 #define EJTAG_DCR_ENM                   (1 << 29)
 132 #define EJTAG_DCR_DB                    (1 << 17)
 133 #define EJTAG_DCR_IB                    (1 << 16)
 134 #define EJTAG_DCR_INTE                  (1 << 4)
 135 #define EJTAG_DCR_MP                    (1 << 2)
 136
 137 /* breakpoint support */
 138 /* EJTAG_V20_* was tested on Broadcom BCM7401
 139  * and may or will differ with other hardware. For example EZ4021-FC. */
 140 #define EJTAG_V20_IBS                   0xFF300004
 141 #define EJTAG_V20_IBA0                  0xFF300100
 142 #define EJTAG_V20_IBC_OFFS              0x4     /* IBC Offset */
 143 #define EJTAG_V20_IBM_OFFS              0x8
 144 #define EJTAG_V20_IBAn_STEP             0x10    /* Offset for next channel */
 145 #define EJTAG_V20_DBS                   0xFF300008
 146 #define EJTAG_V20_DBA0                  0xFF300200
 147 #define EJTAG_V20_DBC_OFFS              0x4
 148 #define EJTAG_V20_DBM_OFFS              0x8
 149 #define EJTAG_V20_DBV_OFFS              0xc
 150 #define EJTAG_V20_DBAn_STEP             0x10
 151
 152 #define EJTAG_V25_IBS                   0xFF301000
 153 #define EJTAG_V25_IBA0                  0xFF301100
 154 #define EJTAG_V25_IBM_OFFS              0x8
 155 #define EJTAG_V25_IBASID_OFFS           0x10
 156 #define EJTAG_V25_IBC_OFFS              0x18
 157 #define EJTAG_V25_IBAn_STEP             0x100
 158 #define EJTAG_V25_DBS                   0xFF302000
 159 #define EJTAG_V25_DBA0                  0xFF302100
 160 #define EJTAG_V25_DBM_OFFS              0x8
 161 #define EJTAG_V25_DBASID_OFFS           0x10
 162 #define EJTAG_V25_DBC_OFFS              0x18
 163 #define EJTAG_V25_DBV_OFFS              0x20
 164 #define EJTAG_V25_DBAn_STEP             0x100
 165
 166 #define EJTAG_DBCn_NOSB                 (1 << 13)
 167 #define EJTAG_DBCn_NOLB                 (1 << 12)
 168 #define EJTAG_DBCn_BLM_MASK             0xff
 169 #define EJTAG_DBCn_BLM_SHIFT    4
 170 #define EJTAG_DBCn_BE                   (1 << 0)
 171
 172 #define EJTAG_VERSION_20                0
 173 #define EJTAG_VERSION_25                1
 174 #define EJTAG_VERSION_26                2
 175 #define EJTAG_VERSION_31                3
 176 #define EJTAG_VERSION_41                4
 177 #define EJTAG_VERSION_51                5
 178
 179 struct mips_ejtag {
 180         struct jtag_tap *tap;
 181         uint32_t impcode;
 182         uint32_t idcode;
 183         uint32_t ejtag_ctrl;
 184         int fast_access_save;
 185         uint32_t reg8;
 186         uint32_t reg9;
 187         unsigned scan_delay;
 188         int mode;
 189         uint32_t pa_ctrl;
 190         uint32_t pa_addr;
 191         unsigned int ejtag_version;
 192
 193         /* Memory-Mapped Registers. This addresses are not same on different
 194          * EJTAG versions. */
 195         uint32_t debug_caps;
 196         uint32_t ejtag_ibs_addr;        /* Instruction Address Break Status */
 197         uint32_t ejtag_iba0_addr;       /* IAB channel 0 */
 198         uint32_t ejtag_ibc_offs;        /* IAB Control offset */
 199         uint32_t ejtag_ibm_offs;        /* IAB Mask offset */
 200         uint32_t ejtag_ibasid_offs;     /* IAB ASID (4Kc) */
 201
 202         uint32_t ejtag_dbs_addr;        /* Data Address Break Status Register */
 203         uint32_t ejtag_dba0_addr;       /* DAB channel 0 */
 204         uint32_t ejtag_dbc_offs;        /* DAB Control offset */
 205         uint32_t ejtag_dbm_offs;        /* DAB Mask offset */
 206         uint32_t ejtag_dbv_offs;        /* DAB Value offset */
 207         uint32_t ejtag_dbasid_offs;     /* DAB ASID (4Kc) */
 208
 209         uint32_t ejtag_iba_step_size;
 210         uint32_t ejtag_dba_step_size;   /* size of step till next *DBAn register. */
 211 };
 212
 213 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
 214 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
 215 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
 216 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
 217 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
 218                             uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
 219 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
 220 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
 221 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
 222 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
 223 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
 224
 225 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
 226 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
 227
 228 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
 229 {
 230         uint8_t *in = (uint8_t *)arg;
 231         *((uint32_t *)arg) = le_to_h_u32(in);
 232 }
 233
 234 #endif /* OPENOCD_TARGET_MIPS_EJTAG_H */