mips_ejtag.c|h: use version specific IMPs
[openocd.git] / src / target / mips_ejtag.h
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
22
23 #ifndef MIPS_EJTAG
24 #define MIPS_EJTAG
25
26 #include <jtag/jtag.h>
27
28 /* tap instructions */
29 #define EJTAG_INST_IDCODE 0x01
30 #define EJTAG_INST_IMPCODE 0x03
31 #define EJTAG_INST_ADDRESS 0x08
32 #define EJTAG_INST_DATA 0x09
33 #define EJTAG_INST_CONTROL 0x0A
34 #define EJTAG_INST_ALL 0x0B
35 #define EJTAG_INST_EJTAGBOOT 0x0C
36 #define EJTAG_INST_NORMALBOOT 0x0D
37 #define EJTAG_INST_FASTDATA 0x0E
38 #define EJTAG_INST_TCBCONTROLA 0x10
39 #define EJTAG_INST_TCBCONTROLB 0x11
40 #define EJTAG_INST_TCBDATA 0x12
41 #define EJTAG_INST_BYPASS 0xFF
42
43 /* microchip PIC32MX specific instructions */
44 #define MTAP_SW_MTAP 0x04
45 #define MTAP_SW_ETAP 0x05
46 #define MTAP_COMMAND 0x07
47
48 /* microchip specific cmds */
49 #define MCHP_ASERT_RST 0xd1
50 #define MCHP_DE_ASSERT_RST 0xd0
51 #define MCHP_ERASE 0xfc
52 #define MCHP_STATUS 0x00
53
54 /* ejtag control register bits ECR */
55 #define EJTAG_CTRL_TOF (1 << 1)
56 #define EJTAG_CTRL_TIF (1 << 2)
57 #define EJTAG_CTRL_BRKST (1 << 3)
58 #define EJTAG_CTRL_DLOCK (1 << 5)
59 #define EJTAG_CTRL_DRWN (1 << 9)
60 #define EJTAG_CTRL_DERR (1 << 10)
61 #define EJTAG_CTRL_DSTRT (1 << 11)
62 #define EJTAG_CTRL_JTAGBRK (1 << 12)
63 #define EJTAG_CTRL_SETDEV (1 << 14)
64 #define EJTAG_CTRL_PROBEN (1 << 15)
65 #define EJTAG_CTRL_PRRST (1 << 16)
66 #define EJTAG_CTRL_DMAACC (1 << 17)
67 #define EJTAG_CTRL_PRACC (1 << 18)
68 #define EJTAG_CTRL_PRNW (1 << 19)
69 #define EJTAG_CTRL_PERRST (1 << 20)
70 #define EJTAG_CTRL_SYNC (1 << 23)
71 #define EJTAG_CTRL_DNM (1 << 28)
72 #define EJTAG_CTRL_ROCC (1 << 31)
73
74 /* Debug Register (CP0 Register 23, Select 0) */
75
76 #define EJTAG_DEBUG_DSS (1 << 0)
77 #define EJTAG_DEBUG_DBP (1 << 1)
78 #define EJTAG_DEBUG_DDBL (1 << 2)
79 #define EJTAG_DEBUG_DDBS (1 << 3)
80 #define EJTAG_DEBUG_DIB (1 << 4)
81 #define EJTAG_DEBUG_DINT (1 << 5)
82 #define EJTAG_DEBUG_OFFLINE (1 << 7)
83 #define EJTAG_DEBUG_SST (1 << 8)
84 #define EJTAG_DEBUG_NOSST (1 << 9)
85 #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
86 #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
87 #define EJTAG_DEBUG_IEXI (1 << 20)
88 #define EJTAG_DEBUG_DBUSEP (1 << 21)
89 #define EJTAG_DEBUG_CACHEEP (1 << 22)
90 #define EJTAG_DEBUG_MCHECKP (1 << 23)
91 #define EJTAG_DEBUG_IBUSEP (1 << 24)
92 #define EJTAG_DEBUG_COUNTDM (1 << 25)
93 #define EJTAG_DEBUG_HALT (1 << 26)
94 #define EJTAG_DEBUG_DOZE (1 << 27)
95 #define EJTAG_DEBUG_LSNM (1 << 28)
96 #define EJTAG_DEBUG_NODCR (1 << 29)
97 #define EJTAG_DEBUG_DM (1 << 30)
98 #define EJTAG_DEBUG_DBD (1 << 31)
99
100 /* implementation MIPS register bits.
101 * Bits marked with V20 or v2.0 mean that, this registers supported only
102 * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
103 * official EJATG.
104 * NOTE: Lexra or BMIPS use EJTAG v2.0 */
105
106 #define EJTAG_IMP_HAS(x) (ejtag_info->impcode & (x))
107 /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
108 * overlaps with version bit of MIPS EJTAG specification. */
109 #define EJTAG_V26_IMP_R3K (1 << 28)
110 /* v2.0 - 24:25 - 2’b00- No profiling support */
111 #define EJTAG_V26_IMP_DINT (1 << 24)
112 #define EJTAG_V20_IMP_SDBBP (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
113 #define EJTAG_IMP_ASID8 (1 << 22)
114 #define EJTAG_IMP_ASID6 (1 << 21)
115 #define EJTAG_V20_IMP_COMPLEX_BREAK (1 << 20) /* Complex Breaks supported*/
116 #define EJTAG_V20_IMP_EADDR_NO32BIT (1 << 19) /* EJTAG_ADDR > 32 bits wide */
117 #define EJTAG_V20_IMP_DCACHE_COH (1 << 18) /* DCache does keep DMA coherent */
118 #define EJTAG_V20_IMP_ICACHE_COH (1 << 17) /* DCache does keep DMA coherent */
119 #define EJTAG_IMP_MIPS16 (1 << 16)
120 #define EJTAG_IMP_NODMA (1 << 14)
121 /* v2.0 - 11:13 external PC trace. Trace PC Width. */
122 /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
123 #define EJTAG_V20_IMP_NOPB (1 << 7) /* no processor breaks */
124 #define EJTAG_V20_IMP_NODB (1 << 6) /* no data breaks */
125 #define EJTAG_V20_IMP_NOIB (1 << 5) /* no instruction breaks implemented */
126 /* v2.0 - 1:4 Number of Break Channels. */
127 #define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
128 #define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
129 #define EJTAG_DCR_MIPS64 (1 << 0)
130
131 /* Debug Control Register DCR */
132 #define EJTAG_DCR 0xFF300000
133 #define EJTAG_DCR_ENM (1 << 29)
134 #define EJTAG_DCR_DB (1 << 17)
135 #define EJTAG_DCR_IB (1 << 16)
136 #define EJTAG_DCR_INTE (1 << 4)
137 #define EJTAG_DCR_MP (1 << 2)
138
139 /* breakpoint support */
140 /* EJTAG_V20_* was tested on Broadcom BCM7401
141 * and may or will differ with other hardware. For example EZ4021-FC. */
142 #define EJTAG_V20_IBS 0xFF300004
143 #define EJTAG_V20_IBA0 0xFF300100
144 #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
145 #define EJTAG_V20_IBM_OFFS 0x8
146 #define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
147 #define EJTAG_V20_DBS 0xFF30008
148 #define EJTAG_V20_DBA0 0xFF300200
149 #define EJTAG_V20_DBC_OFFS 0x4
150 #define EJTAG_V20_DBM_OFFS 0x8
151 #define EJTAG_V20_DBV_OFFS 0xc
152 #define EJTAG_V20_DBAn_STEP 0x10
153
154 #define EJTAG_V25_IBS 0xFF301000
155 #define EJTAG_V25_IBA0 0xFF301100
156 #define EJTAG_V25_IBM_OFFS 0x8
157 #define EJTAG_V25_IBASID_OFFS 0x10
158 #define EJTAG_V25_IBC_OFFS 0x18
159 #define EJTAG_V25_IBAn_STEP 0x100
160 #define EJTAG_V25_DBS 0xFF302000
161 #define EJTAG_V25_DBA0 0xFF302100
162 #define EJTAG_V25_DBM_OFFS 0x8
163 #define EJTAG_V25_DBASID_OFFS 0x10
164 #define EJTAG_V25_DBC_OFFS 0x18
165 #define EJTAG_V25_DBV_OFFS 0x20
166 #define EJTAG_V25_DBAn_STEP 0x100
167
168 #define EJTAG_DBCn_NOSB (1 << 13)
169 #define EJTAG_DBCn_NOLB (1 << 12)
170 #define EJTAG_DBCn_BLM_MASK 0xff
171 #define EJTAG_DBCn_BLM_SHIFT 4
172 #define EJTAG_DBCn_BE (1 << 0)
173
174 #define EJTAG_VERSION_20 0
175 #define EJTAG_VERSION_25 1
176 #define EJTAG_VERSION_26 2
177 #define EJTAG_VERSION_31 3
178 #define EJTAG_VERSION_41 4
179 #define EJTAG_VERSION_51 5
180
181 struct mips_ejtag {
182 struct jtag_tap *tap;
183 uint32_t impcode;
184 uint32_t idcode;
185 uint32_t ejtag_ctrl;
186 int fast_access_save;
187 uint32_t reg8;
188 uint32_t reg9;
189 unsigned scan_delay;
190 int mode;
191 uint32_t pa_ctrl;
192 uint32_t pa_addr;
193 unsigned int ejtag_version;
194
195 /* Memory-Mapped Registers. This addresses are not same on different
196 * EJTAG versions. */
197 uint32_t ejtag_ibs_addr; /* Instruction Address Break Status */
198 uint32_t ejtag_iba0_addr; /* IAB channel 0 */
199 uint32_t ejtag_ibc_offs; /* IAB Control offset */
200 uint32_t ejtag_ibm_offs; /* IAB Mask offset */
201 uint32_t ejtag_ibasid_offs; /* IAB ASID (4Kc) */
202
203 uint32_t ejtag_dbs_addr; /* Data Address Break Status Register */
204 uint32_t ejtag_dba0_addr; /* DAB channel 0 */
205 uint32_t ejtag_dbc_offs; /* DAB Control offset */
206 uint32_t ejtag_dbm_offs; /* DAB Mask offset */
207 uint32_t ejtag_dbv_offs; /* DAB Value offset */
208 uint32_t ejtag_dbasid_offs; /* DAB ASID (4Kc) */
209
210 uint32_t ejtag_iba_step_size;
211 uint32_t ejtag_dba_step_size; /* size of step till next *DBAn register. */
212 };
213
214 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
215 int new_instr);
216 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
217 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
218 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
219 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
220 uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
221 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
222 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
223 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
224 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
225 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
226
227 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
228 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
229
230 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
231 {
232 uint8_t *in = (uint8_t *)arg;
233 *((uint32_t *)arg) = le_to_h_u32(in);
234 }
235
236 #endif /* MIPS_EJTAG */

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