1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "breakpoints.h"
29 #include "mips32_dmaacc.h"
30 #include "target_type.h"
36 /* forward declarations */
37 int mips_m4k_poll(struct target
*target
);
38 int mips_m4k_halt(struct target
*target
);
39 int mips_m4k_soft_reset_halt(struct target
*target
);
40 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
41 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
);
42 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
43 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
44 int mips_m4k_register_commands(struct command_context
*cmd_ctx
);
45 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
);
46 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
);
48 int mips_m4k_examine(struct target
*target
);
49 int mips_m4k_assert_reset(struct target
*target
);
50 int mips_m4k_deassert_reset(struct target
*target
);
51 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
);
53 struct target_type mips_m4k_target
=
57 .poll
= mips_m4k_poll
,
58 .arch_state
= mips32_arch_state
,
60 .target_request_data
= NULL
,
62 .halt
= mips_m4k_halt
,
63 .resume
= mips_m4k_resume
,
64 .step
= mips_m4k_step
,
66 .assert_reset
= mips_m4k_assert_reset
,
67 .deassert_reset
= mips_m4k_deassert_reset
,
68 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
70 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
72 .read_memory
= mips_m4k_read_memory
,
73 .write_memory
= mips_m4k_write_memory
,
74 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
75 .checksum_memory
= mips_m4k_checksum_memory
,
76 .blank_check_memory
= NULL
,
78 .run_algorithm
= mips32_run_algorithm
,
80 .add_breakpoint
= mips_m4k_add_breakpoint
,
81 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
82 .add_watchpoint
= mips_m4k_add_watchpoint
,
83 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
85 .register_commands
= mips_m4k_register_commands
,
86 .target_create
= mips_m4k_target_create
,
87 .init_target
= mips_m4k_init_target
,
88 .examine
= mips_m4k_examine
,
91 int mips_m4k_examine_debug_reason(struct target
*target
)
93 uint32_t break_status
;
96 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
97 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
99 /* get info about inst breakpoint support */
100 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
102 if (break_status
& 0x1f)
104 /* we have halted on a breakpoint */
105 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
107 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
110 /* get info about data breakpoint support */
111 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
113 if (break_status
& 0x1f)
115 /* we have halted on a breakpoint */
116 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
118 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
125 int mips_m4k_debug_entry(struct target
*target
)
127 struct mips32_common
*mips32
= target
->arch_info
;
128 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
131 /* read debug register */
132 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
134 /* make sure break uit configured */
135 mips32_configure_break_unit(target
);
137 /* attempt to find halt reason */
138 mips_m4k_examine_debug_reason(target
);
140 /* clear single step if active */
141 if (debug_reg
& EJTAG_DEBUG_DSS
)
143 /* stopped due to single step - clear step bit */
144 mips_ejtag_config_step(ejtag_info
, 0);
147 mips32_save_context(target
);
149 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
150 *(uint32_t*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
151 target_state_name(target
));
156 int mips_m4k_poll(struct target
*target
)
159 struct mips32_common
*mips32
= target
->arch_info
;
160 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
161 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
163 /* read ejtag control reg */
164 jtag_set_end_state(TAP_IDLE
);
165 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
166 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
168 /* clear this bit before handling polling
169 * as after reset registers will read zero */
170 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
172 /* we have detected a reset, clear flag
173 * otherwise ejtag will not work */
174 jtag_set_end_state(TAP_IDLE
);
175 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
177 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
178 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
179 LOG_DEBUG("Reset Detected");
182 /* check for processor halted */
183 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
185 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
187 jtag_set_end_state(TAP_IDLE
);
188 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
190 target
->state
= TARGET_HALTED
;
192 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
195 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
197 else if (target
->state
== TARGET_DEBUG_RUNNING
)
199 target
->state
= TARGET_HALTED
;
201 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
204 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
209 target
->state
= TARGET_RUNNING
;
212 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
217 int mips_m4k_halt(struct target
*target
)
219 struct mips32_common
*mips32
= target
->arch_info
;
220 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
222 LOG_DEBUG("target->state: %s",
223 target_state_name(target
));
225 if (target
->state
== TARGET_HALTED
)
227 LOG_DEBUG("target was already halted");
231 if (target
->state
== TARGET_UNKNOWN
)
233 LOG_WARNING("target was in unknown state when halt was requested");
236 if (target
->state
== TARGET_RESET
)
238 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
240 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
241 return ERROR_TARGET_FAILURE
;
245 /* we came here in a reset_halt or reset_init sequence
246 * debug entry was already prepared in mips32_prepare_reset_halt()
248 target
->debug_reason
= DBG_REASON_DBGRQ
;
254 /* break processor */
255 mips_ejtag_enter_debug(ejtag_info
);
257 target
->debug_reason
= DBG_REASON_DBGRQ
;
262 int mips_m4k_assert_reset(struct target
*target
)
264 struct mips32_common
*mips32
= target
->arch_info
;
265 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
267 LOG_DEBUG("target->state: %s",
268 target_state_name(target
));
270 enum reset_types jtag_reset_config
= jtag_get_reset_config();
271 if (!(jtag_reset_config
& RESET_HAS_SRST
))
273 LOG_ERROR("Can't assert SRST");
277 if (target
->reset_halt
)
279 /* use hardware to catch reset */
280 jtag_set_end_state(TAP_IDLE
);
281 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
285 jtag_set_end_state(TAP_IDLE
);
286 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
289 if (strcmp(target
->variant
, "ejtag_srst") == 0)
291 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
292 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
293 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
294 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
298 /* here we should issue a srst only, but we may have to assert trst as well */
299 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
301 jtag_add_reset(1, 1);
305 jtag_add_reset(0, 1);
309 target
->state
= TARGET_RESET
;
310 jtag_add_sleep(50000);
312 mips32_invalidate_core_regs(target
);
314 if (target
->reset_halt
)
317 if ((retval
= target_halt(target
)) != ERROR_OK
)
324 int mips_m4k_deassert_reset(struct target
*target
)
326 LOG_DEBUG("target->state: %s",
327 target_state_name(target
));
329 /* deassert reset lines */
330 jtag_add_reset(0, 0);
335 int mips_m4k_soft_reset_halt(struct target
*target
)
341 int mips_m4k_single_step_core(struct target
*target
)
343 struct mips32_common
*mips32
= target
->arch_info
;
344 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
346 /* configure single step mode */
347 mips_ejtag_config_step(ejtag_info
, 1);
349 /* disable interrupts while stepping */
350 mips32_enable_interrupts(target
, 0);
352 /* exit debug mode */
353 mips_ejtag_exit_debug(ejtag_info
);
355 mips_m4k_debug_entry(target
);
360 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
362 struct mips32_common
*mips32
= target
->arch_info
;
363 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
364 struct breakpoint
*breakpoint
= NULL
;
367 if (target
->state
!= TARGET_HALTED
)
369 LOG_WARNING("target not halted");
370 return ERROR_TARGET_NOT_HALTED
;
373 if (!debug_execution
)
375 target_free_all_working_areas(target
);
376 mips_m4k_enable_breakpoints(target
);
377 mips_m4k_enable_watchpoints(target
);
380 /* current = 1: continue on current pc, otherwise continue at <address> */
383 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
384 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
385 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
388 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
390 mips32_restore_context(target
);
392 /* the front-end may request us not to handle breakpoints */
393 if (handle_breakpoints
)
395 /* Single step past breakpoint at current address */
396 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
398 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
399 mips_m4k_unset_breakpoint(target
, breakpoint
);
400 mips_m4k_single_step_core(target
);
401 mips_m4k_set_breakpoint(target
, breakpoint
);
405 /* enable interrupts if we are running */
406 mips32_enable_interrupts(target
, !debug_execution
);
408 /* exit debug mode */
409 mips_ejtag_exit_debug(ejtag_info
);
410 target
->debug_reason
= DBG_REASON_NOTHALTED
;
412 /* registers are now invalid */
413 mips32_invalidate_core_regs(target
);
415 if (!debug_execution
)
417 target
->state
= TARGET_RUNNING
;
418 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
419 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
423 target
->state
= TARGET_DEBUG_RUNNING
;
424 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
425 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
431 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
433 /* get pointers to arch-specific information */
434 struct mips32_common
*mips32
= target
->arch_info
;
435 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
436 struct breakpoint
*breakpoint
= NULL
;
438 if (target
->state
!= TARGET_HALTED
)
440 LOG_WARNING("target not halted");
441 return ERROR_TARGET_NOT_HALTED
;
444 /* current = 1: continue on current pc, otherwise continue at <address> */
446 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
448 /* the front-end may request us not to handle breakpoints */
449 if (handle_breakpoints
)
450 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
451 mips_m4k_unset_breakpoint(target
, breakpoint
);
453 /* restore context */
454 mips32_restore_context(target
);
456 /* configure single step mode */
457 mips_ejtag_config_step(ejtag_info
, 1);
459 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
461 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
463 /* disable interrupts while stepping */
464 mips32_enable_interrupts(target
, 0);
466 /* exit debug mode */
467 mips_ejtag_exit_debug(ejtag_info
);
469 /* registers are now invalid */
470 mips32_invalidate_core_regs(target
);
473 mips_m4k_set_breakpoint(target
, breakpoint
);
475 LOG_DEBUG("target stepped ");
477 mips_m4k_debug_entry(target
);
478 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
483 void mips_m4k_enable_breakpoints(struct target
*target
)
485 struct breakpoint
*breakpoint
= target
->breakpoints
;
487 /* set any pending breakpoints */
490 if (breakpoint
->set
== 0)
491 mips_m4k_set_breakpoint(target
, breakpoint
);
492 breakpoint
= breakpoint
->next
;
496 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
498 struct mips32_common
*mips32
= target
->arch_info
;
499 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
504 LOG_WARNING("breakpoint already set");
508 if (breakpoint
->type
== BKPT_HARD
)
512 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
514 if (bp_num
>= mips32
->num_inst_bpoints
)
516 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
517 breakpoint
->unique_id
);
520 breakpoint
->set
= bp_num
+ 1;
521 comparator_list
[bp_num
].used
= 1;
522 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
523 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
524 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
525 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
526 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
527 breakpoint
->unique_id
,
528 bp_num
, comparator_list
[bp_num
].bp_value
);
530 else if (breakpoint
->type
== BKPT_SOFT
)
532 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
533 if (breakpoint
->length
== 4)
535 uint32_t verify
= 0xffffffff;
537 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
541 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
546 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
550 if (verify
!= MIPS32_SDBBP
)
552 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
558 uint16_t verify
= 0xffff;
560 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
564 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
569 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
573 if (verify
!= MIPS16_SDBBP
)
575 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
580 breakpoint
->set
= 20; /* Any nice value but 0 */
586 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
588 /* get pointers to arch-specific information */
589 struct mips32_common
*mips32
= target
->arch_info
;
590 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
593 if (!breakpoint
->set
)
595 LOG_WARNING("breakpoint not set");
599 if (breakpoint
->type
== BKPT_HARD
)
601 int bp_num
= breakpoint
->set
- 1;
602 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
604 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
605 breakpoint
->unique_id
);
608 LOG_DEBUG("bpid: %d - releasing hw: %d",
609 breakpoint
->unique_id
,
611 comparator_list
[bp_num
].used
= 0;
612 comparator_list
[bp_num
].bp_value
= 0;
613 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
618 /* restore original instruction (kept in target endianness) */
619 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
620 if (breakpoint
->length
== 4)
622 uint32_t current_instr
;
624 /* check that user program has not modified breakpoint instruction */
625 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
629 if (current_instr
== MIPS32_SDBBP
)
631 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
639 uint16_t current_instr
;
641 /* check that user program has not modified breakpoint instruction */
642 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
647 if (current_instr
== MIPS16_SDBBP
)
649 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
661 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
663 struct mips32_common
*mips32
= target
->arch_info
;
665 if (breakpoint
->type
== BKPT_HARD
)
667 if (mips32
->num_inst_bpoints_avail
< 1)
669 LOG_INFO("no hardware breakpoint available");
670 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
673 mips32
->num_inst_bpoints_avail
--;
676 mips_m4k_set_breakpoint(target
, breakpoint
);
681 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
683 /* get pointers to arch-specific information */
684 struct mips32_common
*mips32
= target
->arch_info
;
686 if (target
->state
!= TARGET_HALTED
)
688 LOG_WARNING("target not halted");
689 return ERROR_TARGET_NOT_HALTED
;
694 mips_m4k_unset_breakpoint(target
, breakpoint
);
697 if (breakpoint
->type
== BKPT_HARD
)
698 mips32
->num_inst_bpoints_avail
++;
703 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
705 struct mips32_common
*mips32
= target
->arch_info
;
706 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
709 * watchpoint enabled, ignore all byte lanes in value register
710 * and exclude both load and store accesses from watchpoint
711 * condition evaluation
713 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
714 (0xff << EJTAG_DBCn_BLM_SHIFT
);
718 LOG_WARNING("watchpoint already set");
722 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
724 if (wp_num
>= mips32
->num_data_bpoints
)
726 LOG_ERROR("Can not find free FP Comparator");
730 if (watchpoint
->length
!= 4)
732 LOG_ERROR("Only watchpoints of length 4 are supported");
733 return ERROR_TARGET_UNALIGNED_ACCESS
;
736 if (watchpoint
->address
% 4)
738 LOG_ERROR("Watchpoints address should be word aligned");
739 return ERROR_TARGET_UNALIGNED_ACCESS
;
742 switch (watchpoint
->rw
)
745 enable
&= ~EJTAG_DBCn_NOLB
;
748 enable
&= ~EJTAG_DBCn_NOSB
;
751 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
754 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
757 watchpoint
->set
= wp_num
+ 1;
758 comparator_list
[wp_num
].used
= 1;
759 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
760 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
761 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
762 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
763 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
764 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
765 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
770 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
772 /* get pointers to arch-specific information */
773 struct mips32_common
*mips32
= target
->arch_info
;
774 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
776 if (!watchpoint
->set
)
778 LOG_WARNING("watchpoint not set");
782 int wp_num
= watchpoint
->set
- 1;
783 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
785 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
788 comparator_list
[wp_num
].used
= 0;
789 comparator_list
[wp_num
].bp_value
= 0;
790 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
796 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
798 struct mips32_common
*mips32
= target
->arch_info
;
800 if (mips32
->num_data_bpoints_avail
< 1)
802 LOG_INFO("no hardware watchpoints available");
803 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
806 mips32
->num_data_bpoints_avail
--;
808 mips_m4k_set_watchpoint(target
, watchpoint
);
812 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
814 /* get pointers to arch-specific information */
815 struct mips32_common
*mips32
= target
->arch_info
;
817 if (target
->state
!= TARGET_HALTED
)
819 LOG_WARNING("target not halted");
820 return ERROR_TARGET_NOT_HALTED
;
825 mips_m4k_unset_watchpoint(target
, watchpoint
);
828 mips32
->num_data_bpoints_avail
++;
833 void mips_m4k_enable_watchpoints(struct target
*target
)
835 struct watchpoint
*watchpoint
= target
->watchpoints
;
837 /* set any pending watchpoints */
840 if (watchpoint
->set
== 0)
841 mips_m4k_set_watchpoint(target
, watchpoint
);
842 watchpoint
= watchpoint
->next
;
846 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
848 struct mips32_common
*mips32
= target
->arch_info
;
849 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
851 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
853 if (target
->state
!= TARGET_HALTED
)
855 LOG_WARNING("target not halted");
856 return ERROR_TARGET_NOT_HALTED
;
859 /* sanitize arguments */
860 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
861 return ERROR_INVALID_ARGUMENTS
;
863 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
864 return ERROR_TARGET_UNALIGNED_ACCESS
;
866 /* if noDMA off, use DMAACC mode for memory read */
868 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
869 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
871 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
872 if (ERROR_OK
!= retval
)
878 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
880 struct mips32_common
*mips32
= target
->arch_info
;
881 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
883 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
885 if (target
->state
!= TARGET_HALTED
)
887 LOG_WARNING("target not halted");
888 return ERROR_TARGET_NOT_HALTED
;
891 /* sanitize arguments */
892 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
893 return ERROR_INVALID_ARGUMENTS
;
895 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
896 return ERROR_TARGET_UNALIGNED_ACCESS
;
898 /* if noDMA off, use DMAACC mode for memory write */
899 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
900 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
902 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
905 int mips_m4k_register_commands(struct command_context
*cmd_ctx
)
909 retval
= mips32_register_commands(cmd_ctx
);
913 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
915 mips32_build_reg_cache(target
);
920 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
922 struct mips32_common
*mips32
= &mips_m4k
->mips32_common
;
924 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
926 /* initialize mips4k specific info */
927 mips32_init_arch_info(target
, mips32
, tap
);
928 mips32
->arch_info
= mips_m4k
;
933 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
935 struct mips_m4k_common
*mips_m4k
= calloc(1,sizeof(struct mips_m4k_common
));
937 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
942 int mips_m4k_examine(struct target
*target
)
945 struct mips32_common
*mips32
= target
->arch_info
;
946 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
949 if (!target_was_examined(target
))
951 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
952 ejtag_info
->idcode
= idcode
;
954 if (((idcode
>> 1) & 0x7FF) == 0x29)
956 /* we are using a pic32mx so select ejtag port
957 * as it is not selected by default */
958 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
959 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
963 /* init rest of ejtag interface */
964 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
967 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
973 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
975 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
978 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
)
980 return ERROR_FAIL
; /* use bulk read method */
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