1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
30 #include "breakpoints.h"
33 #include "mips32_dmaacc.h"
34 #include "target_type.h"
37 static void mips_m4k_enable_breakpoints(struct target
*target
);
38 static void mips_m4k_enable_watchpoints(struct target
*target
);
39 static int mips_m4k_set_breakpoint(struct target
*target
,
40 struct breakpoint
*breakpoint
);
41 static int mips_m4k_unset_breakpoint(struct target
*target
,
42 struct breakpoint
*breakpoint
);
43 static int mips_m4k_internal_restore(struct target
*target
, int current
,
44 uint32_t address
, int handle_breakpoints
,
46 static int mips_m4k_halt(struct target
*target
);
47 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
48 uint32_t count
, const uint8_t *buffer
);
50 static int mips_m4k_examine_debug_reason(struct target
*target
)
52 struct mips32_common
*mips32
= target_to_mips32(target
);
53 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
54 uint32_t break_status
;
57 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
58 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
59 if (ejtag_info
->debug_caps
& EJTAG_DCR_IB
) {
60 /* get info about inst breakpoint support */
61 retval
= target_read_u32(target
,
62 ejtag_info
->ejtag_ibs_addr
, &break_status
);
63 if (retval
!= ERROR_OK
)
65 if (break_status
& 0x1f) {
66 /* we have halted on a breakpoint */
67 retval
= target_write_u32(target
,
68 ejtag_info
->ejtag_ibs_addr
, 0);
69 if (retval
!= ERROR_OK
)
71 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
75 if (ejtag_info
->debug_caps
& EJTAG_DCR_DB
) {
76 /* get info about data breakpoint support */
77 retval
= target_read_u32(target
,
78 ejtag_info
->ejtag_dbs_addr
, &break_status
);
79 if (retval
!= ERROR_OK
)
81 if (break_status
& 0x1f) {
82 /* we have halted on a breakpoint */
83 retval
= target_write_u32(target
,
84 ejtag_info
->ejtag_dbs_addr
, 0);
85 if (retval
!= ERROR_OK
)
87 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
95 static int mips_m4k_debug_entry(struct target
*target
)
97 struct mips32_common
*mips32
= target_to_mips32(target
);
98 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
100 mips32_save_context(target
);
102 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
103 mips_ejtag_config_step(ejtag_info
, 0);
105 /* make sure break unit configured */
106 mips32_configure_break_unit(target
);
108 /* attempt to find halt reason */
109 mips_m4k_examine_debug_reason(target
);
111 /* default to mips32 isa, it will be changed below if required */
112 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
114 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
115 mips32
->isa_mode
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1);
117 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
118 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
119 target_state_name(target
));
124 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
126 struct target_list
*head
;
130 while (head
!= (struct target_list
*)NULL
) {
132 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
139 static int mips_m4k_halt_smp(struct target
*target
)
141 int retval
= ERROR_OK
;
142 struct target_list
*head
;
145 while (head
!= (struct target_list
*)NULL
) {
148 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
149 ret
= mips_m4k_halt(curr
);
151 if (ret
!= ERROR_OK
) {
152 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
160 static int update_halt_gdb(struct target
*target
)
162 int retval
= ERROR_OK
;
163 if (target
->gdb_service
->core
[0] == -1) {
164 target
->gdb_service
->target
= target
;
165 target
->gdb_service
->core
[0] = target
->coreid
;
166 retval
= mips_m4k_halt_smp(target
);
171 static int mips_m4k_poll(struct target
*target
)
173 int retval
= ERROR_OK
;
174 struct mips32_common
*mips32
= target_to_mips32(target
);
175 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
176 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
177 enum target_state prev_target_state
= target
->state
;
179 /* toggle to another core is done by gdb as follow */
180 /* maint packet J core_id */
182 /* the next polling trigger an halt event sent to gdb */
183 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
184 (target
->gdb_service
) &&
185 (target
->gdb_service
->target
== NULL
)) {
186 target
->gdb_service
->target
=
187 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
188 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
192 /* read ejtag control reg */
193 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
194 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
195 if (retval
!= ERROR_OK
)
198 /* clear this bit before handling polling
199 * as after reset registers will read zero */
200 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
201 /* we have detected a reset, clear flag
202 * otherwise ejtag will not work */
203 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
205 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
206 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
207 if (retval
!= ERROR_OK
)
209 LOG_DEBUG("Reset Detected");
212 /* check for processor halted */
213 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
214 if ((target
->state
!= TARGET_HALTED
)
215 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
216 if (target
->state
== TARGET_UNKNOWN
)
217 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
219 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
220 * (maybe put on by HALT-ing the board in the previous session).
222 * Force enable debug entry for this session.
224 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
225 target
->state
= TARGET_HALTED
;
226 retval
= mips_m4k_debug_entry(target
);
227 if (retval
!= ERROR_OK
)
231 ((prev_target_state
== TARGET_RUNNING
)
232 || (prev_target_state
== TARGET_RESET
))) {
233 retval
= update_halt_gdb(target
);
234 if (retval
!= ERROR_OK
)
237 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
238 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
239 target
->state
= TARGET_HALTED
;
241 retval
= mips_m4k_debug_entry(target
);
242 if (retval
!= ERROR_OK
)
246 retval
= update_halt_gdb(target
);
247 if (retval
!= ERROR_OK
)
251 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
254 target
->state
= TARGET_RUNNING
;
256 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
261 static int mips_m4k_halt(struct target
*target
)
263 struct mips32_common
*mips32
= target_to_mips32(target
);
264 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
266 LOG_DEBUG("target->state: %s", target_state_name(target
));
268 if (target
->state
== TARGET_HALTED
) {
269 LOG_DEBUG("target was already halted");
273 if (target
->state
== TARGET_UNKNOWN
)
274 LOG_WARNING("target was in unknown state when halt was requested");
276 if (target
->state
== TARGET_RESET
) {
277 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
278 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
279 return ERROR_TARGET_FAILURE
;
281 /* we came here in a reset_halt or reset_init sequence
282 * debug entry was already prepared in mips_m4k_assert_reset()
284 target
->debug_reason
= DBG_REASON_DBGRQ
;
290 /* break processor */
291 mips_ejtag_enter_debug(ejtag_info
);
293 target
->debug_reason
= DBG_REASON_DBGRQ
;
298 static int mips_m4k_assert_reset(struct target
*target
)
300 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
301 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
303 /* TODO: apply hw reset signal in not examined state */
304 if (!(target_was_examined(target
))) {
305 LOG_WARNING("Reset is not asserted because the target is not examined.");
306 LOG_WARNING("Use a reset button or power cycle the target.");
307 return ERROR_TARGET_NOT_EXAMINED
;
310 LOG_DEBUG("target->state: %s",
311 target_state_name(target
));
313 enum reset_types jtag_reset_config
= jtag_get_reset_config();
315 /* some cores support connecting while srst is asserted
316 * use that mode is it has been configured */
318 bool srst_asserted
= false;
320 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
321 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
322 jtag_add_reset(0, 1);
323 srst_asserted
= true;
327 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
328 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
) {
329 if (target
->reset_halt
) {
330 /* use hardware to catch reset */
331 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
333 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
336 if (jtag_reset_config
& RESET_HAS_SRST
) {
337 /* here we should issue a srst only, but we may have to assert trst as well */
338 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
339 jtag_add_reset(1, 1);
340 else if (!srst_asserted
)
341 jtag_add_reset(0, 1);
343 if (mips_m4k
->is_pic32mx
) {
344 LOG_DEBUG("Using MTAP reset to reset processor...");
346 /* use microchip specific MTAP reset */
347 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
348 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
350 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
351 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
352 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
354 /* use ejtag reset - not supported by all cores */
355 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
356 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
357 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
358 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
362 target
->state
= TARGET_RESET
;
363 jtag_add_sleep(50000);
365 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
367 if (target
->reset_halt
) {
368 int retval
= target_halt(target
);
369 if (retval
!= ERROR_OK
)
376 static int mips_m4k_deassert_reset(struct target
*target
)
378 LOG_DEBUG("target->state: %s", target_state_name(target
));
380 /* deassert reset lines */
381 jtag_add_reset(0, 0);
386 static int mips_m4k_single_step_core(struct target
*target
)
388 struct mips32_common
*mips32
= target_to_mips32(target
);
389 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
391 /* configure single step mode */
392 mips_ejtag_config_step(ejtag_info
, 1);
394 /* disable interrupts while stepping */
395 mips32_enable_interrupts(target
, 0);
397 /* exit debug mode */
398 mips_ejtag_exit_debug(ejtag_info
);
400 mips_m4k_debug_entry(target
);
405 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
407 int retval
= ERROR_OK
;
408 struct target_list
*head
;
412 while (head
!= (struct target_list
*)NULL
) {
415 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
416 /* resume current address , not in step mode */
417 ret
= mips_m4k_internal_restore(curr
, 1, address
,
418 handle_breakpoints
, 0);
420 if (ret
!= ERROR_OK
) {
421 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
422 curr
->coreid
, address
);
431 static int mips_m4k_internal_restore(struct target
*target
, int current
,
432 uint32_t address
, int handle_breakpoints
, int debug_execution
)
434 struct mips32_common
*mips32
= target_to_mips32(target
);
435 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
436 struct breakpoint
*breakpoint
= NULL
;
439 if (target
->state
!= TARGET_HALTED
) {
440 LOG_WARNING("target not halted");
441 return ERROR_TARGET_NOT_HALTED
;
444 if (!debug_execution
) {
445 target_free_all_working_areas(target
);
446 mips_m4k_enable_breakpoints(target
);
447 mips_m4k_enable_watchpoints(target
);
450 /* current = 1: continue on current pc, otherwise continue at <address> */
452 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
453 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
454 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
457 if (ejtag_info
->impcode
& EJTAG_IMP_MIPS16
)
458 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
463 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
465 mips32_restore_context(target
);
467 /* the front-end may request us not to handle breakpoints */
468 if (handle_breakpoints
) {
469 /* Single step past breakpoint at current address */
470 breakpoint
= breakpoint_find(target
, resume_pc
);
472 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
"",
473 breakpoint
->address
);
474 mips_m4k_unset_breakpoint(target
, breakpoint
);
475 mips_m4k_single_step_core(target
);
476 mips_m4k_set_breakpoint(target
, breakpoint
);
480 /* enable interrupts if we are running */
481 mips32_enable_interrupts(target
, !debug_execution
);
483 /* exit debug mode */
484 mips_ejtag_exit_debug(ejtag_info
);
485 target
->debug_reason
= DBG_REASON_NOTHALTED
;
487 /* registers are now invalid */
488 register_cache_invalidate(mips32
->core_cache
);
490 if (!debug_execution
) {
491 target
->state
= TARGET_RUNNING
;
492 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
493 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
495 target
->state
= TARGET_DEBUG_RUNNING
;
496 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
497 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
503 static int mips_m4k_resume(struct target
*target
, int current
,
504 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
506 int retval
= ERROR_OK
;
508 /* dummy resume for smp toggle in order to reduce gdb impact */
509 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
510 /* simulate a start and halt of target */
511 target
->gdb_service
->target
= NULL
;
512 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
513 /* fake resume at next poll we play the target core[1], see poll*/
514 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
518 retval
= mips_m4k_internal_restore(target
, current
, address
,
522 if (retval
== ERROR_OK
&& target
->smp
) {
523 target
->gdb_service
->core
[0] = -1;
524 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
530 static int mips_m4k_step(struct target
*target
, int current
,
531 target_addr_t address
, int handle_breakpoints
)
533 /* get pointers to arch-specific information */
534 struct mips32_common
*mips32
= target_to_mips32(target
);
535 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
536 struct breakpoint
*breakpoint
= NULL
;
538 if (target
->state
!= TARGET_HALTED
) {
539 LOG_WARNING("target not halted");
540 return ERROR_TARGET_NOT_HALTED
;
543 /* current = 1: continue on current pc, otherwise continue at <address> */
545 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
546 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
547 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
550 /* the front-end may request us not to handle breakpoints */
551 if (handle_breakpoints
) {
552 breakpoint
= breakpoint_find(target
,
553 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
555 mips_m4k_unset_breakpoint(target
, breakpoint
);
558 /* restore context */
559 mips32_restore_context(target
);
561 /* configure single step mode */
562 mips_ejtag_config_step(ejtag_info
, 1);
564 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
566 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
568 /* disable interrupts while stepping */
569 mips32_enable_interrupts(target
, 0);
571 /* exit debug mode */
572 mips_ejtag_exit_debug(ejtag_info
);
574 /* registers are now invalid */
575 register_cache_invalidate(mips32
->core_cache
);
577 LOG_DEBUG("target stepped ");
578 mips_m4k_debug_entry(target
);
581 mips_m4k_set_breakpoint(target
, breakpoint
);
583 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
588 static void mips_m4k_enable_breakpoints(struct target
*target
)
590 struct breakpoint
*breakpoint
= target
->breakpoints
;
592 /* set any pending breakpoints */
594 if (breakpoint
->set
== 0)
595 mips_m4k_set_breakpoint(target
, breakpoint
);
596 breakpoint
= breakpoint
->next
;
600 static int mips_m4k_set_breakpoint(struct target
*target
,
601 struct breakpoint
*breakpoint
)
603 struct mips32_common
*mips32
= target_to_mips32(target
);
604 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
605 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
608 if (breakpoint
->set
) {
609 LOG_WARNING("breakpoint already set");
613 if (breakpoint
->type
== BKPT_HARD
) {
616 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
618 if (bp_num
>= mips32
->num_inst_bpoints
) {
619 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
620 breakpoint
->unique_id
);
621 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
623 breakpoint
->set
= bp_num
+ 1;
624 comparator_list
[bp_num
].used
= 1;
625 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
627 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
628 * Warning: there is no IB ASID registers in 2.0.
629 * Do not set it! :) */
630 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
631 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
633 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
634 comparator_list
[bp_num
].bp_value
);
635 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
636 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
637 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
638 ejtag_info
->ejtag_ibc_offs
, 1);
639 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
640 breakpoint
->unique_id
,
641 bp_num
, comparator_list
[bp_num
].bp_value
);
642 } else if (breakpoint
->type
== BKPT_SOFT
) {
643 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
644 if (breakpoint
->length
== 4) {
645 uint32_t verify
= 0xffffffff;
647 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
648 breakpoint
->orig_instr
);
649 if (retval
!= ERROR_OK
)
651 retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
);
652 if (retval
!= ERROR_OK
)
655 retval
= target_read_u32(target
, breakpoint
->address
, &verify
);
656 if (retval
!= ERROR_OK
)
658 if (verify
!= MIPS32_SDBBP
) {
659 LOG_ERROR("Unable to set 32-bit breakpoint at address " TARGET_ADDR_FMT
660 " - check that memory is read/writable", breakpoint
->address
);
664 uint16_t verify
= 0xffff;
666 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
667 breakpoint
->orig_instr
);
668 if (retval
!= ERROR_OK
)
670 retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
);
671 if (retval
!= ERROR_OK
)
674 retval
= target_read_u16(target
, breakpoint
->address
, &verify
);
675 if (retval
!= ERROR_OK
)
677 if (verify
!= MIPS16_SDBBP
) {
678 LOG_ERROR("Unable to set 16-bit breakpoint at address " TARGET_ADDR_FMT
679 " - check that memory is read/writable", breakpoint
->address
);
684 breakpoint
->set
= 20; /* Any nice value but 0 */
690 static int mips_m4k_unset_breakpoint(struct target
*target
,
691 struct breakpoint
*breakpoint
)
693 /* get pointers to arch-specific information */
694 struct mips32_common
*mips32
= target_to_mips32(target
);
695 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
696 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
699 if (!breakpoint
->set
) {
700 LOG_WARNING("breakpoint not set");
704 if (breakpoint
->type
== BKPT_HARD
) {
705 int bp_num
= breakpoint
->set
- 1;
706 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
)) {
707 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
708 breakpoint
->unique_id
);
711 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
712 breakpoint
->unique_id
,
714 comparator_list
[bp_num
].used
= 0;
715 comparator_list
[bp_num
].bp_value
= 0;
716 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
717 ejtag_info
->ejtag_ibc_offs
, 0);
720 /* restore original instruction (kept in target endianness) */
721 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
722 if (breakpoint
->length
== 4) {
723 uint32_t current_instr
;
725 /* check that user program has not modified breakpoint instruction */
726 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
727 (uint8_t *)¤t_instr
);
728 if (retval
!= ERROR_OK
)
732 * target_read_memory() gets us data in _target_ endianess.
733 * If we want to use this data on the host for comparisons with some macros
734 * we must first transform it to _host_ endianess using target_buffer_get_u32().
736 current_instr
= target_buffer_get_u32(target
, (uint8_t *)¤t_instr
);
738 if (current_instr
== MIPS32_SDBBP
) {
739 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
740 breakpoint
->orig_instr
);
741 if (retval
!= ERROR_OK
)
745 uint16_t current_instr
;
747 /* check that user program has not modified breakpoint instruction */
748 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
749 (uint8_t *)¤t_instr
);
750 if (retval
!= ERROR_OK
)
752 current_instr
= target_buffer_get_u16(target
, (uint8_t *)¤t_instr
);
753 if (current_instr
== MIPS16_SDBBP
) {
754 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
755 breakpoint
->orig_instr
);
756 if (retval
!= ERROR_OK
)
766 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
768 struct mips32_common
*mips32
= target_to_mips32(target
);
770 if (breakpoint
->type
== BKPT_HARD
) {
771 if (mips32
->num_inst_bpoints_avail
< 1) {
772 LOG_INFO("no hardware breakpoint available");
773 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
776 mips32
->num_inst_bpoints_avail
--;
779 return mips_m4k_set_breakpoint(target
, breakpoint
);
782 static int mips_m4k_remove_breakpoint(struct target
*target
,
783 struct breakpoint
*breakpoint
)
785 /* get pointers to arch-specific information */
786 struct mips32_common
*mips32
= target_to_mips32(target
);
788 if (target
->state
!= TARGET_HALTED
) {
789 LOG_WARNING("target not halted");
790 return ERROR_TARGET_NOT_HALTED
;
794 mips_m4k_unset_breakpoint(target
, breakpoint
);
796 if (breakpoint
->type
== BKPT_HARD
)
797 mips32
->num_inst_bpoints_avail
++;
802 static int mips_m4k_set_watchpoint(struct target
*target
,
803 struct watchpoint
*watchpoint
)
805 struct mips32_common
*mips32
= target_to_mips32(target
);
806 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
807 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
810 * watchpoint enabled, ignore all byte lanes in value register
811 * and exclude both load and store accesses from watchpoint
812 * condition evaluation
814 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
815 (0xff << EJTAG_DBCn_BLM_SHIFT
);
817 if (watchpoint
->set
) {
818 LOG_WARNING("watchpoint already set");
822 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
824 if (wp_num
>= mips32
->num_data_bpoints
) {
825 LOG_ERROR("Can not find free FP Comparator");
829 if (watchpoint
->length
!= 4) {
830 LOG_ERROR("Only watchpoints of length 4 are supported");
831 return ERROR_TARGET_UNALIGNED_ACCESS
;
834 if (watchpoint
->address
% 4) {
835 LOG_ERROR("Watchpoints address should be word aligned");
836 return ERROR_TARGET_UNALIGNED_ACCESS
;
839 switch (watchpoint
->rw
) {
841 enable
&= ~EJTAG_DBCn_NOLB
;
844 enable
&= ~EJTAG_DBCn_NOSB
;
847 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
850 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
853 watchpoint
->set
= wp_num
+ 1;
854 comparator_list
[wp_num
].used
= 1;
855 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
857 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
858 * There is as well no ASID register support. */
859 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
860 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
862 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
863 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
865 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
866 comparator_list
[wp_num
].bp_value
);
867 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
868 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
870 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
871 ejtag_info
->ejtag_dbc_offs
, enable
);
872 /* TODO: probably this value is ignored on 2.0 */
873 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
874 ejtag_info
->ejtag_dbv_offs
, 0);
875 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
880 static int mips_m4k_unset_watchpoint(struct target
*target
,
881 struct watchpoint
*watchpoint
)
883 /* get pointers to arch-specific information */
884 struct mips32_common
*mips32
= target_to_mips32(target
);
885 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
886 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
888 if (!watchpoint
->set
) {
889 LOG_WARNING("watchpoint not set");
893 int wp_num
= watchpoint
->set
- 1;
894 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
)) {
895 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
898 comparator_list
[wp_num
].used
= 0;
899 comparator_list
[wp_num
].bp_value
= 0;
900 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
901 ejtag_info
->ejtag_dbc_offs
, 0);
907 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
909 struct mips32_common
*mips32
= target_to_mips32(target
);
911 if (mips32
->num_data_bpoints_avail
< 1) {
912 LOG_INFO("no hardware watchpoints available");
913 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
916 mips32
->num_data_bpoints_avail
--;
918 mips_m4k_set_watchpoint(target
, watchpoint
);
922 static int mips_m4k_remove_watchpoint(struct target
*target
,
923 struct watchpoint
*watchpoint
)
925 /* get pointers to arch-specific information */
926 struct mips32_common
*mips32
= target_to_mips32(target
);
928 if (target
->state
!= TARGET_HALTED
) {
929 LOG_WARNING("target not halted");
930 return ERROR_TARGET_NOT_HALTED
;
934 mips_m4k_unset_watchpoint(target
, watchpoint
);
936 mips32
->num_data_bpoints_avail
++;
941 static void mips_m4k_enable_watchpoints(struct target
*target
)
943 struct watchpoint
*watchpoint
= target
->watchpoints
;
945 /* set any pending watchpoints */
947 if (watchpoint
->set
== 0)
948 mips_m4k_set_watchpoint(target
, watchpoint
);
949 watchpoint
= watchpoint
->next
;
953 static int mips_m4k_read_memory(struct target
*target
, target_addr_t address
,
954 uint32_t size
, uint32_t count
, uint8_t *buffer
)
956 struct mips32_common
*mips32
= target_to_mips32(target
);
957 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
959 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
960 address
, size
, count
);
962 if (target
->state
!= TARGET_HALTED
) {
963 LOG_WARNING("target not halted");
964 return ERROR_TARGET_NOT_HALTED
;
967 /* sanitize arguments */
968 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
969 return ERROR_COMMAND_SYNTAX_ERROR
;
971 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
972 return ERROR_TARGET_UNALIGNED_ACCESS
;
974 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
978 t
= malloc(count
* size
* sizeof(uint8_t));
980 LOG_ERROR("Out of memory");
986 /* if noDMA off, use DMAACC mode for memory read */
988 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
989 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
991 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
993 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
994 /* endianness, but byte array should represent target endianness */
995 if (ERROR_OK
== retval
) {
998 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1001 target_buffer_set_u16_array(target
, buffer
, count
, t
);
1006 if ((size
> 1) && (t
!= NULL
))
1012 static int mips_m4k_write_memory(struct target
*target
, target_addr_t address
,
1013 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1015 struct mips32_common
*mips32
= target_to_mips32(target
);
1016 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1018 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1019 address
, size
, count
);
1021 if (target
->state
!= TARGET_HALTED
) {
1022 LOG_WARNING("target not halted");
1023 return ERROR_TARGET_NOT_HALTED
;
1026 if (size
== 4 && count
> 32) {
1027 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1028 if (retval
== ERROR_OK
)
1030 LOG_WARNING("Falling back to non-bulk write");
1033 /* sanitize arguments */
1034 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1035 return ERROR_COMMAND_SYNTAX_ERROR
;
1037 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1038 return ERROR_TARGET_UNALIGNED_ACCESS
;
1040 /** correct endianess if we have word or hword access */
1043 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1044 /* endianness, but byte array represents target endianness */
1045 t
= malloc(count
* size
* sizeof(uint8_t));
1047 LOG_ERROR("Out of memory");
1053 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1056 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1062 /* if noDMA off, use DMAACC mode for memory write */
1064 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1065 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1067 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1072 if (ERROR_OK
!= retval
)
1078 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1079 struct target
*target
)
1081 mips32_build_reg_cache(target
);
1086 static int mips_m4k_init_arch_info(struct target
*target
,
1087 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1089 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1091 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1093 /* initialize mips4k specific info */
1094 mips32_init_arch_info(target
, mips32
, tap
);
1095 mips32
->arch_info
= mips_m4k
;
1100 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1102 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1104 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1109 static int mips_m4k_examine(struct target
*target
)
1112 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1113 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1114 uint32_t idcode
= 0;
1116 if (!target_was_examined(target
)) {
1117 retval
= mips_ejtag_get_idcode(ejtag_info
, &idcode
);
1118 if (retval
!= ERROR_OK
)
1120 ejtag_info
->idcode
= idcode
;
1122 if (((idcode
>> 1) & 0x7FF) == 0x29) {
1123 /* we are using a pic32mx so select ejtag port
1124 * as it is not selected by default */
1125 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1126 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1127 mips_m4k
->is_pic32mx
= true;
1131 /* init rest of ejtag interface */
1132 retval
= mips_ejtag_init(ejtag_info
);
1133 if (retval
!= ERROR_OK
)
1136 retval
= mips32_examine(target
);
1137 if (retval
!= ERROR_OK
)
1143 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
1144 uint32_t count
, const uint8_t *buffer
)
1146 struct mips32_common
*mips32
= target_to_mips32(target
);
1147 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1148 struct working_area
*fast_data_area
;
1152 LOG_DEBUG("address: " TARGET_ADDR_FMT
", count: 0x%8.8" PRIx32
"",
1155 /* check alignment */
1157 return ERROR_TARGET_UNALIGNED_ACCESS
;
1159 if (mips32
->fast_data_area
== NULL
) {
1160 /* Get memory for block write handler
1161 * we preserve this area between calls and gain a speed increase
1162 * of about 3kb/sec when writing flash
1163 * this will be released/nulled by the system when the target is resumed or reset */
1164 retval
= target_alloc_working_area(target
,
1165 MIPS32_FASTDATA_HANDLER_SIZE
,
1166 &mips32
->fast_data_area
);
1167 if (retval
!= ERROR_OK
) {
1168 LOG_ERROR("No working area available");
1172 /* reset fastadata state so the algo get reloaded */
1173 ejtag_info
->fast_access_save
= -1;
1176 fast_data_area
= mips32
->fast_data_area
;
1178 if (address
<= fast_data_area
->address
+ fast_data_area
->size
&&
1179 fast_data_area
->address
<= address
+ count
) {
1180 LOG_ERROR("fast_data (" TARGET_ADDR_FMT
") is within write area "
1181 "(" TARGET_ADDR_FMT
"-" TARGET_ADDR_FMT
").",
1182 fast_data_area
->address
, address
, address
+ count
);
1183 LOG_ERROR("Change work-area-phys or load_image address!");
1187 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1188 /* but byte array represents target endianness */
1190 t
= malloc(count
* sizeof(uint32_t));
1192 LOG_ERROR("Out of memory");
1196 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1198 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1204 if (retval
!= ERROR_OK
)
1205 LOG_ERROR("Fastdata access Failed");
1210 static int mips_m4k_verify_pointer(struct command_context
*cmd_ctx
,
1211 struct mips_m4k_common
*mips_m4k
)
1213 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1214 command_print(cmd_ctx
, "target is not an MIPS_M4K");
1215 return ERROR_TARGET_INVALID
;
1220 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1223 struct target
*target
= get_current_target(CMD_CTX
);
1224 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1225 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1227 retval
= mips_m4k_verify_pointer(CMD_CTX
, mips_m4k
);
1228 if (retval
!= ERROR_OK
)
1231 if (target
->state
!= TARGET_HALTED
) {
1232 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1236 /* two or more argument, access a single register/select (write if third argument is given) */
1238 return ERROR_COMMAND_SYNTAX_ERROR
;
1240 uint32_t cp0_reg
, cp0_sel
;
1241 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1242 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1244 if (CMD_ARGC
== 2) {
1246 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1247 if (retval
!= ERROR_OK
) {
1248 command_print(CMD_CTX
,
1249 "couldn't access reg %" PRIi32
,
1253 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1254 cp0_reg
, cp0_sel
, value
);
1256 } else if (CMD_ARGC
== 3) {
1258 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1259 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1260 if (retval
!= ERROR_OK
) {
1261 command_print(CMD_CTX
,
1262 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
1266 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1267 cp0_reg
, cp0_sel
, value
);
1274 COMMAND_HANDLER(mips_m4k_handle_smp_off_command
)
1276 struct target
*target
= get_current_target(CMD_CTX
);
1277 /* check target is an smp target */
1278 struct target_list
*head
;
1279 struct target
*curr
;
1280 head
= target
->head
;
1282 if (head
!= (struct target_list
*)NULL
) {
1283 while (head
!= (struct target_list
*)NULL
) {
1284 curr
= head
->target
;
1288 /* fixes the target display to the debugger */
1289 target
->gdb_service
->target
= target
;
1294 COMMAND_HANDLER(mips_m4k_handle_smp_on_command
)
1296 struct target
*target
= get_current_target(CMD_CTX
);
1297 struct target_list
*head
;
1298 struct target
*curr
;
1299 head
= target
->head
;
1300 if (head
!= (struct target_list
*)NULL
) {
1302 while (head
!= (struct target_list
*)NULL
) {
1303 curr
= head
->target
;
1311 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command
)
1313 struct target
*target
= get_current_target(CMD_CTX
);
1314 int retval
= ERROR_OK
;
1315 struct target_list
*head
;
1316 head
= target
->head
;
1317 if (head
!= (struct target_list
*)NULL
) {
1318 if (CMD_ARGC
== 1) {
1320 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
1321 if (ERROR_OK
!= retval
)
1323 target
->gdb_service
->core
[1] = coreid
;
1326 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
1327 , target
->gdb_service
->core
[1]);
1332 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1334 struct target
*target
= get_current_target(CMD_CTX
);
1335 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1336 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1339 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1340 else if (CMD_ARGC
> 1)
1341 return ERROR_COMMAND_SYNTAX_ERROR
;
1343 command_print(CMD_CTX
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1344 if (ejtag_info
->scan_delay
>= MIPS32_SCAN_DELAY_LEGACY_MODE
) {
1345 ejtag_info
->mode
= 0;
1346 command_print(CMD_CTX
, "running in legacy mode");
1348 ejtag_info
->mode
= 1;
1349 command_print(CMD_CTX
, "running in fast queued mode");
1355 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1358 .handler
= mips_m4k_handle_cp0_command
,
1359 .mode
= COMMAND_EXEC
,
1360 .usage
= "regnum [value]",
1361 .help
= "display/modify cp0 register",
1365 .handler
= mips_m4k_handle_smp_off_command
,
1366 .mode
= COMMAND_EXEC
,
1367 .help
= "Stop smp handling",
1372 .handler
= mips_m4k_handle_smp_on_command
,
1373 .mode
= COMMAND_EXEC
,
1374 .help
= "Restart smp handling",
1379 .handler
= mips_m4k_handle_smp_gdb_command
,
1380 .mode
= COMMAND_EXEC
,
1381 .help
= "display/fix current core played to gdb",
1385 .name
= "scan_delay",
1386 .handler
= mips_m4k_handle_scan_delay_command
,
1387 .mode
= COMMAND_ANY
,
1388 .help
= "display/set scan delay in nano seconds",
1391 COMMAND_REGISTRATION_DONE
1394 const struct command_registration mips_m4k_command_handlers
[] = {
1396 .chain
= mips32_command_handlers
,
1400 .mode
= COMMAND_ANY
,
1401 .help
= "mips_m4k command group",
1403 .chain
= mips_m4k_exec_command_handlers
,
1405 COMMAND_REGISTRATION_DONE
1408 struct target_type mips_m4k_target
= {
1411 .poll
= mips_m4k_poll
,
1412 .arch_state
= mips32_arch_state
,
1414 .halt
= mips_m4k_halt
,
1415 .resume
= mips_m4k_resume
,
1416 .step
= mips_m4k_step
,
1418 .assert_reset
= mips_m4k_assert_reset
,
1419 .deassert_reset
= mips_m4k_deassert_reset
,
1421 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1423 .read_memory
= mips_m4k_read_memory
,
1424 .write_memory
= mips_m4k_write_memory
,
1425 .checksum_memory
= mips32_checksum_memory
,
1426 .blank_check_memory
= mips32_blank_check_memory
,
1428 .run_algorithm
= mips32_run_algorithm
,
1430 .add_breakpoint
= mips_m4k_add_breakpoint
,
1431 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1432 .add_watchpoint
= mips_m4k_add_watchpoint
,
1433 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1435 .commands
= mips_m4k_command_handlers
,
1436 .target_create
= mips_m4k_target_create
,
1437 .init_target
= mips_m4k_init_target
,
1438 .examine
= mips_m4k_examine
,
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