1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
36 /* forward declarations */
37 int mips_m4k_poll(target_t
*target
);
38 int mips_m4k_halt(struct target_s
*target
);
39 int mips_m4k_soft_reset_halt(struct target_s
*target
);
40 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
41 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
42 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
43 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
44 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
45 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int mips_m4k_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
49 int mips_m4k_examine(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
50 int mips_m4k_assert_reset(target_t
*target
);
51 int mips_m4k_deassert_reset(target_t
*target
);
53 target_type_t mips_m4k_target
=
57 .poll
= mips_m4k_poll
,
58 .arch_state
= mips32_arch_state
,
60 .target_request_data
= NULL
,
62 .halt
= mips_m4k_halt
,
63 .resume
= mips_m4k_resume
,
64 .step
= mips_m4k_step
,
66 .assert_reset
= mips_m4k_assert_reset
,
67 .deassert_reset
= mips_m4k_deassert_reset
,
68 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
70 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
72 .read_memory
= mips_m4k_read_memory
,
73 .write_memory
= mips_m4k_write_memory
,
74 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
75 .checksum_memory
= NULL
,
76 .blank_check_memory
= NULL
,
78 .run_algorithm
= mips32_run_algorithm
,
80 .add_breakpoint
= mips_m4k_add_breakpoint
,
81 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
82 .add_watchpoint
= mips_m4k_add_watchpoint
,
83 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
85 .register_commands
= mips_m4k_register_commands
,
86 .target_command
= mips_m4k_target_command
,
87 .init_target
= mips_m4k_init_target
,
88 .examine
= mips_m4k_examine
,
92 int mips_m4k_debug_entry(target_t
*target
)
95 mips32_common_t
*mips32
= target
->arch_info
;
96 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
98 /* read debug register */
99 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
101 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
102 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
104 // if (cortex_m3->nvic_dfsr & DFSR_BKPT)
106 // target->debug_reason = DBG_REASON_BREAKPOINT;
107 // if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
108 // target->debug_reason = DBG_REASON_WPTANDBKPT;
110 // else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
111 // target->debug_reason = DBG_REASON_WATCHPOINT;
114 if (debug_reg
& EJTAG_DEBUG_DSS
)
116 /* stopped due to single step - clear step bit */
117 mips_ejtag_config_step(ejtag_info
, 0);
120 mips32_save_context(target
);
122 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", \
123 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
), target_state_strings
[target
->state
]);
128 int mips_m4k_poll(target_t
*target
)
131 mips32_common_t
*mips32
= target
->arch_info
;
132 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
134 /* read ejtag control reg */
135 jtag_add_end_state(TAP_RTI
);
136 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
137 mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->ejtag_ctrl
);
139 if (ejtag_info
->ejtag_ctrl
& EJTAG_CTRL_BRKST
)
141 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
143 jtag_add_end_state(TAP_RTI
);
144 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
146 target
->state
= TARGET_HALTED
;
148 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
151 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
153 else if (target
->state
== TARGET_DEBUG_RUNNING
)
155 target
->state
= TARGET_HALTED
;
157 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
160 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
165 target
->state
= TARGET_RUNNING
;
168 if (ejtag_info
->ejtag_ctrl
& EJTAG_CTRL_ROCC
)
170 /* we have detected a reset, clear flag
171 * otherwise ejtag will not work */
172 jtag_add_end_state(TAP_RTI
);
173 ejtag_info
->ejtag_ctrl
&= ~EJTAG_CTRL_ROCC
;
175 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
176 mips_ejtag_drscan_32(ejtag_info
, &ejtag_info
->ejtag_ctrl
);
177 LOG_DEBUG("Reset Detected");
180 // LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
185 int mips_m4k_halt(struct target_s
*target
)
187 mips32_common_t
*mips32
= target
->arch_info
;
188 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
190 LOG_DEBUG("target->state: %s", target_state_strings
[target
->state
]);
192 if (target
->state
== TARGET_HALTED
)
194 LOG_DEBUG("target was already halted");
198 if (target
->state
== TARGET_UNKNOWN
)
200 LOG_WARNING("target was in unknown state when halt was requested");
203 if (target
->state
== TARGET_RESET
)
205 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
207 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
208 return ERROR_TARGET_FAILURE
;
212 /* we came here in a reset_halt or reset_init sequence
213 * debug entry was already prepared in mips32_prepare_reset_halt()
215 target
->debug_reason
= DBG_REASON_DBGRQ
;
221 /* break processor */
222 mips_ejtag_enter_debug(ejtag_info
);
224 target
->debug_reason
= DBG_REASON_DBGRQ
;
229 int mips_m4k_assert_reset(target_t
*target
)
231 mips32_common_t
*mips32
= target
->arch_info
;
232 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
234 LOG_DEBUG("target->state: %s", target_state_strings
[target
->state
]);
236 if (!(jtag_reset_config
& RESET_HAS_SRST
))
238 LOG_ERROR("Can't assert SRST");
242 if (target
->reset_halt
)
244 /* use hardware to catch reset */
245 jtag_add_end_state(TAP_RTI
);
246 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
250 jtag_add_end_state(TAP_RTI
);
251 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
254 /* here we should issue a srst only, but we may have to assert trst as well */
255 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
257 jtag_add_reset(1, 1);
261 jtag_add_reset(0, 1);
264 target
->state
= TARGET_RESET
;
265 jtag_add_sleep(50000);
267 mips32_invalidate_core_regs(target
);
272 int mips_m4k_deassert_reset(target_t
*target
)
274 LOG_DEBUG("target->state: %s", target_state_strings
[target
->state
]);
276 /* deassert reset lines */
277 jtag_add_reset(0, 0);
282 int mips_m4k_soft_reset_halt(struct target_s
*target
)
288 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
290 mips32_common_t
*mips32
= target
->arch_info
;
291 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
292 breakpoint_t
*breakpoint
= NULL
;
295 if (target
->state
!= TARGET_HALTED
)
297 LOG_WARNING("target not halted");
298 return ERROR_TARGET_NOT_HALTED
;
301 if (!debug_execution
)
303 target_free_all_working_areas(target
);
304 mips_m4k_enable_breakpoints(target
);
305 mips_m4k_enable_watchpoints(target
);
308 /* current = 1: continue on current pc, otherwise continue at <address> */
311 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
312 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
313 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
316 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
318 mips32_restore_context(target
);
320 /* the front-end may request us not to handle breakpoints */
321 if (handle_breakpoints
)
323 /* Single step past breakpoint at current address */
324 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
326 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
327 mips_m4k_unset_breakpoint(target
, breakpoint
);
328 //mips_m4k_single_step_core(target);
329 mips_m4k_set_breakpoint(target
, breakpoint
);
333 /* exit debug mode - enable interrupts if required */
334 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
336 /* registers are now invalid */
337 mips32_invalidate_core_regs(target
);
339 if (!debug_execution
)
341 target
->state
= TARGET_RUNNING
;
342 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
343 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
347 target
->state
= TARGET_DEBUG_RUNNING
;
348 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
349 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
355 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
357 /* get pointers to arch-specific information */
358 mips32_common_t
*mips32
= target
->arch_info
;
359 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
360 breakpoint_t
*breakpoint
= NULL
;
362 if (target
->state
!= TARGET_HALTED
)
364 LOG_WARNING("target not halted");
365 return ERROR_TARGET_NOT_HALTED
;
368 /* current = 1: continue on current pc, otherwise continue at <address> */
370 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
372 /* the front-end may request us not to handle breakpoints */
373 if (handle_breakpoints
)
374 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
375 mips_m4k_unset_breakpoint(target
, breakpoint
);
377 /* restore context */
378 mips32_restore_context(target
);
380 /* configure single step mode */
381 mips_ejtag_config_step(ejtag_info
, 1);
383 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
385 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
387 /* exit debug mode */
388 mips_ejtag_exit_debug(ejtag_info
, 1);
390 /* registers are now invalid */
391 mips32_invalidate_core_regs(target
);
394 mips_m4k_set_breakpoint(target
, breakpoint
);
396 LOG_DEBUG("target stepped ");
398 mips_m4k_debug_entry(target
);
399 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
404 void mips_m4k_enable_breakpoints(struct target_s
*target
)
406 breakpoint_t
*breakpoint
= target
->breakpoints
;
408 /* set any pending breakpoints */
411 if (breakpoint
->set
== 0)
412 mips_m4k_set_breakpoint(target
, breakpoint
);
413 breakpoint
= breakpoint
->next
;
417 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
423 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
429 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
435 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
441 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
447 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
453 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
459 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
465 void mips_m4k_enable_watchpoints(struct target_s
*target
)
467 watchpoint_t
*watchpoint
= target
->watchpoints
;
469 /* set any pending watchpoints */
472 if (watchpoint
->set
== 0)
473 mips_m4k_set_watchpoint(target
, watchpoint
);
474 watchpoint
= watchpoint
->next
;
478 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
480 mips32_common_t
*mips32
= target
->arch_info
;
481 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
483 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
485 if (target
->state
!= TARGET_HALTED
)
487 LOG_WARNING("target not halted");
488 return ERROR_TARGET_NOT_HALTED
;
491 /* sanitize arguments */
492 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
493 return ERROR_INVALID_ARGUMENTS
;
495 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
496 return ERROR_TARGET_UNALIGNED_ACCESS
;
503 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
505 LOG_ERROR("BUG: we shouldn't get here");
513 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
515 mips32_common_t
*mips32
= target
->arch_info
;
516 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
518 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
520 if (target
->state
!= TARGET_HALTED
)
522 LOG_WARNING("target not halted");
523 return ERROR_TARGET_NOT_HALTED
;
526 /* sanitize arguments */
527 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
528 return ERROR_INVALID_ARGUMENTS
;
530 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
531 return ERROR_TARGET_UNALIGNED_ACCESS
;
538 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
541 LOG_ERROR("BUG: we shouldn't get here");
549 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
553 retval
= mips32_register_commands(cmd_ctx
);
557 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
559 mips32_build_reg_cache(target
);
569 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, int chain_pos
, char *variant
)
571 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
575 mips_m4k
->variant
= strdup(variant
);
579 mips_m4k
->variant
= strdup("");
582 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
584 /* initialize mips4k specific info */
585 mips32_init_arch_info(target
, mips32
, chain_pos
, variant
);
586 mips32
->arch_info
= mips_m4k
;
591 int mips_m4k_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
594 char *variant
= NULL
;
595 mips_m4k_common_t
*mips_m4k
= malloc(sizeof(mips_m4k_common_t
));
599 LOG_ERROR("'target mips4k' requires at least one additional argument");
603 chain_pos
= strtoul(args
[3], NULL
, 0);
608 mips_m4k_init_arch_info(target
, mips_m4k
, chain_pos
, variant
);
613 int mips_m4k_examine(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
616 mips32_common_t
*mips32
= target
->arch_info
;
617 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
620 target
->type
->examined
= 1;
622 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
624 if (((idcode
>> 1) & 0x7FF) == 0x29)
626 /* we are using a pic32mx so select ejtag port
627 * as it is not selected by default */
628 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
629 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
632 /* init rest of ejtag interface */
633 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
639 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
641 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
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