1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
37 /* forward declarations */
38 int mips_m4k_poll(target_t
*target
);
39 int mips_m4k_halt(struct target_s
*target
);
40 int mips_m4k_soft_reset_halt(struct target_s
*target
);
41 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
44 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
45 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
46 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int mips_m4k_quit(void);
48 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
50 int mips_m4k_examine(struct target_s
*target
);
51 int mips_m4k_assert_reset(target_t
*target
);
52 int mips_m4k_deassert_reset(target_t
*target
);
54 target_type_t mips_m4k_target
=
58 .poll
= mips_m4k_poll
,
59 .arch_state
= mips32_arch_state
,
61 .target_request_data
= NULL
,
63 .halt
= mips_m4k_halt
,
64 .resume
= mips_m4k_resume
,
65 .step
= mips_m4k_step
,
67 .assert_reset
= mips_m4k_assert_reset
,
68 .deassert_reset
= mips_m4k_deassert_reset
,
69 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
71 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
73 .read_memory
= mips_m4k_read_memory
,
74 .write_memory
= mips_m4k_write_memory
,
75 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
76 .checksum_memory
= NULL
,
77 .blank_check_memory
= NULL
,
79 .run_algorithm
= mips32_run_algorithm
,
81 .add_breakpoint
= mips_m4k_add_breakpoint
,
82 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
83 .add_watchpoint
= mips_m4k_add_watchpoint
,
84 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
86 .register_commands
= mips_m4k_register_commands
,
87 .target_create
= mips_m4k_target_create
,
88 .init_target
= mips_m4k_init_target
,
89 .examine
= mips_m4k_examine
,
93 int mips_m4k_debug_entry(target_t
*target
)
96 mips32_common_t
*mips32
= target
->arch_info
;
97 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
99 /* read debug register */
100 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
102 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
103 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
105 // if (cortex_m3->nvic_dfsr & DFSR_BKPT)
107 // target->debug_reason = DBG_REASON_BREAKPOINT;
108 // if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
109 // target->debug_reason = DBG_REASON_WPTANDBKPT;
111 // else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
112 // target->debug_reason = DBG_REASON_WATCHPOINT;
115 if (debug_reg
& EJTAG_DEBUG_DSS
)
117 /* stopped due to single step - clear step bit */
118 mips_ejtag_config_step(ejtag_info
, 0);
121 mips32_save_context(target
);
123 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
124 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
125 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
130 int mips_m4k_poll(target_t
*target
)
133 mips32_common_t
*mips32
= target
->arch_info
;
134 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
135 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
137 /* read ejtag control reg */
138 jtag_add_end_state(TAP_RTI
);
139 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
140 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
142 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
144 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
146 jtag_add_end_state(TAP_RTI
);
147 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
149 target
->state
= TARGET_HALTED
;
151 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
154 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
156 else if (target
->state
== TARGET_DEBUG_RUNNING
)
158 target
->state
= TARGET_HALTED
;
160 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
163 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
168 target
->state
= TARGET_RUNNING
;
171 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
173 /* we have detected a reset, clear flag
174 * otherwise ejtag will not work */
175 jtag_add_end_state(TAP_RTI
);
176 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
178 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
179 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
180 LOG_DEBUG("Reset Detected");
183 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
188 int mips_m4k_halt(struct target_s
*target
)
190 mips32_common_t
*mips32
= target
->arch_info
;
191 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
193 LOG_DEBUG("target->state: %s",
194 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
196 if (target
->state
== TARGET_HALTED
)
198 LOG_DEBUG("target was already halted");
202 if (target
->state
== TARGET_UNKNOWN
)
204 LOG_WARNING("target was in unknown state when halt was requested");
207 if (target
->state
== TARGET_RESET
)
209 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
211 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
212 return ERROR_TARGET_FAILURE
;
216 /* we came here in a reset_halt or reset_init sequence
217 * debug entry was already prepared in mips32_prepare_reset_halt()
219 target
->debug_reason
= DBG_REASON_DBGRQ
;
225 /* break processor */
226 mips_ejtag_enter_debug(ejtag_info
);
228 target
->debug_reason
= DBG_REASON_DBGRQ
;
233 int mips_m4k_assert_reset(target_t
*target
)
235 mips32_common_t
*mips32
= target
->arch_info
;
236 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
238 LOG_DEBUG("target->state: %s",
239 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
241 if (!(jtag_reset_config
& RESET_HAS_SRST
))
243 LOG_ERROR("Can't assert SRST");
247 if (target
->reset_halt
)
249 /* use hardware to catch reset */
250 jtag_add_end_state(TAP_RTI
);
251 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
255 jtag_add_end_state(TAP_RTI
);
256 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
259 /* here we should issue a srst only, but we may have to assert trst as well */
260 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
262 jtag_add_reset(1, 1);
266 jtag_add_reset(0, 1);
269 target
->state
= TARGET_RESET
;
270 jtag_add_sleep(50000);
272 mips32_invalidate_core_regs(target
);
274 if (target
->reset_halt
)
277 if ((retval
= target_halt(target
))!=ERROR_OK
)
285 int mips_m4k_deassert_reset(target_t
*target
)
287 LOG_DEBUG("target->state: %s",
288 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
290 /* deassert reset lines */
291 jtag_add_reset(0, 0);
296 int mips_m4k_soft_reset_halt(struct target_s
*target
)
302 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
304 mips32_common_t
*mips32
= target
->arch_info
;
305 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
306 breakpoint_t
*breakpoint
= NULL
;
309 if (target
->state
!= TARGET_HALTED
)
311 LOG_WARNING("target not halted");
312 return ERROR_TARGET_NOT_HALTED
;
315 if (!debug_execution
)
317 target_free_all_working_areas(target
);
318 mips_m4k_enable_breakpoints(target
);
319 mips_m4k_enable_watchpoints(target
);
322 /* current = 1: continue on current pc, otherwise continue at <address> */
325 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
326 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
327 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
330 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
332 mips32_restore_context(target
);
334 /* the front-end may request us not to handle breakpoints */
335 if (handle_breakpoints
)
337 /* Single step past breakpoint at current address */
338 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
340 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
341 mips_m4k_unset_breakpoint(target
, breakpoint
);
342 //mips_m4k_single_step_core(target);
343 mips_m4k_set_breakpoint(target
, breakpoint
);
347 /* exit debug mode - enable interrupts if required */
348 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
350 /* registers are now invalid */
351 mips32_invalidate_core_regs(target
);
353 if (!debug_execution
)
355 target
->state
= TARGET_RUNNING
;
356 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
357 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
361 target
->state
= TARGET_DEBUG_RUNNING
;
362 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
363 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
369 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
371 /* get pointers to arch-specific information */
372 mips32_common_t
*mips32
= target
->arch_info
;
373 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
374 breakpoint_t
*breakpoint
= NULL
;
376 if (target
->state
!= TARGET_HALTED
)
378 LOG_WARNING("target not halted");
379 return ERROR_TARGET_NOT_HALTED
;
382 /* current = 1: continue on current pc, otherwise continue at <address> */
384 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
386 /* the front-end may request us not to handle breakpoints */
387 if (handle_breakpoints
)
388 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
389 mips_m4k_unset_breakpoint(target
, breakpoint
);
391 /* restore context */
392 mips32_restore_context(target
);
394 /* configure single step mode */
395 mips_ejtag_config_step(ejtag_info
, 1);
397 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
399 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
401 /* exit debug mode */
402 mips_ejtag_exit_debug(ejtag_info
, 1);
404 /* registers are now invalid */
405 mips32_invalidate_core_regs(target
);
408 mips_m4k_set_breakpoint(target
, breakpoint
);
410 LOG_DEBUG("target stepped ");
412 mips_m4k_debug_entry(target
);
413 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
418 void mips_m4k_enable_breakpoints(struct target_s
*target
)
420 breakpoint_t
*breakpoint
= target
->breakpoints
;
422 /* set any pending breakpoints */
425 if (breakpoint
->set
== 0)
426 mips_m4k_set_breakpoint(target
, breakpoint
);
427 breakpoint
= breakpoint
->next
;
431 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
437 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
443 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
449 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
455 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
461 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
467 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
473 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
479 void mips_m4k_enable_watchpoints(struct target_s
*target
)
481 watchpoint_t
*watchpoint
= target
->watchpoints
;
483 /* set any pending watchpoints */
486 if (watchpoint
->set
== 0)
487 mips_m4k_set_watchpoint(target
, watchpoint
);
488 watchpoint
= watchpoint
->next
;
492 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
494 mips32_common_t
*mips32
= target
->arch_info
;
495 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
497 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
499 if (target
->state
!= TARGET_HALTED
)
501 LOG_WARNING("target not halted");
502 return ERROR_TARGET_NOT_HALTED
;
505 /* sanitize arguments */
506 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
507 return ERROR_INVALID_ARGUMENTS
;
509 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
510 return ERROR_TARGET_UNALIGNED_ACCESS
;
517 /* if noDMA off, use DMAACC mode for memory read */
518 if(ejtag_info
->impcode
& (1<<14))
519 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
521 return mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
523 LOG_ERROR("BUG: we shouldn't get here");
531 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
533 mips32_common_t
*mips32
= target
->arch_info
;
534 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
536 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
538 if (target
->state
!= TARGET_HALTED
)
540 LOG_WARNING("target not halted");
541 return ERROR_TARGET_NOT_HALTED
;
544 /* sanitize arguments */
545 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
546 return ERROR_INVALID_ARGUMENTS
;
548 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
549 return ERROR_TARGET_UNALIGNED_ACCESS
;
556 /* if noDMA off, use DMAACC mode for memory write */
557 if(ejtag_info
->impcode
& (1<<14))
558 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
560 mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
563 LOG_ERROR("BUG: we shouldn't get here");
571 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
575 retval
= mips32_register_commands(cmd_ctx
);
579 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
581 mips32_build_reg_cache(target
);
586 int mips_m4k_quit(void)
591 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, int chain_pos
, const char *variant
)
593 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
597 mips_m4k
->variant
= strdup(variant
);
601 mips_m4k
->variant
= strdup("");
604 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
606 /* initialize mips4k specific info */
607 mips32_init_arch_info(target
, mips32
, chain_pos
, variant
);
608 mips32
->arch_info
= mips_m4k
;
613 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
615 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
617 mips_m4k_init_arch_info(target
, mips_m4k
, target
->chain_position
, target
->variant
);
622 int mips_m4k_examine(struct target_s
*target
)
625 mips32_common_t
*mips32
= target
->arch_info
;
626 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
629 target
->type
->examined
= 1;
631 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
633 if (((idcode
>> 1) & 0x7FF) == 0x29)
635 /* we are using a pic32mx so select ejtag port
636 * as it is not selected by default */
637 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
638 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
641 /* init rest of ejtag interface */
642 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
648 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
650 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)