src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "mips32.h"
  27 #include "mips_m4k.h"
  28 #include "mips32_dmaacc.h"
  29 #include "jtag.h"
  30 #include "log.h"
  31
  32 #include <stdlib.h>
  33 #include <string.h>
  34
  35 /* cli handling */
  36
  37 /* forward declarations */
  38 int mips_m4k_poll(target_t *target);
  39 int mips_m4k_halt(struct target_s *target);
  40 int mips_m4k_soft_reset_halt(struct target_s *target);
  41 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
  42 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
  43 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  44 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  45 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
  46 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int mips_m4k_quit(void);
  48 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
  49
  50 int mips_m4k_examine(struct target_s *target);
  51 int mips_m4k_assert_reset(target_t *target);
  52 int mips_m4k_deassert_reset(target_t *target);
  53
  54 target_type_t mips_m4k_target =
  55 {
  56         .name = "mips_m4k",
  57
  58         .poll = mips_m4k_poll,
  59         .arch_state = mips32_arch_state,
  60
  61         .target_request_data = NULL,
  62
  63         .halt = mips_m4k_halt,
  64         .resume = mips_m4k_resume,
  65         .step = mips_m4k_step,
  66
  67         .assert_reset = mips_m4k_assert_reset,
  68         .deassert_reset = mips_m4k_deassert_reset,
  69         .soft_reset_halt = mips_m4k_soft_reset_halt,
  70
  71         .get_gdb_reg_list = mips32_get_gdb_reg_list,
  72
  73         .read_memory = mips_m4k_read_memory,
  74         .write_memory = mips_m4k_write_memory,
  75         .bulk_write_memory = mips_m4k_bulk_write_memory,
  76         .checksum_memory = NULL,
  77         .blank_check_memory = NULL,
  78
  79         .run_algorithm = mips32_run_algorithm,
  80
  81         .add_breakpoint = mips_m4k_add_breakpoint,
  82         .remove_breakpoint = mips_m4k_remove_breakpoint,
  83         .add_watchpoint = mips_m4k_add_watchpoint,
  84         .remove_watchpoint = mips_m4k_remove_watchpoint,
  85
  86         .register_commands = mips_m4k_register_commands,
  87         .target_create = mips_m4k_target_create,
  88         .init_target = mips_m4k_init_target,
  89         .examine = mips_m4k_examine,
  90         .quit = mips_m4k_quit
  91 };
  92
  93 int mips_m4k_debug_entry(target_t *target)
  94 {
  95         u32 debug_reg;
  96         mips32_common_t *mips32 = target->arch_info;
  97         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
  98
  99         /* read debug register */
 100         mips_ejtag_read_debug(ejtag_info, &debug_reg);
 101
 102         if ((target->debug_reason != DBG_REASON_DBGRQ)
 103                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 104         {
 105 //              if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 106 //              {
 107 //                      target->debug_reason = DBG_REASON_BREAKPOINT;
 108 //                      if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 109 //                              target->debug_reason = DBG_REASON_WPTANDBKPT;
 110 //              }
 111 //              else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 112 //                      target->debug_reason = DBG_REASON_WATCHPOINT;
 113         }
 114
 115         if (debug_reg & EJTAG_DEBUG_DSS)
 116         {
 117                 /* stopped due to single step - clear step bit */
 118                 mips_ejtag_config_step(ejtag_info, 0);
 119         }
 120
 121         mips32_save_context(target);
 122
 123         LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
 124                 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
 125                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 126
 127         return ERROR_OK;
 128 }
 129
 130 int mips_m4k_poll(target_t *target)
 131 {
 132         int retval;
 133         mips32_common_t *mips32 = target->arch_info;
 134         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 135
 136         /* read ejtag control reg */
 137         jtag_add_end_state(TAP_RTI);
 138         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 139         mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
 140
 141         if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
 142         {
 143                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 144                 {
 145                         jtag_add_end_state(TAP_RTI);
 146                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 147
 148                         target->state = TARGET_HALTED;
 149
 150                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 151                                 return retval;
 152
 153                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 154                 }
 155                 else if (target->state == TARGET_DEBUG_RUNNING)
 156                 {
 157                         target->state = TARGET_HALTED;
 158
 159                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 160                                 return retval;
 161
 162                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 163                 }
 164         }
 165         else
 166         {
 167                 target->state = TARGET_RUNNING;
 168         }
 169
 170         if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
 171         {
 172                 /* we have detected a reset, clear flag
 173                  * otherwise ejtag will not work */
 174                 jtag_add_end_state(TAP_RTI);
 175                 ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
 176
 177                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 178                 mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
 179                 LOG_DEBUG("Reset Detected");
 180         }
 181
 182 //      LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
 183
 184         return ERROR_OK;
 185 }
 186
 187 int mips_m4k_halt(struct target_s *target)
 188 {
 189         mips32_common_t *mips32 = target->arch_info;
 190         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 191
 192         LOG_DEBUG("target->state: %s",
 193                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 194
 195         if (target->state == TARGET_HALTED)
 196         {
 197                 LOG_DEBUG("target was already halted");
 198                 return ERROR_OK;
 199         }
 200
 201         if (target->state == TARGET_UNKNOWN)
 202         {
 203                 LOG_WARNING("target was in unknown state when halt was requested");
 204         }
 205
 206         if (target->state == TARGET_RESET)
 207         {
 208                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 209                 {
 210                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 211                         return ERROR_TARGET_FAILURE;
 212                 }
 213                 else
 214                 {
 215                         /* we came here in a reset_halt or reset_init sequence
 216                          * debug entry was already prepared in mips32_prepare_reset_halt()
 217                          */
 218                         target->debug_reason = DBG_REASON_DBGRQ;
 219
 220                         return ERROR_OK;
 221                 }
 222         }
 223
 224         /* break processor */
 225         mips_ejtag_enter_debug(ejtag_info);
 226
 227         target->debug_reason = DBG_REASON_DBGRQ;
 228
 229         return ERROR_OK;
 230 }
 231
 232 int mips_m4k_assert_reset(target_t *target)
 233 {
 234         mips32_common_t *mips32 = target->arch_info;
 235         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 236
 237         LOG_DEBUG("target->state: %s",
 238                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 239
 240         if (!(jtag_reset_config & RESET_HAS_SRST))
 241         {
 242                 LOG_ERROR("Can't assert SRST");
 243                 return ERROR_FAIL;
 244         }
 245
 246         if (target->reset_halt)
 247         {
 248                 /* use hardware to catch reset */
 249                 jtag_add_end_state(TAP_RTI);
 250                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
 251         }
 252         else
 253         {
 254                 jtag_add_end_state(TAP_RTI);
 255                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 256         }
 257
 258         /* here we should issue a srst only, but we may have to assert trst as well */
 259         if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 260         {
 261                 jtag_add_reset(1, 1);
 262         }
 263         else
 264         {
 265                 jtag_add_reset(0, 1);
 266         }
 267
 268         target->state = TARGET_RESET;
 269         jtag_add_sleep(50000);
 270
 271         mips32_invalidate_core_regs(target);
 272
 273     if (target->reset_halt)
 274     {
 275         int retval;
 276                 if ((retval = target_halt(target))!=ERROR_OK)
 277                         return retval;
 278     }
 279
 280
 281         return ERROR_OK;
 282 }
 283
 284 int mips_m4k_deassert_reset(target_t *target)
 285 {
 286         LOG_DEBUG("target->state: %s",
 287                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 288
 289         /* deassert reset lines */
 290         jtag_add_reset(0, 0);
 291
 292         return ERROR_OK;
 293 }
 294
 295 int mips_m4k_soft_reset_halt(struct target_s *target)
 296 {
 297         /* TODO */
 298         return ERROR_OK;
 299 }
 300
 301 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 302 {
 303         mips32_common_t *mips32 = target->arch_info;
 304         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 305         breakpoint_t *breakpoint = NULL;
 306         u32 resume_pc;
 307
 308         if (target->state != TARGET_HALTED)
 309         {
 310                 LOG_WARNING("target not halted");
 311                 return ERROR_TARGET_NOT_HALTED;
 312         }
 313
 314         if (!debug_execution)
 315         {
 316                 target_free_all_working_areas(target);
 317                 mips_m4k_enable_breakpoints(target);
 318                 mips_m4k_enable_watchpoints(target);
 319         }
 320
 321         /* current = 1: continue on current pc, otherwise continue at <address> */
 322         if (!current)
 323         {
 324                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 325                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 326                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 327         }
 328
 329         resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 330
 331         mips32_restore_context(target);
 332
 333         /* the front-end may request us not to handle breakpoints */
 334         if (handle_breakpoints)
 335         {
 336                 /* Single step past breakpoint at current address */
 337                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 338                 {
 339                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 340                         mips_m4k_unset_breakpoint(target, breakpoint);
 341                         //mips_m4k_single_step_core(target);
 342                         mips_m4k_set_breakpoint(target, breakpoint);
 343                 }
 344         }
 345
 346         /* exit debug mode - enable interrupts if required */
 347         mips_ejtag_exit_debug(ejtag_info, !debug_execution);
 348
 349         /* registers are now invalid */
 350         mips32_invalidate_core_regs(target);
 351
 352         if (!debug_execution)
 353         {
 354                 target->state = TARGET_RUNNING;
 355                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 356                 LOG_DEBUG("target resumed at 0x%x", resume_pc);
 357         }
 358         else
 359         {
 360                 target->state = TARGET_DEBUG_RUNNING;
 361                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 362                 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
 363         }
 364
 365         return ERROR_OK;
 366 }
 367
 368 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 369 {
 370         /* get pointers to arch-specific information */
 371         mips32_common_t *mips32 = target->arch_info;
 372         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 373         breakpoint_t *breakpoint = NULL;
 374
 375         if (target->state != TARGET_HALTED)
 376         {
 377                 LOG_WARNING("target not halted");
 378                 return ERROR_TARGET_NOT_HALTED;
 379         }
 380
 381         /* current = 1: continue on current pc, otherwise continue at <address> */
 382         if (!current)
 383                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 384
 385         /* the front-end may request us not to handle breakpoints */
 386         if (handle_breakpoints)
 387                 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
 388                         mips_m4k_unset_breakpoint(target, breakpoint);
 389
 390         /* restore context */
 391         mips32_restore_context(target);
 392
 393         /* configure single step mode */
 394         mips_ejtag_config_step(ejtag_info, 1);
 395
 396         target->debug_reason = DBG_REASON_SINGLESTEP;
 397
 398         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 399
 400         /* exit debug mode */
 401         mips_ejtag_exit_debug(ejtag_info, 1);
 402
 403         /* registers are now invalid */
 404         mips32_invalidate_core_regs(target);
 405
 406         if (breakpoint)
 407                 mips_m4k_set_breakpoint(target, breakpoint);
 408
 409         LOG_DEBUG("target stepped ");
 410
 411         mips_m4k_debug_entry(target);
 412         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 413
 414         return ERROR_OK;
 415 }
 416
 417 void mips_m4k_enable_breakpoints(struct target_s *target)
 418 {
 419         breakpoint_t *breakpoint = target->breakpoints;
 420
 421         /* set any pending breakpoints */
 422         while (breakpoint)
 423         {
 424                 if (breakpoint->set == 0)
 425                         mips_m4k_set_breakpoint(target, breakpoint);
 426                 breakpoint = breakpoint->next;
 427         }
 428 }
 429
 430 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 431 {
 432         /* TODO */
 433         return ERROR_OK;
 434 }
 435
 436 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 437 {
 438         /* TODO */
 439         return ERROR_OK;
 440 }
 441
 442 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 443 {
 444         /* TODO */
 445         return ERROR_OK;
 446 }
 447
 448 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 449 {
 450         /* TODO */
 451         return ERROR_OK;
 452 }
 453
 454 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 455 {
 456         /* TODO */
 457         return ERROR_OK;
 458 }
 459
 460 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 461 {
 462         /* TODO */
 463         return ERROR_OK;
 464 }
 465
 466 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 467 {
 468         /* TODO */
 469         return ERROR_OK;
 470 }
 471
 472 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 473 {
 474         /* TODO */
 475         return ERROR_OK;
 476 }
 477
 478 void mips_m4k_enable_watchpoints(struct target_s *target)
 479 {
 480         watchpoint_t *watchpoint = target->watchpoints;
 481
 482         /* set any pending watchpoints */
 483         while (watchpoint)
 484         {
 485                 if (watchpoint->set == 0)
 486                         mips_m4k_set_watchpoint(target, watchpoint);
 487                 watchpoint = watchpoint->next;
 488         }
 489 }
 490
 491 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 492 {
 493         mips32_common_t *mips32 = target->arch_info;
 494         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 495
 496         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 497
 498         if (target->state != TARGET_HALTED)
 499         {
 500                 LOG_WARNING("target not halted");
 501                 return ERROR_TARGET_NOT_HALTED;
 502         }
 503
 504         /* sanitize arguments */
 505         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 506                 return ERROR_INVALID_ARGUMENTS;
 507
 508         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 509                 return ERROR_TARGET_UNALIGNED_ACCESS;
 510
 511         switch (size)
 512         {
 513                 case 4:
 514                 case 2:
 515                 case 1:
 516                         /* if noDMA off, use DMAACC mode for memory read */
 517                         if(ejtag_info->impcode & (1<<14))
 518                                 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 519                         else
 520                                 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 521                 default:
 522                         LOG_ERROR("BUG: we shouldn't get here");
 523                         exit(-1);
 524                         break;
 525         }
 526
 527         return ERROR_OK;
 528 }
 529
 530 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 531 {
 532         mips32_common_t *mips32 = target->arch_info;
 533         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 534
 535         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 536
 537         if (target->state != TARGET_HALTED)
 538         {
 539                 LOG_WARNING("target not halted");
 540                 return ERROR_TARGET_NOT_HALTED;
 541         }
 542
 543         /* sanitize arguments */
 544         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 545                 return ERROR_INVALID_ARGUMENTS;
 546
 547         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 548                 return ERROR_TARGET_UNALIGNED_ACCESS;
 549
 550         switch (size)
 551         {
 552                 case 4:
 553                 case 2:
 554                 case 1:
 555                         /* if noDMA off, use DMAACC mode for memory write */
 556                         if(ejtag_info->impcode & (1<<14))
 557                                 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 558                         else
 559                                 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 560                         break;
 561                 default:
 562                         LOG_ERROR("BUG: we shouldn't get here");
 563                         exit(-1);
 564                         break;
 565         }
 566
 567         return ERROR_OK;
 568 }
 569
 570 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
 571 {
 572         int retval;
 573
 574         retval = mips32_register_commands(cmd_ctx);
 575         return retval;
 576 }
 577
 578 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 579 {
 580         mips32_build_reg_cache(target);
 581
 582         return ERROR_OK;
 583 }
 584
 585 int mips_m4k_quit(void)
 586 {
 587         return ERROR_OK;
 588 }
 589
 590 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, const char *variant)
 591 {
 592         mips32_common_t *mips32 = &mips_m4k->mips32_common;
 593
 594         if (variant)
 595         {
 596                 mips_m4k->variant = strdup(variant);
 597         }
 598         else
 599         {
 600                 mips_m4k->variant = strdup("");
 601         }
 602
 603         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 604
 605         /* initialize mips4k specific info */
 606         mips32_init_arch_info(target, mips32, chain_pos, variant);
 607         mips32->arch_info = mips_m4k;
 608
 609         return ERROR_OK;
 610 }
 611
 612 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
 613 {
 614         mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 615
 616         mips_m4k_init_arch_info(target, mips_m4k, target->chain_position, target->variant);
 617
 618         return ERROR_OK;
 619 }
 620
 621 int mips_m4k_examine(struct target_s *target)
 622 {
 623         int retval;
 624         mips32_common_t *mips32 = target->arch_info;
 625         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 626         u32 idcode = 0;
 627
 628         target->type->examined = 1;
 629
 630         mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
 631
 632         if (((idcode >> 1) & 0x7FF) == 0x29)
 633         {
 634                 /* we are using a pic32mx so select ejtag port
 635                  * as it is not selected by default */
 636                 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
 637                 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 638         }
 639
 640         /* init rest of ejtag interface */
 641         if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 642                 return retval;
 643
 644         return ERROR_OK;
 645 }
 646
 647 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 648 {
 649         return mips_m4k_write_memory(target, address, 4, count, buffer);
 650 }