1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
37 /* forward declarations */
38 int mips_m4k_poll(target_t
*target
);
39 int mips_m4k_halt(struct target_s
*target
);
40 int mips_m4k_soft_reset_halt(struct target_s
*target
);
41 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
44 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
45 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
);
46 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
47 int mips_m4k_quit(void);
48 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
);
50 int mips_m4k_examine(struct target_s
*target
);
51 int mips_m4k_assert_reset(target_t
*target
);
52 int mips_m4k_deassert_reset(target_t
*target
);
53 int mips_m4k_checksum_memory(target_t
*target
, u32 address
, u32 size
, u32
*checksum
);
55 target_type_t mips_m4k_target
=
59 .poll
= mips_m4k_poll
,
60 .arch_state
= mips32_arch_state
,
62 .target_request_data
= NULL
,
64 .halt
= mips_m4k_halt
,
65 .resume
= mips_m4k_resume
,
66 .step
= mips_m4k_step
,
68 .assert_reset
= mips_m4k_assert_reset
,
69 .deassert_reset
= mips_m4k_deassert_reset
,
70 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
72 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
74 .read_memory
= mips_m4k_read_memory
,
75 .write_memory
= mips_m4k_write_memory
,
76 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
77 .checksum_memory
= mips_m4k_checksum_memory
,
78 .blank_check_memory
= NULL
,
80 .run_algorithm
= mips32_run_algorithm
,
82 .add_breakpoint
= mips_m4k_add_breakpoint
,
83 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
84 .add_watchpoint
= mips_m4k_add_watchpoint
,
85 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
87 .register_commands
= mips_m4k_register_commands
,
88 .target_create
= mips_m4k_target_create
,
89 .init_target
= mips_m4k_init_target
,
90 .examine
= mips_m4k_examine
,
94 int mips_m4k_examine_debug_reason(target_t
*target
)
99 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
100 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
102 /* get info about inst breakpoint support */
103 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
105 if (break_status
& 0x1f)
107 /* we have halted on a breakpoint */
108 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
110 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
113 /* get info about data breakpoint support */
114 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
116 if (break_status
& 0x1f)
118 /* we have halted on a breakpoint */
119 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
121 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
128 int mips_m4k_debug_entry(target_t
*target
)
130 mips32_common_t
*mips32
= target
->arch_info
;
131 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
134 /* read debug register */
135 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
137 /* make sure break uit configured */
138 mips32_configure_break_unit(target
);
140 /* attempt to find halt reason */
141 mips_m4k_examine_debug_reason(target
);
143 /* clear single step if active */
144 if (debug_reg
& EJTAG_DEBUG_DSS
)
146 /* stopped due to single step - clear step bit */
147 mips_ejtag_config_step(ejtag_info
, 0);
150 mips32_save_context(target
);
152 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
153 *(u32
*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
154 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
159 int mips_m4k_poll(target_t
*target
)
162 mips32_common_t
*mips32
= target
->arch_info
;
163 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
164 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
166 /* read ejtag control reg */
167 jtag_add_end_state(TAP_IDLE
);
168 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
169 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
171 /* clear this bit before handling polling
172 * as after reset registers will read zero */
173 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
175 /* we have detected a reset, clear flag
176 * otherwise ejtag will not work */
177 jtag_add_end_state(TAP_IDLE
);
178 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
180 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
181 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
182 LOG_DEBUG("Reset Detected");
185 /* check for processor halted */
186 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
188 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
190 jtag_add_end_state(TAP_IDLE
);
191 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
193 target
->state
= TARGET_HALTED
;
195 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
198 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
200 else if (target
->state
== TARGET_DEBUG_RUNNING
)
202 target
->state
= TARGET_HALTED
;
204 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
207 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
212 target
->state
= TARGET_RUNNING
;
215 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
220 int mips_m4k_halt(struct target_s
*target
)
222 mips32_common_t
*mips32
= target
->arch_info
;
223 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
225 LOG_DEBUG("target->state: %s",
226 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
228 if (target
->state
== TARGET_HALTED
)
230 LOG_DEBUG("target was already halted");
234 if (target
->state
== TARGET_UNKNOWN
)
236 LOG_WARNING("target was in unknown state when halt was requested");
239 if (target
->state
== TARGET_RESET
)
241 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) && jtag_srst
)
243 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
244 return ERROR_TARGET_FAILURE
;
248 /* we came here in a reset_halt or reset_init sequence
249 * debug entry was already prepared in mips32_prepare_reset_halt()
251 target
->debug_reason
= DBG_REASON_DBGRQ
;
257 /* break processor */
258 mips_ejtag_enter_debug(ejtag_info
);
260 target
->debug_reason
= DBG_REASON_DBGRQ
;
265 int mips_m4k_assert_reset(target_t
*target
)
267 mips32_common_t
*mips32
= target
->arch_info
;
268 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
270 LOG_DEBUG("target->state: %s",
271 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
273 if (!(jtag_reset_config
& RESET_HAS_SRST
))
275 LOG_ERROR("Can't assert SRST");
279 if (target
->reset_halt
)
281 /* use hardware to catch reset */
282 jtag_add_end_state(TAP_IDLE
);
283 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
287 jtag_add_end_state(TAP_IDLE
);
288 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
291 if (strcmp(target
->variant
, "ejtag_srst") == 0)
293 u32 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
294 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
295 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
296 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
300 /* here we should issue a srst only, but we may have to assert trst as well */
301 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
303 jtag_add_reset(1, 1);
307 jtag_add_reset(0, 1);
311 target
->state
= TARGET_RESET
;
312 jtag_add_sleep(50000);
314 mips32_invalidate_core_regs(target
);
316 if (target
->reset_halt
)
319 if ((retval
= target_halt(target
))!=ERROR_OK
)
326 int mips_m4k_deassert_reset(target_t
*target
)
328 LOG_DEBUG("target->state: %s",
329 Jim_Nvp_value2name_simple( nvp_target_state
, target
->state
)->name
);
331 /* deassert reset lines */
332 jtag_add_reset(0, 0);
337 int mips_m4k_soft_reset_halt(struct target_s
*target
)
343 int mips_m4k_single_step_core(target_t
*target
)
345 mips32_common_t
*mips32
= target
->arch_info
;
346 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
348 /* configure single step mode */
349 mips_ejtag_config_step(ejtag_info
, 1);
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info
, 1);
354 mips_m4k_debug_entry(target
);
359 int mips_m4k_resume(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
, int debug_execution
)
361 mips32_common_t
*mips32
= target
->arch_info
;
362 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
363 breakpoint_t
*breakpoint
= NULL
;
366 if (target
->state
!= TARGET_HALTED
)
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED
;
372 if (!debug_execution
)
374 target_free_all_working_areas(target
);
375 mips_m4k_enable_breakpoints(target
);
376 mips_m4k_enable_watchpoints(target
);
379 /* current = 1: continue on current pc, otherwise continue at <address> */
382 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
383 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
384 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
387 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
389 mips32_restore_context(target
);
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints
)
394 /* Single step past breakpoint at current address */
395 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
397 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
398 mips_m4k_unset_breakpoint(target
, breakpoint
);
399 mips_m4k_single_step_core(target
);
400 mips_m4k_set_breakpoint(target
, breakpoint
);
404 /* exit debug mode - enable interrupts if required */
405 mips_ejtag_exit_debug(ejtag_info
, !debug_execution
);
406 target
->debug_reason
= DBG_REASON_NOTHALTED
;
408 /* registers are now invalid */
409 mips32_invalidate_core_regs(target
);
411 if (!debug_execution
)
413 target
->state
= TARGET_RUNNING
;
414 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
415 LOG_DEBUG("target resumed at 0x%x", resume_pc
);
419 target
->state
= TARGET_DEBUG_RUNNING
;
420 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
421 LOG_DEBUG("target debug resumed at 0x%x", resume_pc
);
427 int mips_m4k_step(struct target_s
*target
, int current
, u32 address
, int handle_breakpoints
)
429 /* get pointers to arch-specific information */
430 mips32_common_t
*mips32
= target
->arch_info
;
431 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
432 breakpoint_t
*breakpoint
= NULL
;
434 if (target
->state
!= TARGET_HALTED
)
436 LOG_WARNING("target not halted");
437 return ERROR_TARGET_NOT_HALTED
;
440 /* current = 1: continue on current pc, otherwise continue at <address> */
442 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
444 /* the front-end may request us not to handle breakpoints */
445 if (handle_breakpoints
)
446 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
447 mips_m4k_unset_breakpoint(target
, breakpoint
);
449 /* restore context */
450 mips32_restore_context(target
);
452 /* configure single step mode */
453 mips_ejtag_config_step(ejtag_info
, 1);
455 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
457 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
459 /* exit debug mode */
460 mips_ejtag_exit_debug(ejtag_info
, 1);
462 /* registers are now invalid */
463 mips32_invalidate_core_regs(target
);
466 mips_m4k_set_breakpoint(target
, breakpoint
);
468 LOG_DEBUG("target stepped ");
470 mips_m4k_debug_entry(target
);
471 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
476 void mips_m4k_enable_breakpoints(struct target_s
*target
)
478 breakpoint_t
*breakpoint
= target
->breakpoints
;
480 /* set any pending breakpoints */
483 if (breakpoint
->set
== 0)
484 mips_m4k_set_breakpoint(target
, breakpoint
);
485 breakpoint
= breakpoint
->next
;
489 int mips_m4k_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
491 mips32_common_t
*mips32
= target
->arch_info
;
492 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
496 LOG_WARNING("breakpoint already set");
500 if (breakpoint
->type
== BKPT_HARD
)
504 while(comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
506 if (bp_num
>= mips32
->num_inst_bpoints
)
508 LOG_DEBUG("ERROR Can not find free FP Comparator");
509 LOG_WARNING("ERROR Can not find free FP Comparator");
512 breakpoint
->set
= bp_num
+ 1;
513 comparator_list
[bp_num
].used
= 1;
514 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
515 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
516 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
517 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
518 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num
, comparator_list
[bp_num
].bp_value
);
520 else if (breakpoint
->type
== BKPT_SOFT
)
528 int mips_m4k_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
530 /* get pointers to arch-specific information */
531 mips32_common_t
*mips32
= target
->arch_info
;
532 mips32_comparator_t
* comparator_list
= mips32
->inst_break_list
;
534 if (!breakpoint
->set
)
536 LOG_WARNING("breakpoint not set");
540 if (breakpoint
->type
== BKPT_HARD
)
542 int bp_num
= breakpoint
->set
- 1;
543 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
545 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
548 comparator_list
[bp_num
].used
= 0;
549 comparator_list
[bp_num
].bp_value
= 0;
550 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
561 int mips_m4k_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
563 mips32_common_t
*mips32
= target
->arch_info
;
565 if (mips32
->num_inst_bpoints_avail
< 1)
567 LOG_INFO("no hardware breakpoint available");
568 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
571 /* default to hardware for now */
572 breakpoint
->type
= BKPT_HARD
;
574 mips32
->num_inst_bpoints_avail
--;
575 mips_m4k_set_breakpoint(target
, breakpoint
);
580 int mips_m4k_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
582 /* get pointers to arch-specific information */
583 mips32_common_t
*mips32
= target
->arch_info
;
585 if (target
->state
!= TARGET_HALTED
)
587 LOG_WARNING("target not halted");
588 return ERROR_TARGET_NOT_HALTED
;
593 mips_m4k_unset_breakpoint(target
, breakpoint
);
596 if (breakpoint
->type
== BKPT_HARD
)
597 mips32
->num_inst_bpoints_avail
++;
602 int mips_m4k_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
608 int mips_m4k_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
614 int mips_m4k_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
620 int mips_m4k_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
626 void mips_m4k_enable_watchpoints(struct target_s
*target
)
628 watchpoint_t
*watchpoint
= target
->watchpoints
;
630 /* set any pending watchpoints */
633 if (watchpoint
->set
== 0)
634 mips_m4k_set_watchpoint(target
, watchpoint
);
635 watchpoint
= watchpoint
->next
;
639 int mips_m4k_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
641 mips32_common_t
*mips32
= target
->arch_info
;
642 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
644 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
646 if (target
->state
!= TARGET_HALTED
)
648 LOG_WARNING("target not halted");
649 return ERROR_TARGET_NOT_HALTED
;
652 /* sanitize arguments */
653 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
654 return ERROR_INVALID_ARGUMENTS
;
656 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
657 return ERROR_TARGET_UNALIGNED_ACCESS
;
664 /* if noDMA off, use DMAACC mode for memory read */
665 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
666 return mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
668 return mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
670 LOG_ERROR("BUG: we shouldn't get here");
678 int mips_m4k_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
680 mips32_common_t
*mips32
= target
->arch_info
;
681 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
683 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
685 if (target
->state
!= TARGET_HALTED
)
687 LOG_WARNING("target not halted");
688 return ERROR_TARGET_NOT_HALTED
;
691 /* sanitize arguments */
692 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
693 return ERROR_INVALID_ARGUMENTS
;
695 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
696 return ERROR_TARGET_UNALIGNED_ACCESS
;
703 /* if noDMA off, use DMAACC mode for memory write */
704 if(ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
705 mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
707 mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
710 LOG_ERROR("BUG: we shouldn't get here");
718 int mips_m4k_register_commands(struct command_context_s
*cmd_ctx
)
722 retval
= mips32_register_commands(cmd_ctx
);
726 int mips_m4k_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
728 mips32_build_reg_cache(target
);
733 int mips_m4k_quit(void)
738 int mips_m4k_init_arch_info(target_t
*target
, mips_m4k_common_t
*mips_m4k
, jtag_tap_t
*tap
)
740 mips32_common_t
*mips32
= &mips_m4k
->mips32_common
;
742 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
744 /* initialize mips4k specific info */
745 mips32_init_arch_info(target
, mips32
, tap
);
746 mips32
->arch_info
= mips_m4k
;
751 int mips_m4k_target_create(struct target_s
*target
, Jim_Interp
*interp
)
753 mips_m4k_common_t
*mips_m4k
= calloc(1,sizeof(mips_m4k_common_t
));
755 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
760 int mips_m4k_examine(struct target_s
*target
)
763 mips32_common_t
*mips32
= target
->arch_info
;
764 mips_ejtag_t
*ejtag_info
= &mips32
->ejtag_info
;
767 if (!target
->type
->examined
)
769 mips_ejtag_get_idcode(ejtag_info
, &idcode
, NULL
);
770 ejtag_info
->idcode
= idcode
;
772 if (((idcode
>> 1) & 0x7FF) == 0x29)
774 /* we are using a pic32mx so select ejtag port
775 * as it is not selected by default */
776 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
777 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
781 /* init rest of ejtag interface */
782 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
785 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
791 int mips_m4k_bulk_write_memory(target_t
*target
, u32 address
, u32 count
, u8
*buffer
)
793 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
796 int mips_m4k_checksum_memory(target_t
*target
, u32 address
, u32 size
, u32
*checksum
)
798 return ERROR_FAIL
; /* use bulk read method */
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