Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Add target_read_memory wrapper:
[openocd.git] / src / target / mips_m4k.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "mips32.h"
27 #include "mips_m4k.h"
28 #include "mips32_dmaacc.h"
29
30
31 /* cli handling */
32
33 /* forward declarations */
34 int mips_m4k_poll(target_t *target);
35 int mips_m4k_halt(struct target_s *target);
36 int mips_m4k_soft_reset_halt(struct target_s *target);
37 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
38 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
39 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
40 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
41 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
42 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
43 int mips_m4k_quit(void);
44 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
45
46 int mips_m4k_examine(struct target_s *target);
47 int mips_m4k_assert_reset(target_t *target);
48 int mips_m4k_deassert_reset(target_t *target);
49 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
50
51 target_type_t mips_m4k_target =
52 {
53 .name = "mips_m4k",
54
55 .poll = mips_m4k_poll,
56 .arch_state = mips32_arch_state,
57
58 .target_request_data = NULL,
59
60 .halt = mips_m4k_halt,
61 .resume = mips_m4k_resume,
62 .step = mips_m4k_step,
63
64 .assert_reset = mips_m4k_assert_reset,
65 .deassert_reset = mips_m4k_deassert_reset,
66 .soft_reset_halt = mips_m4k_soft_reset_halt,
67
68 .get_gdb_reg_list = mips32_get_gdb_reg_list,
69
70 .read_memory = mips_m4k_read_memory,
71 .write_memory = mips_m4k_write_memory,
72 .bulk_write_memory = mips_m4k_bulk_write_memory,
73 .checksum_memory = mips_m4k_checksum_memory,
74 .blank_check_memory = NULL,
75
76 .run_algorithm = mips32_run_algorithm,
77
78 .add_breakpoint = mips_m4k_add_breakpoint,
79 .remove_breakpoint = mips_m4k_remove_breakpoint,
80 .add_watchpoint = mips_m4k_add_watchpoint,
81 .remove_watchpoint = mips_m4k_remove_watchpoint,
82
83 .register_commands = mips_m4k_register_commands,
84 .target_create = mips_m4k_target_create,
85 .init_target = mips_m4k_init_target,
86 .examine = mips_m4k_examine,
87 .quit = mips_m4k_quit
88 };
89
90 int mips_m4k_examine_debug_reason(target_t *target)
91 {
92 u32 break_status;
93 int retval;
94
95 if ((target->debug_reason != DBG_REASON_DBGRQ)
96 && (target->debug_reason != DBG_REASON_SINGLESTEP))
97 {
98 /* get info about inst breakpoint support */
99 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
100 return retval;
101 if (break_status & 0x1f)
102 {
103 /* we have halted on a breakpoint */
104 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
105 return retval;
106 target->debug_reason = DBG_REASON_BREAKPOINT;
107 }
108
109 /* get info about data breakpoint support */
110 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
111 return retval;
112 if (break_status & 0x1f)
113 {
114 /* we have halted on a breakpoint */
115 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
116 return retval;
117 target->debug_reason = DBG_REASON_WATCHPOINT;
118 }
119 }
120
121 return ERROR_OK;
122 }
123
124 int mips_m4k_debug_entry(target_t *target)
125 {
126 mips32_common_t *mips32 = target->arch_info;
127 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
128 u32 debug_reg;
129
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info, &debug_reg);
132
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target);
135
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target);
138
139 /* clear single step if active */
140 if (debug_reg & EJTAG_DEBUG_DSS)
141 {
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info, 0);
144 }
145
146 mips32_save_context(target);
147
148 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
149 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
150 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
151
152 return ERROR_OK;
153 }
154
155 int mips_m4k_poll(target_t *target)
156 {
157 int retval;
158 mips32_common_t *mips32 = target->arch_info;
159 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
160 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
161
162 /* read ejtag control reg */
163 jtag_add_end_state(TAP_IDLE);
164 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
165 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
166
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
170 {
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_add_end_state(TAP_IDLE);
174 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
175
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
177 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178 LOG_DEBUG("Reset Detected");
179 }
180
181 /* check for processor halted */
182 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
183 {
184 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
185 {
186 jtag_add_end_state(TAP_IDLE);
187 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
188
189 target->state = TARGET_HALTED;
190
191 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
192 return retval;
193
194 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
195 }
196 else if (target->state == TARGET_DEBUG_RUNNING)
197 {
198 target->state = TARGET_HALTED;
199
200 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
201 return retval;
202
203 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
204 }
205 }
206 else
207 {
208 target->state = TARGET_RUNNING;
209 }
210
211 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
212
213 return ERROR_OK;
214 }
215
216 int mips_m4k_halt(struct target_s *target)
217 {
218 mips32_common_t *mips32 = target->arch_info;
219 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
220
221 LOG_DEBUG("target->state: %s",
222 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
223
224 if (target->state == TARGET_HALTED)
225 {
226 LOG_DEBUG("target was already halted");
227 return ERROR_OK;
228 }
229
230 if (target->state == TARGET_UNKNOWN)
231 {
232 LOG_WARNING("target was in unknown state when halt was requested");
233 }
234
235 if (target->state == TARGET_RESET)
236 {
237 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
238 {
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE;
241 }
242 else
243 {
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
246 */
247 target->debug_reason = DBG_REASON_DBGRQ;
248
249 return ERROR_OK;
250 }
251 }
252
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info);
255
256 target->debug_reason = DBG_REASON_DBGRQ;
257
258 return ERROR_OK;
259 }
260
261 int mips_m4k_assert_reset(target_t *target)
262 {
263 mips32_common_t *mips32 = target->arch_info;
264 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
265
266 LOG_DEBUG("target->state: %s",
267 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
268
269 if (!(jtag_reset_config & RESET_HAS_SRST))
270 {
271 LOG_ERROR("Can't assert SRST");
272 return ERROR_FAIL;
273 }
274
275 if (target->reset_halt)
276 {
277 /* use hardware to catch reset */
278 jtag_add_end_state(TAP_IDLE);
279 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
280 }
281 else
282 {
283 jtag_add_end_state(TAP_IDLE);
284 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
285 }
286
287 if (strcmp(target->variant, "ejtag_srst") == 0)
288 {
289 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
290 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
291 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
292 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
293 }
294 else
295 {
296 /* here we should issue a srst only, but we may have to assert trst as well */
297 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
298 {
299 jtag_add_reset(1, 1);
300 }
301 else
302 {
303 jtag_add_reset(0, 1);
304 }
305 }
306
307 target->state = TARGET_RESET;
308 jtag_add_sleep(50000);
309
310 mips32_invalidate_core_regs(target);
311
312 if (target->reset_halt)
313 {
314 int retval;
315 if ((retval = target_halt(target))!=ERROR_OK)
316 return retval;
317 }
318
319 return ERROR_OK;
320 }
321
322 int mips_m4k_deassert_reset(target_t *target)
323 {
324 LOG_DEBUG("target->state: %s",
325 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
326
327 /* deassert reset lines */
328 jtag_add_reset(0, 0);
329
330 return ERROR_OK;
331 }
332
333 int mips_m4k_soft_reset_halt(struct target_s *target)
334 {
335 /* TODO */
336 return ERROR_OK;
337 }
338
339 int mips_m4k_single_step_core(target_t *target)
340 {
341 mips32_common_t *mips32 = target->arch_info;
342 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
343
344 /* configure single step mode */
345 mips_ejtag_config_step(ejtag_info, 1);
346
347 /* disable interrupts while stepping */
348 mips32_enable_interrupts(target, 0);
349
350 /* exit debug mode */
351 mips_ejtag_exit_debug(ejtag_info);
352
353 mips_m4k_debug_entry(target);
354
355 return ERROR_OK;
356 }
357
358 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
359 {
360 mips32_common_t *mips32 = target->arch_info;
361 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
362 breakpoint_t *breakpoint = NULL;
363 u32 resume_pc;
364
365 if (target->state != TARGET_HALTED)
366 {
367 LOG_WARNING("target not halted");
368 return ERROR_TARGET_NOT_HALTED;
369 }
370
371 if (!debug_execution)
372 {
373 target_free_all_working_areas(target);
374 mips_m4k_enable_breakpoints(target);
375 mips_m4k_enable_watchpoints(target);
376 }
377
378 /* current = 1: continue on current pc, otherwise continue at <address> */
379 if (!current)
380 {
381 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
382 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
383 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
384 }
385
386 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
387
388 mips32_restore_context(target);
389
390 /* the front-end may request us not to handle breakpoints */
391 if (handle_breakpoints)
392 {
393 /* Single step past breakpoint at current address */
394 if ((breakpoint = breakpoint_find(target, resume_pc)))
395 {
396 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
397 mips_m4k_unset_breakpoint(target, breakpoint);
398 mips_m4k_single_step_core(target);
399 mips_m4k_set_breakpoint(target, breakpoint);
400 }
401 }
402
403 /* enable interrupts if we are running */
404 mips32_enable_interrupts(target, !debug_execution);
405
406 /* exit debug mode */
407 mips_ejtag_exit_debug(ejtag_info);
408 target->debug_reason = DBG_REASON_NOTHALTED;
409
410 /* registers are now invalid */
411 mips32_invalidate_core_regs(target);
412
413 if (!debug_execution)
414 {
415 target->state = TARGET_RUNNING;
416 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
417 LOG_DEBUG("target resumed at 0x%x", resume_pc);
418 }
419 else
420 {
421 target->state = TARGET_DEBUG_RUNNING;
422 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
423 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
424 }
425
426 return ERROR_OK;
427 }
428
429 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
430 {
431 /* get pointers to arch-specific information */
432 mips32_common_t *mips32 = target->arch_info;
433 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
434 breakpoint_t *breakpoint = NULL;
435
436 if (target->state != TARGET_HALTED)
437 {
438 LOG_WARNING("target not halted");
439 return ERROR_TARGET_NOT_HALTED;
440 }
441
442 /* current = 1: continue on current pc, otherwise continue at <address> */
443 if (!current)
444 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
445
446 /* the front-end may request us not to handle breakpoints */
447 if (handle_breakpoints)
448 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
449 mips_m4k_unset_breakpoint(target, breakpoint);
450
451 /* restore context */
452 mips32_restore_context(target);
453
454 /* configure single step mode */
455 mips_ejtag_config_step(ejtag_info, 1);
456
457 target->debug_reason = DBG_REASON_SINGLESTEP;
458
459 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
460
461 /* disable interrupts while stepping */
462 mips32_enable_interrupts(target, 0);
463
464 /* exit debug mode */
465 mips_ejtag_exit_debug(ejtag_info);
466
467 /* registers are now invalid */
468 mips32_invalidate_core_regs(target);
469
470 if (breakpoint)
471 mips_m4k_set_breakpoint(target, breakpoint);
472
473 LOG_DEBUG("target stepped ");
474
475 mips_m4k_debug_entry(target);
476 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
477
478 return ERROR_OK;
479 }
480
481 void mips_m4k_enable_breakpoints(struct target_s *target)
482 {
483 breakpoint_t *breakpoint = target->breakpoints;
484
485 /* set any pending breakpoints */
486 while (breakpoint)
487 {
488 if (breakpoint->set == 0)
489 mips_m4k_set_breakpoint(target, breakpoint);
490 breakpoint = breakpoint->next;
491 }
492 }
493
494 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
495 {
496 mips32_common_t *mips32 = target->arch_info;
497 mips32_comparator_t * comparator_list = mips32->inst_break_list;
498 int retval;
499
500 if (breakpoint->set)
501 {
502 LOG_WARNING("breakpoint already set");
503 return ERROR_OK;
504 }
505
506 if (breakpoint->type == BKPT_HARD)
507 {
508 int bp_num = 0;
509
510 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
511 bp_num++;
512 if (bp_num >= mips32->num_inst_bpoints)
513 {
514 LOG_DEBUG("ERROR Can not find free FP Comparator");
515 LOG_WARNING("ERROR Can not find free FP Comparator");
516 exit(-1);
517 }
518 breakpoint->set = bp_num + 1;
519 comparator_list[bp_num].used = 1;
520 comparator_list[bp_num].bp_value = breakpoint->address;
521 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
522 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
523 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
524 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
525 }
526 else if (breakpoint->type == BKPT_SOFT)
527 {
528 if (breakpoint->length == 4)
529 {
530 u32 verify = 0xffffffff;
531
532 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
533 {
534 return retval;
535 }
536 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
537 {
538 return retval;
539 }
540
541 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
542 {
543 return retval;
544 }
545 if (verify != MIPS32_SDBBP)
546 {
547 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
548 return ERROR_OK;
549 }
550 }
551 else
552 {
553 u16 verify = 0xffff;
554
555 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
556 {
557 return retval;
558 }
559 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
560 {
561 return retval;
562 }
563
564 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
565 {
566 return retval;
567 }
568 if (verify != MIPS16_SDBBP)
569 {
570 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
571 return ERROR_OK;
572 }
573 }
574
575 breakpoint->set = 20; /* Any nice value but 0 */
576 }
577
578 return ERROR_OK;
579 }
580
581 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
582 {
583 /* get pointers to arch-specific information */
584 mips32_common_t *mips32 = target->arch_info;
585 mips32_comparator_t * comparator_list = mips32->inst_break_list;
586 int retval;
587
588 if (!breakpoint->set)
589 {
590 LOG_WARNING("breakpoint not set");
591 return ERROR_OK;
592 }
593
594 if (breakpoint->type == BKPT_HARD)
595 {
596 int bp_num = breakpoint->set - 1;
597 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
598 {
599 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
600 return ERROR_OK;
601 }
602 comparator_list[bp_num].used = 0;
603 comparator_list[bp_num].bp_value = 0;
604 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
605 }
606 else
607 {
608 /* restore original instruction (kept in target endianness) */
609 if (breakpoint->length == 4)
610 {
611 u32 current_instr;
612
613 /* check that user program has not modified breakpoint instruction */
614 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
615 {
616 return retval;
617 }
618 if (current_instr == MIPS32_SDBBP)
619 {
620 if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
621 {
622 return retval;
623 }
624 }
625 }
626 else
627 {
628 u16 current_instr;
629
630 /* check that user program has not modified breakpoint instruction */
631 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
632 {
633 return retval;
634 }
635
636 if (current_instr == MIPS16_SDBBP)
637 {
638 if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
639 {
640 return retval;
641 }
642 }
643 }
644 }
645 breakpoint->set = 0;
646
647 return ERROR_OK;
648 }
649
650 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
651 {
652 mips32_common_t *mips32 = target->arch_info;
653
654 if (breakpoint->type == BKPT_HARD)
655 {
656 if (mips32->num_inst_bpoints_avail < 1)
657 {
658 LOG_INFO("no hardware breakpoint available");
659 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
660 }
661
662 mips32->num_inst_bpoints_avail--;
663 }
664
665 mips_m4k_set_breakpoint(target, breakpoint);
666
667 return ERROR_OK;
668 }
669
670 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
671 {
672 /* get pointers to arch-specific information */
673 mips32_common_t *mips32 = target->arch_info;
674
675 if (target->state != TARGET_HALTED)
676 {
677 LOG_WARNING("target not halted");
678 return ERROR_TARGET_NOT_HALTED;
679 }
680
681 if (breakpoint->set)
682 {
683 mips_m4k_unset_breakpoint(target, breakpoint);
684 }
685
686 if (breakpoint->type == BKPT_HARD)
687 mips32->num_inst_bpoints_avail++;
688
689 return ERROR_OK;
690 }
691
692 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
693 {
694 /* TODO */
695 return ERROR_OK;
696 }
697
698 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
699 {
700 /* TODO */
701 return ERROR_OK;
702 }
703
704 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
705 {
706 /* TODO */
707 return ERROR_OK;
708 }
709
710 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
711 {
712 /* TODO */
713 return ERROR_OK;
714 }
715
716 void mips_m4k_enable_watchpoints(struct target_s *target)
717 {
718 watchpoint_t *watchpoint = target->watchpoints;
719
720 /* set any pending watchpoints */
721 while (watchpoint)
722 {
723 if (watchpoint->set == 0)
724 mips_m4k_set_watchpoint(target, watchpoint);
725 watchpoint = watchpoint->next;
726 }
727 }
728
729 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
730 {
731 mips32_common_t *mips32 = target->arch_info;
732 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
733
734 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
735
736 if (target->state != TARGET_HALTED)
737 {
738 LOG_WARNING("target not halted");
739 return ERROR_TARGET_NOT_HALTED;
740 }
741
742 /* sanitize arguments */
743 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
744 return ERROR_INVALID_ARGUMENTS;
745
746 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
747 return ERROR_TARGET_UNALIGNED_ACCESS;
748
749 switch (size)
750 {
751 case 4:
752 case 2:
753 case 1:
754 /* if noDMA off, use DMAACC mode for memory read */
755 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
756 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
757 else
758 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
759 default:
760 LOG_ERROR("BUG: we shouldn't get here");
761 exit(-1);
762 break;
763 }
764
765 return ERROR_OK;
766 }
767
768 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
769 {
770 mips32_common_t *mips32 = target->arch_info;
771 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
772
773 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
774
775 if (target->state != TARGET_HALTED)
776 {
777 LOG_WARNING("target not halted");
778 return ERROR_TARGET_NOT_HALTED;
779 }
780
781 /* sanitize arguments */
782 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
783 return ERROR_INVALID_ARGUMENTS;
784
785 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
786 return ERROR_TARGET_UNALIGNED_ACCESS;
787
788 switch (size)
789 {
790 case 4:
791 case 2:
792 case 1:
793 /* if noDMA off, use DMAACC mode for memory write */
794 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
795 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
796 else
797 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
798 break;
799 default:
800 LOG_ERROR("BUG: we shouldn't get here");
801 exit(-1);
802 break;
803 }
804
805 return ERROR_OK;
806 }
807
808 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
809 {
810 int retval;
811
812 retval = mips32_register_commands(cmd_ctx);
813 return retval;
814 }
815
816 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
817 {
818 mips32_build_reg_cache(target);
819
820 return ERROR_OK;
821 }
822
823 int mips_m4k_quit(void)
824 {
825 return ERROR_OK;
826 }
827
828 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
829 {
830 mips32_common_t *mips32 = &mips_m4k->mips32_common;
831
832 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
833
834 /* initialize mips4k specific info */
835 mips32_init_arch_info(target, mips32, tap);
836 mips32->arch_info = mips_m4k;
837
838 return ERROR_OK;
839 }
840
841 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
842 {
843 mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
844
845 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
846
847 return ERROR_OK;
848 }
849
850 int mips_m4k_examine(struct target_s *target)
851 {
852 int retval;
853 mips32_common_t *mips32 = target->arch_info;
854 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
855 u32 idcode = 0;
856
857 if (!target->type->examined)
858 {
859 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
860 ejtag_info->idcode = idcode;
861
862 if (((idcode >> 1) & 0x7FF) == 0x29)
863 {
864 /* we are using a pic32mx so select ejtag port
865 * as it is not selected by default */
866 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
867 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
868 }
869 }
870
871 /* init rest of ejtag interface */
872 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
873 return retval;
874
875 if ((retval = mips32_examine(target)) != ERROR_OK)
876 return retval;
877
878 return ERROR_OK;
879 }
880
881 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
882 {
883 return mips_m4k_write_memory(target, address, 4, count, buffer);
884 }
885
886 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
887 {
888 return ERROR_FAIL; /* use bulk read method */
889 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)