1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
28 #include "breakpoints.h"
31 #include "mips32_dmaacc.h"
32 #include "target_type.h"
37 /* forward declarations */
38 int mips_m4k_poll(struct target
*target
);
39 int mips_m4k_halt(struct target
*target
);
40 int mips_m4k_soft_reset_halt(struct target
*target
);
41 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
);
42 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
);
43 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
44 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
45 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
);
46 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
);
48 int mips_m4k_examine(struct target
*target
);
49 int mips_m4k_assert_reset(struct target
*target
);
50 int mips_m4k_deassert_reset(struct target
*target
);
51 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
);
53 struct target_type mips_m4k_target
=
57 .poll
= mips_m4k_poll
,
58 .arch_state
= mips32_arch_state
,
60 .target_request_data
= NULL
,
62 .halt
= mips_m4k_halt
,
63 .resume
= mips_m4k_resume
,
64 .step
= mips_m4k_step
,
66 .assert_reset
= mips_m4k_assert_reset
,
67 .deassert_reset
= mips_m4k_deassert_reset
,
68 .soft_reset_halt
= mips_m4k_soft_reset_halt
,
70 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
72 .read_memory
= mips_m4k_read_memory
,
73 .write_memory
= mips_m4k_write_memory
,
74 .bulk_write_memory
= mips_m4k_bulk_write_memory
,
75 .checksum_memory
= mips_m4k_checksum_memory
,
76 .blank_check_memory
= NULL
,
78 .run_algorithm
= mips32_run_algorithm
,
80 .add_breakpoint
= mips_m4k_add_breakpoint
,
81 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
82 .add_watchpoint
= mips_m4k_add_watchpoint
,
83 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
85 .target_create
= mips_m4k_target_create
,
86 .init_target
= mips_m4k_init_target
,
87 .examine
= mips_m4k_examine
,
90 int mips_m4k_examine_debug_reason(struct target
*target
)
92 uint32_t break_status
;
95 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
96 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
98 /* get info about inst breakpoint support */
99 if ((retval
= target_read_u32(target
, EJTAG_IBS
, &break_status
)) != ERROR_OK
)
101 if (break_status
& 0x1f)
103 /* we have halted on a breakpoint */
104 if ((retval
= target_write_u32(target
, EJTAG_IBS
, 0)) != ERROR_OK
)
106 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
109 /* get info about data breakpoint support */
110 if ((retval
= target_read_u32(target
, 0xFF302000, &break_status
)) != ERROR_OK
)
112 if (break_status
& 0x1f)
114 /* we have halted on a breakpoint */
115 if ((retval
= target_write_u32(target
, 0xFF302000, 0)) != ERROR_OK
)
117 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
124 int mips_m4k_debug_entry(struct target
*target
)
126 struct mips32_common
*mips32
= target
->arch_info
;
127 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info
, &debug_reg
);
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target
);
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target
);
139 /* clear single step if active */
140 if (debug_reg
& EJTAG_DEBUG_DSS
)
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info
, 0);
146 mips32_save_context(target
);
148 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
149 *(uint32_t*)(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
),
150 target_state_name(target
));
155 int mips_m4k_poll(struct target
*target
)
158 struct mips32_common
*mips32
= target
->arch_info
;
159 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
160 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
162 /* read ejtag control reg */
163 jtag_set_end_state(TAP_IDLE
);
164 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
165 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
)
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_set_end_state(TAP_IDLE
);
174 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
176 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
177 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
178 LOG_DEBUG("Reset Detected");
181 /* check for processor halted */
182 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
)
184 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
186 jtag_set_end_state(TAP_IDLE
);
187 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
189 target
->state
= TARGET_HALTED
;
191 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
194 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
196 else if (target
->state
== TARGET_DEBUG_RUNNING
)
198 target
->state
= TARGET_HALTED
;
200 if ((retval
= mips_m4k_debug_entry(target
)) != ERROR_OK
)
203 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
208 target
->state
= TARGET_RUNNING
;
211 // LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
216 int mips_m4k_halt(struct target
*target
)
218 struct mips32_common
*mips32
= target
->arch_info
;
219 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
221 LOG_DEBUG("target->state: %s",
222 target_state_name(target
));
224 if (target
->state
== TARGET_HALTED
)
226 LOG_DEBUG("target was already halted");
230 if (target
->state
== TARGET_UNKNOWN
)
232 LOG_WARNING("target was in unknown state when halt was requested");
235 if (target
->state
== TARGET_RESET
)
237 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE
;
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
247 target
->debug_reason
= DBG_REASON_DBGRQ
;
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info
);
256 target
->debug_reason
= DBG_REASON_DBGRQ
;
261 int mips_m4k_assert_reset(struct target
*target
)
263 struct mips32_common
*mips32
= target
->arch_info
;
264 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
266 LOG_DEBUG("target->state: %s",
267 target_state_name(target
));
269 enum reset_types jtag_reset_config
= jtag_get_reset_config();
270 if (!(jtag_reset_config
& RESET_HAS_SRST
))
272 LOG_ERROR("Can't assert SRST");
276 if (target
->reset_halt
)
278 /* use hardware to catch reset */
279 jtag_set_end_state(TAP_IDLE
);
280 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
, NULL
);
284 jtag_set_end_state(TAP_IDLE
);
285 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
, NULL
);
288 if (strcmp(target
->variant
, "ejtag_srst") == 0)
290 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
291 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
292 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
, NULL
);
293 mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
297 /* here we should issue a srst only, but we may have to assert trst as well */
298 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
300 jtag_add_reset(1, 1);
304 jtag_add_reset(0, 1);
308 target
->state
= TARGET_RESET
;
309 jtag_add_sleep(50000);
311 register_cache_invalidate(mips32
->core_cache
);
313 if (target
->reset_halt
)
316 if ((retval
= target_halt(target
)) != ERROR_OK
)
323 int mips_m4k_deassert_reset(struct target
*target
)
325 LOG_DEBUG("target->state: %s",
326 target_state_name(target
));
328 /* deassert reset lines */
329 jtag_add_reset(0, 0);
334 int mips_m4k_soft_reset_halt(struct target
*target
)
340 int mips_m4k_single_step_core(struct target
*target
)
342 struct mips32_common
*mips32
= target
->arch_info
;
343 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
345 /* configure single step mode */
346 mips_ejtag_config_step(ejtag_info
, 1);
348 /* disable interrupts while stepping */
349 mips32_enable_interrupts(target
, 0);
351 /* exit debug mode */
352 mips_ejtag_exit_debug(ejtag_info
);
354 mips_m4k_debug_entry(target
);
359 int mips_m4k_resume(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
361 struct mips32_common
*mips32
= target
->arch_info
;
362 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
363 struct breakpoint
*breakpoint
= NULL
;
366 if (target
->state
!= TARGET_HALTED
)
368 LOG_WARNING("target not halted");
369 return ERROR_TARGET_NOT_HALTED
;
372 if (!debug_execution
)
374 target_free_all_working_areas(target
);
375 mips_m4k_enable_breakpoints(target
);
376 mips_m4k_enable_watchpoints(target
);
379 /* current = 1: continue on current pc, otherwise continue at <address> */
382 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
383 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
384 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
387 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
389 mips32_restore_context(target
);
391 /* the front-end may request us not to handle breakpoints */
392 if (handle_breakpoints
)
394 /* Single step past breakpoint at current address */
395 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
397 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
398 mips_m4k_unset_breakpoint(target
, breakpoint
);
399 mips_m4k_single_step_core(target
);
400 mips_m4k_set_breakpoint(target
, breakpoint
);
404 /* enable interrupts if we are running */
405 mips32_enable_interrupts(target
, !debug_execution
);
407 /* exit debug mode */
408 mips_ejtag_exit_debug(ejtag_info
);
409 target
->debug_reason
= DBG_REASON_NOTHALTED
;
411 /* registers are now invalid */
412 register_cache_invalidate(mips32
->core_cache
);
414 if (!debug_execution
)
416 target
->state
= TARGET_RUNNING
;
417 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
418 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
422 target
->state
= TARGET_DEBUG_RUNNING
;
423 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
424 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
430 int mips_m4k_step(struct target
*target
, int current
, uint32_t address
, int handle_breakpoints
)
432 /* get pointers to arch-specific information */
433 struct mips32_common
*mips32
= target
->arch_info
;
434 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
435 struct breakpoint
*breakpoint
= NULL
;
437 if (target
->state
!= TARGET_HALTED
)
439 LOG_WARNING("target not halted");
440 return ERROR_TARGET_NOT_HALTED
;
443 /* current = 1: continue on current pc, otherwise continue at <address> */
445 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
447 /* the front-end may request us not to handle breakpoints */
448 if (handle_breakpoints
)
449 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32))))
450 mips_m4k_unset_breakpoint(target
, breakpoint
);
452 /* restore context */
453 mips32_restore_context(target
);
455 /* configure single step mode */
456 mips_ejtag_config_step(ejtag_info
, 1);
458 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
460 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
462 /* disable interrupts while stepping */
463 mips32_enable_interrupts(target
, 0);
465 /* exit debug mode */
466 mips_ejtag_exit_debug(ejtag_info
);
468 /* registers are now invalid */
469 register_cache_invalidate(mips32
->core_cache
);
472 mips_m4k_set_breakpoint(target
, breakpoint
);
474 LOG_DEBUG("target stepped ");
476 mips_m4k_debug_entry(target
);
477 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
482 void mips_m4k_enable_breakpoints(struct target
*target
)
484 struct breakpoint
*breakpoint
= target
->breakpoints
;
486 /* set any pending breakpoints */
489 if (breakpoint
->set
== 0)
490 mips_m4k_set_breakpoint(target
, breakpoint
);
491 breakpoint
= breakpoint
->next
;
495 int mips_m4k_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
497 struct mips32_common
*mips32
= target
->arch_info
;
498 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
503 LOG_WARNING("breakpoint already set");
507 if (breakpoint
->type
== BKPT_HARD
)
511 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
513 if (bp_num
>= mips32
->num_inst_bpoints
)
515 LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
516 breakpoint
->unique_id
);
519 breakpoint
->set
= bp_num
+ 1;
520 comparator_list
[bp_num
].used
= 1;
521 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
522 target_write_u32(target
, comparator_list
[bp_num
].reg_address
, comparator_list
[bp_num
].bp_value
);
523 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x08, 0x00000000);
524 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 1);
525 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32
"",
526 breakpoint
->unique_id
,
527 bp_num
, comparator_list
[bp_num
].bp_value
);
529 else if (breakpoint
->type
== BKPT_SOFT
)
531 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
532 if (breakpoint
->length
== 4)
534 uint32_t verify
= 0xffffffff;
536 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
540 if ((retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP
)) != ERROR_OK
)
545 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
549 if (verify
!= MIPS32_SDBBP
)
551 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
557 uint16_t verify
= 0xffff;
559 if ((retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
563 if ((retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP
)) != ERROR_OK
)
568 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
572 if (verify
!= MIPS16_SDBBP
)
574 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
579 breakpoint
->set
= 20; /* Any nice value but 0 */
585 int mips_m4k_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
587 /* get pointers to arch-specific information */
588 struct mips32_common
*mips32
= target
->arch_info
;
589 struct mips32_comparator
* comparator_list
= mips32
->inst_break_list
;
592 if (!breakpoint
->set
)
594 LOG_WARNING("breakpoint not set");
598 if (breakpoint
->type
== BKPT_HARD
)
600 int bp_num
= breakpoint
->set
- 1;
601 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
))
603 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
604 breakpoint
->unique_id
);
607 LOG_DEBUG("bpid: %d - releasing hw: %d",
608 breakpoint
->unique_id
,
610 comparator_list
[bp_num
].used
= 0;
611 comparator_list
[bp_num
].bp_value
= 0;
612 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+ 0x18, 0);
617 /* restore original instruction (kept in target endianness) */
618 LOG_DEBUG("bpid: %d", breakpoint
->unique_id
);
619 if (breakpoint
->length
== 4)
621 uint32_t current_instr
;
623 /* check that user program has not modified breakpoint instruction */
624 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
628 if (current_instr
== MIPS32_SDBBP
)
630 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
638 uint16_t current_instr
;
640 /* check that user program has not modified breakpoint instruction */
641 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
646 if (current_instr
== MIPS16_SDBBP
)
648 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
660 int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
662 struct mips32_common
*mips32
= target
->arch_info
;
664 if (breakpoint
->type
== BKPT_HARD
)
666 if (mips32
->num_inst_bpoints_avail
< 1)
668 LOG_INFO("no hardware breakpoint available");
669 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
672 mips32
->num_inst_bpoints_avail
--;
675 mips_m4k_set_breakpoint(target
, breakpoint
);
680 int mips_m4k_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
682 /* get pointers to arch-specific information */
683 struct mips32_common
*mips32
= target
->arch_info
;
685 if (target
->state
!= TARGET_HALTED
)
687 LOG_WARNING("target not halted");
688 return ERROR_TARGET_NOT_HALTED
;
693 mips_m4k_unset_breakpoint(target
, breakpoint
);
696 if (breakpoint
->type
== BKPT_HARD
)
697 mips32
->num_inst_bpoints_avail
++;
702 int mips_m4k_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
704 struct mips32_common
*mips32
= target
->arch_info
;
705 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
708 * watchpoint enabled, ignore all byte lanes in value register
709 * and exclude both load and store accesses from watchpoint
710 * condition evaluation
712 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
713 (0xff << EJTAG_DBCn_BLM_SHIFT
);
717 LOG_WARNING("watchpoint already set");
721 while(comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
723 if (wp_num
>= mips32
->num_data_bpoints
)
725 LOG_ERROR("Can not find free FP Comparator");
729 if (watchpoint
->length
!= 4)
731 LOG_ERROR("Only watchpoints of length 4 are supported");
732 return ERROR_TARGET_UNALIGNED_ACCESS
;
735 if (watchpoint
->address
% 4)
737 LOG_ERROR("Watchpoints address should be word aligned");
738 return ERROR_TARGET_UNALIGNED_ACCESS
;
741 switch (watchpoint
->rw
)
744 enable
&= ~EJTAG_DBCn_NOLB
;
747 enable
&= ~EJTAG_DBCn_NOSB
;
750 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
753 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
756 watchpoint
->set
= wp_num
+ 1;
757 comparator_list
[wp_num
].used
= 1;
758 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
759 target_write_u32(target
, comparator_list
[wp_num
].reg_address
, comparator_list
[wp_num
].bp_value
);
760 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x08, 0x00000000);
761 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x10, 0x00000000);
762 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, enable
);
763 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x20, 0);
764 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
769 int mips_m4k_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
771 /* get pointers to arch-specific information */
772 struct mips32_common
*mips32
= target
->arch_info
;
773 struct mips32_comparator
* comparator_list
= mips32
->data_break_list
;
775 if (!watchpoint
->set
)
777 LOG_WARNING("watchpoint not set");
781 int wp_num
= watchpoint
->set
- 1;
782 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
))
784 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
787 comparator_list
[wp_num
].used
= 0;
788 comparator_list
[wp_num
].bp_value
= 0;
789 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+ 0x18, 0);
795 int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
797 struct mips32_common
*mips32
= target
->arch_info
;
799 if (mips32
->num_data_bpoints_avail
< 1)
801 LOG_INFO("no hardware watchpoints available");
802 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
805 mips32
->num_data_bpoints_avail
--;
807 mips_m4k_set_watchpoint(target
, watchpoint
);
811 int mips_m4k_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
813 /* get pointers to arch-specific information */
814 struct mips32_common
*mips32
= target
->arch_info
;
816 if (target
->state
!= TARGET_HALTED
)
818 LOG_WARNING("target not halted");
819 return ERROR_TARGET_NOT_HALTED
;
824 mips_m4k_unset_watchpoint(target
, watchpoint
);
827 mips32
->num_data_bpoints_avail
++;
832 void mips_m4k_enable_watchpoints(struct target
*target
)
834 struct watchpoint
*watchpoint
= target
->watchpoints
;
836 /* set any pending watchpoints */
839 if (watchpoint
->set
== 0)
840 mips_m4k_set_watchpoint(target
, watchpoint
);
841 watchpoint
= watchpoint
->next
;
845 int mips_m4k_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
847 struct mips32_common
*mips32
= target
->arch_info
;
848 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
850 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
852 if (target
->state
!= TARGET_HALTED
)
854 LOG_WARNING("target not halted");
855 return ERROR_TARGET_NOT_HALTED
;
858 /* sanitize arguments */
859 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
860 return ERROR_INVALID_ARGUMENTS
;
862 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
863 return ERROR_TARGET_UNALIGNED_ACCESS
;
865 /* if noDMA off, use DMAACC mode for memory read */
867 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
868 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
870 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
871 if (ERROR_OK
!= retval
)
877 int mips_m4k_write_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
879 struct mips32_common
*mips32
= target
->arch_info
;
880 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
882 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
884 if (target
->state
!= TARGET_HALTED
)
886 LOG_WARNING("target not halted");
887 return ERROR_TARGET_NOT_HALTED
;
890 /* sanitize arguments */
891 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
892 return ERROR_INVALID_ARGUMENTS
;
894 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
895 return ERROR_TARGET_UNALIGNED_ACCESS
;
897 /* if noDMA off, use DMAACC mode for memory write */
898 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
899 return mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
901 return mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, (void *)buffer
);
904 int mips_m4k_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
906 mips32_build_reg_cache(target
);
911 int mips_m4k_init_arch_info(struct target
*target
, struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
913 struct mips32_common
*mips32
= &mips_m4k
->mips32_common
;
915 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
917 /* initialize mips4k specific info */
918 mips32_init_arch_info(target
, mips32
, tap
);
919 mips32
->arch_info
= mips_m4k
;
924 int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
926 struct mips_m4k_common
*mips_m4k
= calloc(1,sizeof(struct mips_m4k_common
));
928 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
933 int mips_m4k_examine(struct target
*target
)
936 struct mips32_common
*mips32
= target
->arch_info
;
937 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
940 if (!target_was_examined(target
))
942 mips_ejtag_get_idcode(ejtag_info
, &idcode
);
943 ejtag_info
->idcode
= idcode
;
945 if (((idcode
>> 1) & 0x7FF) == 0x29)
947 /* we are using a pic32mx so select ejtag port
948 * as it is not selected by default */
949 mips_ejtag_set_instr(ejtag_info
, 0x05, NULL
);
950 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
954 /* init rest of ejtag interface */
955 if ((retval
= mips_ejtag_init(ejtag_info
)) != ERROR_OK
)
958 if ((retval
= mips32_examine(target
)) != ERROR_OK
)
964 int mips_m4k_bulk_write_memory(struct target
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
966 struct mips32_common
*mips32
= target
->arch_info
;
967 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
968 struct working_area
*source
;
972 LOG_DEBUG("address: 0x%8.8x, count: 0x%8.8x", address
, count
);
974 if (target
->state
!= TARGET_HALTED
)
976 LOG_WARNING("target not halted");
977 return ERROR_TARGET_NOT_HALTED
;
980 /* check alignment */
982 return ERROR_TARGET_UNALIGNED_ACCESS
;
984 /* Get memory for block write handler */
985 retval
= target_alloc_working_area(target
, MIPS32_FASTDATA_HANDLER_SIZE
, &source
);
986 if (retval
!= ERROR_OK
)
988 LOG_WARNING("No working area available, falling back to non-bulk write");
989 return mips_m4k_write_memory(target
, address
, 4, count
, buffer
);
992 /* TAP data register is loaded LSB first (little endian) */
993 if (target
->endianness
== TARGET_BIG_ENDIAN
)
996 for(i
= 0; i
< (count
* 4); i
+= 4)
998 t32
= be_to_h_u32((uint8_t *) &buffer
[i
]);
999 h_u32_to_le(&buffer
[i
], t32
);
1003 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, source
, write
, address
, count
, (uint32_t*) buffer
);
1006 target_free_working_area(target
, source
);
1011 int mips_m4k_checksum_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t *checksum
)
1013 return ERROR_FAIL
; /* use bulk read method */
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