src/target/nds32_aice.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes technology.                                  *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_NDS32_AICE_H
  20 #define OPENOCD_TARGET_NDS32_AICE_H
  21
  22 #include <jtag/aice/aice_port.h>
  23
  24 int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val);
  25 int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val);
  26 int aice_read_tlb(struct aice_port_s *aice, target_addr_t virtual_address,
  27                 target_addr_t *physical_address);
  28 int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address);
  29 int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times);
  30 int aice_program_edm(struct aice_port_s *aice, char *command_sequence);
  31 int aice_set_command_mode(struct aice_port_s *aice,
  32                 enum aice_command_mode command_mode);
  33 int aice_execute(struct aice_port_s *aice, uint32_t *instructions,
  34                 uint32_t instruction_num);
  35 int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script);
  36 int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script);
  37 int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script);
  38 int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check);
  39 int aice_profiling(struct aice_port_s *aice, uint32_t interval, uint32_t iteration,
  40                 uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
  41
  42 static inline int aice_open(struct aice_port_s *aice, struct aice_port_param_s *param)
  43 {
  44         return aice->port->api->open(param);
  45 }
  46
  47 static inline int aice_close(struct aice_port_s *aice)
  48 {
  49         return aice->port->api->close();
  50 }
  51
  52 static inline int aice_reset(struct aice_port_s *aice)
  53 {
  54         return aice->port->api->reset();
  55 }
  56
  57 static inline int aice_assert_srst(struct aice_port_s *aice,
  58                 enum aice_srst_type_s srst)
  59 {
  60         return aice->port->api->assert_srst(aice->coreid, srst);
  61 }
  62
  63 static inline int aice_run(struct aice_port_s *aice)
  64 {
  65         return aice->port->api->run(aice->coreid);
  66 }
  67
  68 static inline int aice_halt(struct aice_port_s *aice)
  69 {
  70         return aice->port->api->halt(aice->coreid);
  71 }
  72
  73 static inline int aice_step(struct aice_port_s *aice)
  74 {
  75         return aice->port->api->step(aice->coreid);
  76 }
  77
  78 static inline int aice_read_register(struct aice_port_s *aice, uint32_t num,
  79                 uint32_t *val)
  80 {
  81         return aice->port->api->read_reg(aice->coreid, num, val);
  82 }
  83
  84 static inline int aice_write_register(struct aice_port_s *aice, uint32_t num,
  85                 uint32_t val)
  86 {
  87         return aice->port->api->write_reg(aice->coreid, num, val);
  88 }
  89
  90 static inline int aice_read_debug_reg(struct aice_port_s *aice, uint32_t addr,
  91                 uint32_t *val)
  92 {
  93         return aice->port->api->read_debug_reg(aice->coreid, addr, val);
  94 }
  95
  96 static inline int aice_write_debug_reg(struct aice_port_s *aice, uint32_t addr,
  97                 const uint32_t val)
  98 {
  99         return aice->port->api->write_debug_reg(aice->coreid, addr, val);
 100 }
 101
 102 static inline int aice_read_mem_unit(struct aice_port_s *aice, uint32_t addr,
 103                 uint32_t size, uint32_t count, uint8_t *buffer)
 104 {
 105         return aice->port->api->read_mem_unit(aice->coreid, addr, size, count, buffer);
 106 }
 107
 108 static inline int aice_write_mem_unit(struct aice_port_s *aice, uint32_t addr,
 109                 uint32_t size, uint32_t count, const uint8_t *buffer)
 110 {
 111         return aice->port->api->write_mem_unit(aice->coreid, addr, size, count, buffer);
 112 }
 113
 114 static inline int aice_read_mem_bulk(struct aice_port_s *aice, uint32_t addr,
 115                 uint32_t length, uint8_t *buffer)
 116 {
 117         return aice->port->api->read_mem_bulk(aice->coreid, addr, length, buffer);
 118 }
 119
 120 static inline int aice_write_mem_bulk(struct aice_port_s *aice, uint32_t addr,
 121                 uint32_t length, const uint8_t *buffer)
 122 {
 123         return aice->port->api->write_mem_bulk(aice->coreid, addr, length, buffer);
 124 }
 125
 126 static inline int aice_idcode(struct aice_port_s *aice, uint32_t *idcode,
 127                 uint8_t *num_of_idcode)
 128 {
 129         return aice->port->api->idcode(idcode, num_of_idcode);
 130 }
 131
 132 static inline int aice_state(struct aice_port_s *aice,
 133                 enum aice_target_state_s *state)
 134 {
 135         return aice->port->api->state(aice->coreid, state);
 136 }
 137
 138 static inline int aice_set_jtag_clock(struct aice_port_s *aice, uint32_t a_clock)
 139 {
 140         return aice->port->api->set_jtag_clock(a_clock);
 141 }
 142
 143 static inline int aice_memory_access(struct aice_port_s *aice,
 144                 enum nds_memory_access a_access)
 145 {
 146         return aice->port->api->memory_access(aice->coreid, a_access);
 147 }
 148
 149 static inline int aice_memory_mode(struct aice_port_s *aice,
 150                 enum nds_memory_select mem_select)
 151 {
 152         return aice->port->api->memory_mode(aice->coreid, mem_select);
 153 }
 154
 155 static inline int aice_set_data_endian(struct aice_port_s *aice,
 156                 enum aice_target_endian target_data_endian)
 157 {
 158         return aice->port->api->set_data_endian(aice->coreid, target_data_endian);
 159 }
 160
 161 #endif /* OPENOCD_TARGET_NDS32_AICE_H */