1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
12 #include <helper/command.h>
14 #include "nds32_aice.h"
15 #include "nds32_disassembler.h"
17 extern struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
18 extern uint32_t nds32_edm_ops_num
;
20 static const char *const nds_memory_access_name
[] = {
25 static const char *const nds_memory_select_name
[] = {
32 COMMAND_HANDLER(handle_nds32_dssim_command
)
34 struct target
*target
= get_current_target(CMD_CTX
);
35 struct nds32
*nds32
= target_to_nds32(target
);
37 if (!is_nds32(nds32
)) {
38 command_print(CMD
, "current target isn't an Andes core");
43 if (strcmp(CMD_ARGV
[0], "on") == 0)
44 nds32
->step_isr_enable
= true;
45 if (strcmp(CMD_ARGV
[0], "off") == 0)
46 nds32
->step_isr_enable
= false;
49 command_print(CMD
, "%s: $INT_MASK.DSSIM: %d", target_name(target
),
50 nds32
->step_isr_enable
);
55 COMMAND_HANDLER(handle_nds32_memory_access_command
)
57 struct target
*target
= get_current_target(CMD_CTX
);
58 struct nds32
*nds32
= target_to_nds32(target
);
59 struct aice_port_s
*aice
= target_to_aice(target
);
60 struct nds32_memory
*memory
= &(nds32
->memory
);
62 if (!is_nds32(nds32
)) {
63 command_print(CMD
, "current target isn't an Andes core");
68 if (strcmp(CMD_ARGV
[0], "bus") == 0)
69 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
70 else if (strcmp(CMD_ARGV
[0], "cpu") == 0)
71 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
72 else /* default access channel is NDS_MEMORY_ACC_CPU */
73 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
75 LOG_DEBUG("memory access channel is changed to %s",
76 nds_memory_access_name
[memory
->access_channel
]);
78 aice_memory_access(aice
, memory
->access_channel
);
80 command_print(CMD
, "%s: memory access channel: %s",
82 nds_memory_access_name
[memory
->access_channel
]);
88 COMMAND_HANDLER(handle_nds32_memory_mode_command
)
90 struct target
*target
= get_current_target(CMD_CTX
);
91 struct nds32
*nds32
= target_to_nds32(target
);
92 struct aice_port_s
*aice
= target_to_aice(target
);
94 if (!is_nds32(nds32
)) {
95 command_print(CMD
, "current target isn't an Andes core");
101 if (nds32
->edm
.access_control
== false) {
102 command_print(CMD
, "%s does not support ACC_CTL. "
103 "Set memory mode to MEMORY", target_name(target
));
104 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
105 } else if (nds32
->edm
.direct_access_local_memory
== false) {
106 command_print(CMD
, "%s does not support direct access "
107 "local memory. Set memory mode to MEMORY",
108 target_name(target
));
109 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
112 aice_memory_mode(aice
, nds32
->memory
.mode
);
114 if (strcmp(CMD_ARGV
[0], "auto") == 0) {
115 nds32
->memory
.mode
= NDS_MEMORY_SELECT_AUTO
;
116 } else if (strcmp(CMD_ARGV
[0], "mem") == 0) {
117 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
118 } else if (strcmp(CMD_ARGV
[0], "ilm") == 0) {
119 if (nds32
->memory
.ilm_base
== 0)
120 command_print(CMD
, "%s does not support ILM",
121 target_name(target
));
123 nds32
->memory
.mode
= NDS_MEMORY_SELECT_ILM
;
124 } else if (strcmp(CMD_ARGV
[0], "dlm") == 0) {
125 if (nds32
->memory
.dlm_base
== 0)
126 command_print(CMD
, "%s does not support DLM",
127 target_name(target
));
129 nds32
->memory
.mode
= NDS_MEMORY_SELECT_DLM
;
133 aice_memory_mode(aice
, nds32
->memory
.mode
);
137 command_print(CMD
, "%s: memory mode: %s",
139 nds_memory_select_name
[nds32
->memory
.mode
]);
144 COMMAND_HANDLER(handle_nds32_cache_command
)
146 struct target
*target
= get_current_target(CMD_CTX
);
147 struct nds32
*nds32
= target_to_nds32(target
);
148 struct aice_port_s
*aice
= target_to_aice(target
);
149 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
150 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
153 if (!is_nds32(nds32
)) {
154 command_print(CMD
, "current target isn't an Andes core");
160 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
161 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
163 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
164 if (result
!= ERROR_OK
) {
165 command_print(CMD
, "%s: Write back data cache...failed",
166 target_name(target
));
170 command_print(CMD
, "%s: Write back data cache...done",
171 target_name(target
));
174 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
175 if (result
!= ERROR_OK
) {
176 command_print(CMD
, "%s: Invalidate data cache...failed",
177 target_name(target
));
181 command_print(CMD
, "%s: Invalidate data cache...done",
182 target_name(target
));
184 if (dcache
->line_size
== 0)
185 command_print(CMD
, "%s: No data cache",
186 target_name(target
));
188 command_print(CMD
, "%s: Data cache disabled",
189 target_name(target
));
192 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
194 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
195 if (result
!= ERROR_OK
) {
196 command_print(CMD
, "%s: Invalidate instruction cache...failed",
197 target_name(target
));
201 command_print(CMD
, "%s: Invalidate instruction cache...done",
202 target_name(target
));
204 if (icache
->line_size
== 0)
205 command_print(CMD
, "%s: No instruction cache",
206 target_name(target
));
208 command_print(CMD
, "%s: Instruction cache disabled",
209 target_name(target
));
212 command_print(CMD
, "No valid parameter");
218 COMMAND_HANDLER(handle_nds32_icache_command
)
220 struct target
*target
= get_current_target(CMD_CTX
);
221 struct nds32
*nds32
= target_to_nds32(target
);
222 struct aice_port_s
*aice
= target_to_aice(target
);
223 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
226 if (!is_nds32(nds32
)) {
227 command_print(CMD
, "current target isn't an Andes core");
233 if (icache
->line_size
== 0) {
234 command_print(CMD
, "%s: No instruction cache",
235 target_name(target
));
239 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
240 if (icache
->enable
== true) {
242 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
243 if (result
!= ERROR_OK
) {
244 command_print(CMD
, "%s: Invalidate instruction cache...failed",
245 target_name(target
));
249 command_print(CMD
, "%s: Invalidate instruction cache...done",
250 target_name(target
));
252 command_print(CMD
, "%s: Instruction cache disabled",
253 target_name(target
));
255 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
257 nds32_get_mapped_reg(nds32
, IR8
, &value
);
258 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x1);
259 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
261 nds32_get_mapped_reg(nds32
, IR8
, &value
);
262 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x1);
263 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
264 /* TODO: dump cache content */
266 command_print(CMD
, "%s: No valid parameter", target_name(target
));
273 COMMAND_HANDLER(handle_nds32_dcache_command
)
275 struct target
*target
= get_current_target(CMD_CTX
);
276 struct nds32
*nds32
= target_to_nds32(target
);
277 struct aice_port_s
*aice
= target_to_aice(target
);
278 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
281 if (!is_nds32(nds32
)) {
282 command_print(CMD
, "current target isn't an Andes core");
288 if (dcache
->line_size
== 0) {
289 command_print(CMD
, "%s: No data cache", target_name(target
));
293 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
294 if (dcache
->enable
== true) {
296 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
297 if (result
!= ERROR_OK
) {
298 command_print(CMD
, "%s: Write back data cache...failed",
299 target_name(target
));
303 command_print(CMD
, "%s: Write back data cache...done",
304 target_name(target
));
307 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
308 if (result
!= ERROR_OK
) {
309 command_print(CMD
, "%s: Invalidate data cache...failed",
310 target_name(target
));
314 command_print(CMD
, "%s: Invalidate data cache...done",
315 target_name(target
));
317 command_print(CMD
, "%s: Data cache disabled",
318 target_name(target
));
320 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
322 nds32_get_mapped_reg(nds32
, IR8
, &value
);
323 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x2);
324 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
326 nds32_get_mapped_reg(nds32
, IR8
, &value
);
327 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x2);
328 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
329 /* TODO: dump cache content */
331 command_print(CMD
, "%s: No valid parameter", target_name(target
));
338 COMMAND_HANDLER(handle_nds32_auto_break_command
)
340 struct target
*target
= get_current_target(CMD_CTX
);
341 struct nds32
*nds32
= target_to_nds32(target
);
343 if (!is_nds32(nds32
)) {
344 command_print(CMD
, "current target isn't an Andes core");
349 if (strcmp(CMD_ARGV
[0], "on") == 0)
350 nds32
->auto_convert_hw_bp
= true;
351 if (strcmp(CMD_ARGV
[0], "off") == 0)
352 nds32
->auto_convert_hw_bp
= false;
355 if (nds32
->auto_convert_hw_bp
)
356 command_print(CMD
, "%s: convert sw break to hw break on ROM: on",
357 target_name(target
));
359 command_print(CMD
, "%s: convert sw break to hw break on ROM: off",
360 target_name(target
));
365 COMMAND_HANDLER(handle_nds32_virtual_hosting_command
)
367 struct target
*target
= get_current_target(CMD_CTX
);
368 struct nds32
*nds32
= target_to_nds32(target
);
370 if (!is_nds32(nds32
)) {
371 command_print(CMD
, "current target isn't an Andes core");
376 if (strcmp(CMD_ARGV
[0], "on") == 0)
377 nds32
->virtual_hosting
= true;
378 if (strcmp(CMD_ARGV
[0], "off") == 0)
379 nds32
->virtual_hosting
= false;
382 if (nds32
->virtual_hosting
)
383 command_print(CMD
, "%s: virtual hosting: on", target_name(target
));
385 command_print(CMD
, "%s: virtual hosting: off", target_name(target
));
390 COMMAND_HANDLER(handle_nds32_global_stop_command
)
392 struct target
*target
= get_current_target(CMD_CTX
);
393 struct nds32
*nds32
= target_to_nds32(target
);
395 if (!is_nds32(nds32
)) {
396 command_print(CMD
, "current target isn't an Andes core");
401 if (strcmp(CMD_ARGV
[0], "on") == 0)
402 nds32
->global_stop
= true;
403 if (strcmp(CMD_ARGV
[0], "off") == 0)
404 nds32
->global_stop
= false;
407 if (nds32
->global_stop
)
408 LOG_INFO("%s: global stop: on", target_name(target
));
410 LOG_INFO("%s: global stop: off", target_name(target
));
415 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command
)
417 struct target
*target
= get_current_target(CMD_CTX
);
418 struct nds32
*nds32
= target_to_nds32(target
);
420 if (!is_nds32(nds32
)) {
421 command_print(CMD
, "current target isn't an Andes core");
426 if (strcmp(CMD_ARGV
[0], "on") == 0)
427 nds32
->soft_reset_halt
= true;
428 if (strcmp(CMD_ARGV
[0], "off") == 0)
429 nds32
->soft_reset_halt
= false;
432 if (nds32
->soft_reset_halt
)
433 LOG_INFO("%s: soft-reset-halt: on", target_name(target
));
435 LOG_INFO("%s: soft-reset-halt: off", target_name(target
));
440 COMMAND_HANDLER(handle_nds32_boot_time_command
)
442 struct target
*target
= get_current_target(CMD_CTX
);
443 struct nds32
*nds32
= target_to_nds32(target
);
445 if (!is_nds32(nds32
)) {
446 command_print(CMD
, "current target isn't an Andes core");
451 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], nds32
->boot_time
);
456 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command
)
458 struct target
*target
= get_current_target(CMD_CTX
);
459 struct nds32
*nds32
= target_to_nds32(target
);
461 if (!is_nds32(nds32
)) {
462 command_print(CMD
, "current target isn't an Andes core");
466 nds32
->edm_passcode
= strdup(CMD_ARGV
[0]);
471 COMMAND_HANDLER(handle_nds32_login_edm_operation_command
)
473 struct target
*target
= get_current_target(CMD_CTX
);
474 struct nds32
*nds32
= target_to_nds32(target
);
476 if (!is_nds32(nds32
)) {
477 command_print(CMD
, "current target isn't an Andes core");
483 uint32_t misc_reg_no
;
486 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], misc_reg_no
);
487 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], data
);
489 if (nds32_edm_ops_num
>= NDS32_EDM_OPERATION_MAX_NUM
)
492 /* Just save the operation. Execute it in nds32_login() */
493 nds32_edm_ops
[nds32_edm_ops_num
].reg_no
= misc_reg_no
;
494 nds32_edm_ops
[nds32_edm_ops_num
].value
= data
;
502 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command
)
504 struct target
*target
= get_current_target(CMD_CTX
);
505 struct nds32
*nds32
= target_to_nds32(target
);
507 if (!is_nds32(nds32
)) {
508 command_print(CMD
, "current target isn't an Andes core");
513 if (strcmp(CMD_ARGV
[0], "on") == 0)
514 nds32
->reset_halt_as_examine
= true;
515 if (strcmp(CMD_ARGV
[0], "off") == 0)
516 nds32
->reset_halt_as_examine
= false;
522 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command
)
524 struct target
*target
= get_current_target(CMD_CTX
);
525 struct nds32
*nds32
= target_to_nds32(target
);
527 if (!is_nds32(nds32
)) {
528 command_print(CMD
, "current target isn't an Andes core");
533 if (strcmp(CMD_ARGV
[0], "on") == 0)
534 nds32
->keep_target_edm_ctl
= true;
535 if (strcmp(CMD_ARGV
[0], "off") == 0)
536 nds32
->keep_target_edm_ctl
= false;
542 COMMAND_HANDLER(handle_nds32_decode_command
)
544 struct target
*target
= get_current_target(CMD_CTX
);
545 struct nds32
*nds32
= target_to_nds32(target
);
547 if (!is_nds32(nds32
)) {
548 command_print(CMD
, "current target isn't an Andes core");
559 struct nds32_instruction instruction
;
561 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
562 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], insn_count
);
566 while (i
< insn_count
) {
567 if (nds32_read_opcode(nds32
, read_addr
, &opcode
) != ERROR_OK
)
569 if (nds32_evaluate_opcode(nds32
, opcode
, read_addr
, &instruction
) != ERROR_OK
)
572 command_print(CMD
, "%s", instruction
.text
);
574 read_addr
+= instruction
.instruction_size
;
577 } else if (CMD_ARGC
== 1) {
581 struct nds32_instruction instruction
;
583 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
585 if (nds32_read_opcode(nds32
, addr
, &opcode
) != ERROR_OK
)
587 if (nds32_evaluate_opcode(nds32
, opcode
, addr
, &instruction
) != ERROR_OK
)
590 command_print(CMD
, "%s", instruction
.text
);
597 COMMAND_HANDLER(handle_nds32_word_access_mem_command
)
599 struct target
*target
= get_current_target(CMD_CTX
);
600 struct nds32
*nds32
= target_to_nds32(target
);
602 if (!is_nds32(nds32
)) {
603 command_print(CMD
, "current target isn't an Andes core");
608 if (strcmp(CMD_ARGV
[0], "on") == 0)
609 nds32
->word_access_mem
= true;
610 if (strcmp(CMD_ARGV
[0], "off") == 0)
611 nds32
->word_access_mem
= false;
617 COMMAND_HANDLER(handle_nds32_query_target_command
)
619 struct target
*target
= get_current_target(CMD_CTX
);
620 struct nds32
*nds32
= target_to_nds32(target
);
622 if (!is_nds32(nds32
)) {
623 command_print(CMD
, "current target isn't an Andes core");
627 command_print(CMD
, "OCD");
632 COMMAND_HANDLER(handle_nds32_query_endian_command
)
634 struct target
*target
= get_current_target(CMD_CTX
);
635 struct nds32
*nds32
= target_to_nds32(target
);
637 if (!is_nds32(nds32
)) {
638 command_print(CMD
, "current target isn't an Andes core");
643 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
645 if (value_psw
& 0x20)
646 command_print(CMD
, "%s: BE", target_name(target
));
648 command_print(CMD
, "%s: LE", target_name(target
));
653 COMMAND_HANDLER(handle_nds32_query_cpuid_command
)
655 struct target
*target
= get_current_target(CMD_CTX
);
656 struct nds32
*nds32
= target_to_nds32(target
);
658 if (!is_nds32(nds32
)) {
659 command_print(CMD
, "current target isn't an Andes core");
663 command_print(CMD
, "CPUID: %s", target_name(target
));
668 static int jim_nds32_bulk_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
670 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
672 struct jim_getopt_info goi
;
673 jim_getopt_setup(&goi
, interp
, argc
- 1, argv
+ 1);
676 Jim_SetResultFormatted(goi
.interp
,
677 "usage: %s <address> <count> <data>", cmd_name
);
683 e
= jim_getopt_wide(&goi
, &address
);
688 e
= jim_getopt_wide(&goi
, &count
);
692 uint32_t *data
= malloc(count
* sizeof(uint32_t));
697 for (i
= 0; i
< count
; i
++) {
699 e
= jim_getopt_wide(&goi
, &tmp
);
704 data
[i
] = (uint32_t)tmp
;
707 /* all args must be consumed */
713 struct command_context
*cmd_ctx
= current_command_context(interp
);
715 struct target
*target
= get_current_target(cmd_ctx
);
718 result
= target_write_buffer(target
, address
, count
* 4, (const uint8_t *)data
);
725 static int jim_nds32_multi_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
727 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
729 struct jim_getopt_info goi
;
730 jim_getopt_setup(&goi
, interp
, argc
- 1, argv
+ 1);
733 Jim_SetResultFormatted(goi
.interp
,
734 "usage: %s # of pairs [<address> <data>]+", cmd_name
);
739 jim_wide num_of_pairs
;
740 e
= jim_getopt_wide(&goi
, &num_of_pairs
);
744 struct command_context
*cmd_ctx
= current_command_context(interp
);
746 struct target
*target
= get_current_target(cmd_ctx
);
747 struct aice_port_s
*aice
= target_to_aice(target
);
753 aice_set_command_mode(aice
, AICE_COMMAND_MODE_PACK
);
754 for (i
= 0; i
< num_of_pairs
; i
++) {
756 e
= jim_getopt_wide(&goi
, &tmp
);
759 address
= (uint32_t)tmp
;
761 e
= jim_getopt_wide(&goi
, &tmp
);
764 data
= (uint32_t)tmp
;
766 result
= target_write_buffer(target
, address
, 4, (const uint8_t *)&data
);
767 if (result
!= ERROR_OK
)
770 aice_set_command_mode(aice
, AICE_COMMAND_MODE_NORMAL
);
772 /* all args must be consumed */
779 static int jim_nds32_bulk_read(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
781 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
783 struct jim_getopt_info goi
;
784 jim_getopt_setup(&goi
, interp
, argc
- 1, argv
+ 1);
787 Jim_SetResultFormatted(goi
.interp
,
788 "usage: %s <address> <count>", cmd_name
);
794 e
= jim_getopt_wide(&goi
, &address
);
799 e
= jim_getopt_wide(&goi
, &count
);
803 /* all args must be consumed */
807 struct command_context
*cmd_ctx
= current_command_context(interp
);
809 struct target
*target
= get_current_target(cmd_ctx
);
810 uint32_t *data
= malloc(count
* sizeof(uint32_t));
812 result
= target_read_buffer(target
, address
, count
* 4, (uint8_t *)data
);
816 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
817 for (i
= 0; i
< count
; i
++) {
818 sprintf(data_str
, "0x%08" PRIx32
" ", data
[i
]);
819 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
827 static int jim_nds32_read_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
829 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
831 struct jim_getopt_info goi
;
832 jim_getopt_setup(&goi
, interp
, argc
- 1, argv
+ 1);
835 Jim_SetResultFormatted(goi
.interp
,
836 "usage: %s <edm_sr_name>", cmd_name
);
841 const char *edm_sr_name
;
843 e
= jim_getopt_string(&goi
, &edm_sr_name
, &edm_sr_name_len
);
847 /* all args must be consumed */
851 uint32_t edm_sr_number
;
852 uint32_t edm_sr_value
;
853 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
854 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
855 else if (strncmp(edm_sr_name
, "edmsw", edm_sr_name_len
) == 0)
856 edm_sr_number
= NDS_EDM_SR_EDMSW
;
860 struct command_context
*cmd_ctx
= current_command_context(interp
);
862 struct target
*target
= get_current_target(cmd_ctx
);
863 struct aice_port_s
*aice
= target_to_aice(target
);
866 aice_read_debug_reg(aice
, edm_sr_number
, &edm_sr_value
);
868 sprintf(data_str
, "0x%08" PRIx32
, edm_sr_value
);
869 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
870 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
875 static int jim_nds32_write_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
877 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
879 struct jim_getopt_info goi
;
880 jim_getopt_setup(&goi
, interp
, argc
- 1, argv
+ 1);
883 Jim_SetResultFormatted(goi
.interp
,
884 "usage: %s <edm_sr_name> <value>", cmd_name
);
889 const char *edm_sr_name
;
891 e
= jim_getopt_string(&goi
, &edm_sr_name
, &edm_sr_name_len
);
896 e
= jim_getopt_wide(&goi
, &value
);
900 /* all args must be consumed */
904 uint32_t edm_sr_number
;
905 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
906 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
910 struct command_context
*cmd_ctx
= current_command_context(interp
);
912 struct target
*target
= get_current_target(cmd_ctx
);
913 struct aice_port_s
*aice
= target_to_aice(target
);
915 aice_write_debug_reg(aice
, edm_sr_number
, value
);
920 static const struct command_registration nds32_query_command_handlers
[] = {
923 .handler
= handle_nds32_query_target_command
,
924 .mode
= COMMAND_EXEC
,
926 .help
= "reply 'OCD' for gdb to identify server-side is OpenOCD",
930 .handler
= handle_nds32_query_endian_command
,
931 .mode
= COMMAND_EXEC
,
933 .help
= "query target endian",
937 .handler
= handle_nds32_query_cpuid_command
,
938 .mode
= COMMAND_EXEC
,
940 .help
= "query CPU ID",
943 COMMAND_REGISTRATION_DONE
946 static const struct command_registration nds32_exec_command_handlers
[] = {
949 .handler
= handle_nds32_dssim_command
,
950 .mode
= COMMAND_EXEC
,
951 .usage
= "['on'|'off']",
952 .help
= "display/change $INT_MASK.DSSIM status",
955 .name
= "mem_access",
956 .handler
= handle_nds32_memory_access_command
,
957 .mode
= COMMAND_EXEC
,
958 .usage
= "['bus'|'cpu']",
959 .help
= "display/change memory access channel",
963 .handler
= handle_nds32_memory_mode_command
,
964 .mode
= COMMAND_EXEC
,
965 .usage
= "['auto'|'mem'|'ilm'|'dlm']",
966 .help
= "display/change memory mode",
970 .handler
= handle_nds32_cache_command
,
971 .mode
= COMMAND_EXEC
,
972 .usage
= "['invalidate']",
973 .help
= "cache control",
977 .handler
= handle_nds32_icache_command
,
978 .mode
= COMMAND_EXEC
,
979 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
980 .help
= "icache control",
984 .handler
= handle_nds32_dcache_command
,
985 .mode
= COMMAND_EXEC
,
986 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
987 .help
= "dcache control",
990 .name
= "auto_break",
991 .handler
= handle_nds32_auto_break_command
,
992 .mode
= COMMAND_EXEC
,
993 .usage
= "['on'|'off']",
994 .help
= "convert software breakpoints to hardware breakpoints if needed",
997 .name
= "virtual_hosting",
998 .handler
= handle_nds32_virtual_hosting_command
,
1000 .usage
= "['on'|'off']",
1001 .help
= "turn on/off virtual hosting",
1004 .name
= "global_stop",
1005 .handler
= handle_nds32_global_stop_command
,
1006 .mode
= COMMAND_ANY
,
1007 .usage
= "['on'|'off']",
1008 .help
= "turn on/off global stop. After turning on, every load/store "
1009 "instructions will be stopped to check memory access.",
1012 .name
= "soft_reset_halt",
1013 .handler
= handle_nds32_soft_reset_halt_command
,
1014 .mode
= COMMAND_ANY
,
1015 .usage
= "['on'|'off']",
1016 .help
= "as issuing rest-halt, to use soft-reset-halt or not."
1017 "the feature is for backward-compatible.",
1020 .name
= "boot_time",
1021 .handler
= handle_nds32_boot_time_command
,
1022 .mode
= COMMAND_CONFIG
,
1023 .usage
= "milliseconds",
1024 .help
= "set the period to wait after srst.",
1027 .name
= "login_edm_passcode",
1028 .handler
= handle_nds32_login_edm_passcode_command
,
1029 .mode
= COMMAND_CONFIG
,
1030 .usage
= "passcode",
1031 .help
= "set EDM passcode for secure MCU debugging.",
1034 .name
= "login_edm_operation",
1035 .handler
= handle_nds32_login_edm_operation_command
,
1036 .mode
= COMMAND_CONFIG
,
1037 .usage
= "misc_reg_no value",
1038 .help
= "add EDM operations for secure MCU debugging.",
1041 .name
= "reset_halt_as_init",
1042 .handler
= handle_nds32_reset_halt_as_init_command
,
1043 .mode
= COMMAND_CONFIG
,
1044 .usage
= "['on'|'off']",
1045 .help
= "reset halt as openocd init.",
1048 .name
= "keep_target_edm_ctl",
1049 .handler
= handle_nds32_keep_target_edm_ctl_command
,
1050 .mode
= COMMAND_CONFIG
,
1051 .usage
= "['on'|'off']",
1052 .help
= "Backup/Restore target EDM_CTL register.",
1056 .handler
= handle_nds32_decode_command
,
1057 .mode
= COMMAND_EXEC
,
1058 .usage
= "address icount",
1059 .help
= "decode instruction.",
1062 .name
= "word_access_mem",
1063 .handler
= handle_nds32_word_access_mem_command
,
1064 .mode
= COMMAND_ANY
,
1065 .usage
= "['on'|'off']",
1066 .help
= "Always use word-aligned address to access memory.",
1069 .name
= "bulk_write",
1070 .jim_handler
= jim_nds32_bulk_write
,
1071 .mode
= COMMAND_EXEC
,
1072 .help
= "Write multiple 32-bit words to target memory",
1073 .usage
= "address count data",
1076 .name
= "multi_write",
1077 .jim_handler
= jim_nds32_multi_write
,
1078 .mode
= COMMAND_EXEC
,
1079 .help
= "Write multiple addresses/words to target memory",
1080 .usage
= "num_of_pairs [address data]+",
1083 .name
= "bulk_read",
1084 .jim_handler
= jim_nds32_bulk_read
,
1085 .mode
= COMMAND_EXEC
,
1086 .help
= "Read multiple 32-bit words from target memory",
1087 .usage
= "address count",
1090 .name
= "read_edmsr",
1091 .jim_handler
= jim_nds32_read_edm_sr
,
1092 .mode
= COMMAND_EXEC
,
1093 .help
= "Read EDM system register",
1094 .usage
= "['edmsw'|'edm_dtr']",
1097 .name
= "write_edmsr",
1098 .jim_handler
= jim_nds32_write_edm_sr
,
1099 .mode
= COMMAND_EXEC
,
1100 .help
= "Write EDM system register",
1101 .usage
= "['edm_dtr'] value",
1105 .mode
= COMMAND_EXEC
,
1106 .help
= "Andes query command group",
1108 .chain
= nds32_query_command_handlers
,
1111 COMMAND_REGISTRATION_DONE
1114 const struct command_registration nds32_command_handlers
[] = {
1117 .mode
= COMMAND_ANY
,
1118 .help
= "Andes command group",
1120 .chain
= nds32_exec_command_handlers
,
1122 COMMAND_REGISTRATION_DONE
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