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target/mips: Use 'bool' data type
[openocd.git] / src / target / nds32_disassembler.c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/log.h>
24 #include <target/target.h>
25 #include "nds32_disassembler.h"
26
27 static const int enable4_bits[] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
28
29 int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value)
30 {
31 struct target *target = nds32->target;
32 uint8_t value_buf[4];
33
34 if (!target_was_examined(target)) {
35 LOG_ERROR("Target not examined yet");
36 return ERROR_FAIL;
37 }
38
39 int retval = target_read_buffer(target, address, 4, value_buf);
40
41 if (retval == ERROR_OK) {
42 /* instructions are always big-endian */
43 *value = be_to_h_u32(value_buf);
44
45 LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "",
46 address,
47 *value);
48 } else {
49 *value = 0x0;
50 LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
51 address);
52 }
53
54 return retval;
55 }
56
57 static int nds32_parse_type_0(uint32_t opcode, int32_t *imm)
58 {
59 *imm = opcode & 0x1FFFFFF;
60
61 return ERROR_OK;
62 }
63
64 static int nds32_parse_type_1(uint32_t opcode, uint8_t *rt, int32_t *imm)
65 {
66 *rt = (opcode >> 20) & 0x1F;
67 *imm = opcode & 0xFFFFF;
68
69 return ERROR_OK;
70 }
71
72 static int nds32_parse_type_2(uint32_t opcode, uint8_t *rt, uint8_t *ra, int32_t *imm)
73 {
74 *rt = (opcode >> 20) & 0x1F;
75 *ra = (opcode >> 15) & 0x1F;
76 *imm = opcode & 0x7FFF;
77
78 return ERROR_OK;
79 }
80
81 static int nds32_parse_type_3(uint32_t opcode, uint8_t *rt, uint8_t *ra,
82 uint8_t *rb, int32_t *imm)
83 {
84 *rt = (opcode >> 20) & 0x1F;
85 *ra = (opcode >> 15) & 0x1F;
86 *rb = (opcode >> 10) & 0x1F;
87 *imm = opcode & 0x3FF;
88
89 return ERROR_OK;
90 }
91
92 static int nds32_parse_type_4(uint32_t opcode, uint8_t *rt, uint8_t *ra,
93 uint8_t *rb, uint8_t *rd, uint8_t *sub_opc)
94 {
95 *rt = (opcode >> 20) & 0x1F;
96 *ra = (opcode >> 15) & 0x1F;
97 *rb = (opcode >> 10) & 0x1F;
98 *rd = (opcode >> 5) & 0x1F;
99 *sub_opc = opcode & 0x1F;
100
101 return ERROR_OK;
102 }
103
104 /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
105 static int nds32_parse_group_0_insn(struct nds32 *nds32, uint32_t opcode,
106 uint32_t address,
107 struct nds32_instruction *instruction)
108 {
109 uint8_t opc_6;
110
111 opc_6 = instruction->info.opc_6;
112
113 switch (opc_6 & 0x7) {
114 case 0: /* LBI */
115 nds32_parse_type_2(opcode, &(instruction->info.rt),
116 &(instruction->info.ra), &(instruction->info.imm));
117 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
118 instruction->type = NDS32_INSN_LOAD_STORE;
119 nds32_get_mapped_reg(nds32, instruction->info.ra,
120 &(instruction->access_start));
121 instruction->access_start += instruction->info.imm;
122 instruction->access_end = instruction->access_start + 1;
123 snprintf(instruction->text,
124 128,
125 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
126 "\tLBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
127 address,
128 opcode, instruction->info.rt, instruction->info.ra,
129 instruction->info.imm);
130 break;
131 case 1: /* LHI */
132 nds32_parse_type_2(opcode, &(instruction->info.rt),
133 &(instruction->info.ra), &(instruction->info.imm));
134 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
135 instruction->type = NDS32_INSN_LOAD_STORE;
136 nds32_get_mapped_reg(nds32, instruction->info.ra,
137 &(instruction->access_start));
138 instruction->access_start += instruction->info.imm;
139 instruction->access_end = instruction->access_start + 2;
140 snprintf(instruction->text,
141 128,
142 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
143 "\tLHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
144 address,
145 opcode, instruction->info.rt, instruction->info.ra,
146 instruction->info.imm);
147 break;
148 case 2: /* LWI */
149 nds32_parse_type_2(opcode, &(instruction->info.rt),
150 &(instruction->info.ra), &(instruction->info.imm));
151 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
152 instruction->type = NDS32_INSN_LOAD_STORE;
153 nds32_get_mapped_reg(nds32, instruction->info.ra,
154 &(instruction->access_start));
155 instruction->access_start += instruction->info.imm;
156 instruction->access_end = instruction->access_start + 4;
157 snprintf(instruction->text,
158 128,
159 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
160 "\tLWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
161 address,
162 opcode, instruction->info.rt, instruction->info.ra,
163 instruction->info.imm);
164 break;
165 case 4: /* LBI.bi */
166 nds32_parse_type_2(opcode, &(instruction->info.rt),
167 &(instruction->info.ra), &(instruction->info.imm));
168 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
169 instruction->type = NDS32_INSN_LOAD_STORE;
170 nds32_get_mapped_reg(nds32, instruction->info.ra,
171 &(instruction->access_start));
172 instruction->access_end = instruction->access_start + 1;
173 snprintf(instruction->text,
174 128,
175 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
176 "\tLBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
177 address,
178 opcode, instruction->info.rt, instruction->info.ra,
179 instruction->info.imm);
180 break;
181 case 5: /* LHI.bi */
182 nds32_parse_type_2(opcode, &(instruction->info.rt),
183 &(instruction->info.ra), &(instruction->info.imm));
184 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
185 instruction->type = NDS32_INSN_LOAD_STORE;
186 nds32_get_mapped_reg(nds32, instruction->info.ra,
187 &(instruction->access_start));
188 instruction->access_end = instruction->access_start + 2;
189 snprintf(instruction->text,
190 128,
191 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
192 "\tLHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
193 address,
194 opcode, instruction->info.rt, instruction->info.ra,
195 instruction->info.imm);
196 break;
197 case 6: /* LWI.bi */
198 nds32_parse_type_2(opcode, &(instruction->info.rt),
199 &(instruction->info.ra), &(instruction->info.imm));
200 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
201 instruction->type = NDS32_INSN_LOAD_STORE;
202 nds32_get_mapped_reg(nds32, instruction->info.ra,
203 &(instruction->access_start));
204 instruction->access_end = instruction->access_start + 4;
205 snprintf(instruction->text,
206 128,
207 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
208 "\tLWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32 "",
209 address,
210 opcode, instruction->info.rt, instruction->info.ra,
211 instruction->info.imm);
212 break;
213 default:
214 snprintf(instruction->text,
215 128,
216 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
217 address,
218 opcode);
219 return ERROR_FAIL;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int nds32_parse_group_1_insn(struct nds32 *nds32, uint32_t opcode,
226 uint32_t address, struct nds32_instruction *instruction)
227 {
228 uint8_t opc_6;
229
230 opc_6 = instruction->info.opc_6;
231
232 switch (opc_6 & 0x7) {
233 case 0: /* SBI */
234 nds32_parse_type_2(opcode, &(instruction->info.rt),
235 &(instruction->info.ra), &(instruction->info.imm));
236 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
237 instruction->type = NDS32_INSN_LOAD_STORE;
238 nds32_get_mapped_reg(nds32, instruction->info.ra,
239 &(instruction->access_start));
240 instruction->access_start += instruction->info.imm;
241 instruction->access_end = instruction->access_start + 1;
242 snprintf(instruction->text,
243 128,
244 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
245 "\tSBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
246 address,
247 opcode, instruction->info.rt, instruction->info.ra,
248 instruction->info.imm);
249 break;
250 case 1: /* SHI */
251 nds32_parse_type_2(opcode, &(instruction->info.rt),
252 &(instruction->info.ra), &(instruction->info.imm));
253 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
254 instruction->type = NDS32_INSN_LOAD_STORE;
255 nds32_get_mapped_reg(nds32, instruction->info.ra,
256 &(instruction->access_start));
257 instruction->access_start += instruction->info.imm;
258 instruction->access_end = instruction->access_start + 2;
259 snprintf(instruction->text,
260 128,
261 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
262 "\tSHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
263 address,
264 opcode, instruction->info.rt, instruction->info.ra,
265 instruction->info.imm);
266 break;
267 case 2: /* SWI */
268 nds32_parse_type_2(opcode, &(instruction->info.rt),
269 &(instruction->info.ra), &(instruction->info.imm));
270 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
271 instruction->type = NDS32_INSN_LOAD_STORE;
272 nds32_get_mapped_reg(nds32, instruction->info.ra,
273 &(instruction->access_start));
274 instruction->access_start += instruction->info.imm;
275 instruction->access_end = instruction->access_start + 4;
276 snprintf(instruction->text,
277 128,
278 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
279 "\tSWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
280 address,
281 opcode, instruction->info.rt, instruction->info.ra,
282 instruction->info.imm);
283 break;
284 case 4: /* SBI.bi */
285 nds32_parse_type_2(opcode, &(instruction->info.rt),
286 &(instruction->info.ra), &(instruction->info.imm));
287 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
288 instruction->type = NDS32_INSN_LOAD_STORE;
289 nds32_get_mapped_reg(nds32, instruction->info.ra,
290 &(instruction->access_start));
291 instruction->access_end = instruction->access_start + 1;
292 snprintf(instruction->text,
293 128,
294 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
295 "\tSBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
296 address,
297 opcode, instruction->info.rt, instruction->info.ra,
298 instruction->info.imm);
299 break;
300 case 5: /* SHI.bi */
301 nds32_parse_type_2(opcode, &(instruction->info.rt),
302 &(instruction->info.ra), &(instruction->info.imm));
303 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
304 instruction->type = NDS32_INSN_LOAD_STORE;
305 nds32_get_mapped_reg(nds32, instruction->info.ra,
306 &(instruction->access_start));
307 instruction->access_end = instruction->access_start + 2;
308 snprintf(instruction->text,
309 128,
310 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
311 "\tSHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
312 address,
313 opcode, instruction->info.rt, instruction->info.ra,
314 instruction->info.imm);
315 break;
316 case 6: /* SWI.bi */
317 nds32_parse_type_2(opcode, &(instruction->info.rt),
318 &(instruction->info.ra), &(instruction->info.imm));
319 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
320 instruction->type = NDS32_INSN_LOAD_STORE;
321 nds32_get_mapped_reg(nds32, instruction->info.ra,
322 &(instruction->access_start));
323 instruction->access_end = instruction->access_start + 4;
324 snprintf(instruction->text,
325 128,
326 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
327 "\tSWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
328 address,
329 opcode, instruction->info.rt, instruction->info.ra,
330 instruction->info.imm);
331 break;
332 default:
333 snprintf(instruction->text,
334 128,
335 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
336 address,
337 opcode);
338 return ERROR_FAIL;
339 }
340
341 return ERROR_OK;
342 }
343
344 static int nds32_parse_group_2_insn(struct nds32 *nds32, uint32_t opcode,
345 uint32_t address, struct nds32_instruction *instruction)
346 {
347 uint8_t opc_6;
348
349 opc_6 = instruction->info.opc_6;
350
351 switch (opc_6 & 0x7) {
352 case 0: /* LBSI */
353 nds32_parse_type_2(opcode, &(instruction->info.rt),
354 &(instruction->info.ra), &(instruction->info.imm));
355 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
356 instruction->type = NDS32_INSN_LOAD_STORE;
357 nds32_get_mapped_reg(nds32, instruction->info.ra,
358 &(instruction->access_start));
359 instruction->access_start += instruction->info.imm;
360 instruction->access_end = instruction->access_start + 1;
361 snprintf(instruction->text,
362 128,
363 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
364 "\tLBSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
365 address,
366 opcode, instruction->info.rt, instruction->info.ra,
367 instruction->info.imm);
368 break;
369 case 1: /* LHSI */
370 nds32_parse_type_2(opcode, &(instruction->info.rt),
371 &(instruction->info.ra), &(instruction->info.imm));
372 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
373 instruction->type = NDS32_INSN_LOAD_STORE;
374 nds32_get_mapped_reg(nds32, instruction->info.ra,
375 &(instruction->access_start));
376 instruction->access_start += instruction->info.imm;
377 instruction->access_end = instruction->access_start + 2;
378 snprintf(instruction->text,
379 128,
380 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
381 "\tLHSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
382 address,
383 opcode, instruction->info.rt, instruction->info.ra,
384 instruction->info.imm);
385 break;
386 case 3: { /* DPREFI */
387 uint8_t sub_type;
388 nds32_parse_type_2(opcode, &sub_type, &(instruction->info.ra),
389 &(instruction->info.imm));
390 instruction->info.sub_opc = sub_type & 0xF;
391 instruction->type = NDS32_INSN_MISC;
392 if (sub_type & 0x10) { /* DPREFI.d */
393 /* sign-extend */
394 instruction->info.imm = (instruction->info.imm << 17) >> 14;
395 snprintf(instruction->text,
396 128,
397 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
398 "\tDPREFI.d\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
399 address,
400 opcode, instruction->info.sub_opc,
401 instruction->info.ra, instruction->info.imm);
402 } else { /* DPREFI.w */
403 /* sign-extend */
404 instruction->info.imm = (instruction->info.imm << 17) >> 15;
405 snprintf(instruction->text,
406 128,
407 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
408 "\tDPREFI.w\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
409 address,
410 opcode, instruction->info.sub_opc,
411 instruction->info.ra, instruction->info.imm);
412 }
413 }
414 break;
415 case 4: /* LBSI.bi */
416 nds32_parse_type_2(opcode, &(instruction->info.rt),
417 &(instruction->info.ra), &(instruction->info.imm));
418 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
419 instruction->type = NDS32_INSN_LOAD_STORE;
420 nds32_get_mapped_reg(nds32, instruction->info.ra,
421 &(instruction->access_start));
422 instruction->access_end = instruction->access_start + 1;
423 snprintf(instruction->text,
424 128,
425 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
426 "\tLBSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
427 address,
428 opcode, instruction->info.rt, instruction->info.ra,
429 instruction->info.imm);
430 break;
431 case 5: /* LHSI.bi */
432 nds32_parse_type_2(opcode, &(instruction->info.rt),
433 &(instruction->info.ra), &(instruction->info.imm));
434 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
435 instruction->type = NDS32_INSN_LOAD_STORE;
436 nds32_get_mapped_reg(nds32, instruction->info.ra,
437 &(instruction->access_start));
438 instruction->access_end = instruction->access_start + 2;
439 snprintf(instruction->text,
440 128,
441 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
442 "\tLHSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
443 address,
444 opcode, instruction->info.rt, instruction->info.ra,
445 instruction->info.imm);
446 break;
447 case 6: /* LBGP */
448 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
449 instruction->type = NDS32_INSN_LOAD_STORE;
450 if ((instruction->info.imm >> 19) & 0x1) { /* LBSI.gp */
451 instruction->info.imm = (instruction->info.imm << 13) >> 13;
452 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
453 instruction->access_start += instruction->info.imm;
454 instruction->access_end = instruction->access_start + 1;
455 snprintf(instruction->text,
456 128,
457 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
458 "\tLBSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
459 address,
460 opcode, instruction->info.rt, instruction->info.imm);
461 } else { /* LBI.gp */
462 instruction->info.imm = (instruction->info.imm << 13) >> 13;
463 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
464 instruction->access_start += instruction->info.imm;
465 instruction->access_end = instruction->access_start + 1;
466 snprintf(instruction->text,
467 128,
468 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
469 "\tLBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
470 address,
471 opcode, instruction->info.rt, instruction->info.imm);
472 }
473 break;
474 default:
475 snprintf(instruction->text,
476 128,
477 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
478 address,
479 opcode);
480 return ERROR_FAIL;
481 }
482
483 return ERROR_OK;
484 }
485
486 static int nds32_parse_mem(struct nds32 *nds32, uint32_t opcode, uint32_t address,
487 struct nds32_instruction *instruction)
488 {
489 uint32_t sub_opcode = opcode & 0x3F;
490 uint32_t val_ra, val_rb;
491 switch (sub_opcode >> 3) {
492 case 0:
493 switch (sub_opcode & 0x7) {
494 case 0: /* LB */
495 nds32_parse_type_3(opcode, &(instruction->info.rt),
496 &(instruction->info.ra), \
497 &(instruction->info.rb), &(instruction->info.imm));
498 instruction->type = NDS32_INSN_LOAD_STORE;
499 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
500 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
501 instruction->access_start = val_ra +
502 (val_rb << ((instruction->info.imm >> 8) & 0x3));
503 instruction->access_end = instruction->access_start + 1;
504 snprintf(instruction->text,
505 128,
506 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
507 "\tLB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
508 address,
509 opcode, instruction->info.rt, instruction->info.ra,
510 instruction->info.rb,
511 (instruction->info.imm >> 8) & 0x3);
512 break;
513 case 1: /* LH */
514 nds32_parse_type_3(opcode, &(instruction->info.rt),
515 &(instruction->info.ra),
516 &(instruction->info.rb), &(instruction->info.imm));
517 instruction->type = NDS32_INSN_LOAD_STORE;
518 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
519 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
520 instruction->access_start = val_ra +
521 (val_rb << ((instruction->info.imm >> 8) & 0x3));
522 instruction->access_end = instruction->access_start + 2;
523 snprintf(instruction->text,
524 128,
525 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
526 "\tLH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
527 address,
528 opcode, instruction->info.rt, instruction->info.ra,
529 instruction->info.rb,
530 (instruction->info.imm >> 8) & 0x3);
531 break;
532 case 2: /* LW */
533 nds32_parse_type_3(opcode, &(instruction->info.rt),
534 &(instruction->info.ra),
535 &(instruction->info.rb), &(instruction->info.imm));
536 instruction->type = NDS32_INSN_LOAD_STORE;
537 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
538 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
539 instruction->access_start = val_ra +
540 (val_rb << ((instruction->info.imm >> 8) & 0x3));
541 instruction->access_end = instruction->access_start + 4;
542 snprintf(instruction->text,
543 128,
544 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
545 "\tLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
546 address,
547 opcode, instruction->info.rt, instruction->info.ra,
548 instruction->info.rb,
549 (instruction->info.imm >> 8) & 0x3);
550 break;
551 case 4: /* LB.bi */
552 nds32_parse_type_3(opcode, &(instruction->info.rt),
553 &(instruction->info.ra),
554 &(instruction->info.rb), &(instruction->info.imm));
555 instruction->type = NDS32_INSN_LOAD_STORE;
556 nds32_get_mapped_reg(nds32, instruction->info.ra,
557 &(instruction->access_start));
558 instruction->access_end = instruction->access_start + 1;
559 snprintf(instruction->text,
560 128,
561 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
562 "\tLB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
563 address,
564 opcode, instruction->info.rt,
565 instruction->info.ra, instruction->info.rb,
566 (instruction->info.imm >> 8) & 0x3);
567 break;
568 case 5: /* LH.bi */
569 nds32_parse_type_3(opcode, &(instruction->info.rt),
570 &(instruction->info.ra),
571 &(instruction->info.rb), &(instruction->info.imm));
572 instruction->type = NDS32_INSN_LOAD_STORE;
573 nds32_get_mapped_reg(nds32, instruction->info.ra,
574 &(instruction->access_start));
575 instruction->access_end = instruction->access_start + 2;
576 snprintf(instruction->text,
577 128,
578 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
579 "\tLH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
580 address,
581 opcode, instruction->info.rt, instruction->info.ra,
582 instruction->info.rb,
583 (instruction->info.imm >> 8) & 0x3);
584 break;
585 case 6: /* LW.bi */
586 nds32_parse_type_3(opcode, &(instruction->info.rt),
587 &(instruction->info.ra),
588 &(instruction->info.rb), &(instruction->info.imm));
589 instruction->type = NDS32_INSN_LOAD_STORE;
590 nds32_get_mapped_reg(nds32, instruction->info.ra,
591 &(instruction->access_start));
592 instruction->access_end = instruction->access_start + 4;
593 snprintf(instruction->text,
594 128,
595 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
596 "\tLW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
597 address,
598 opcode, instruction->info.rt, instruction->info.ra,
599 instruction->info.rb,
600 (instruction->info.imm >> 8) & 0x3);
601 break;
602 }
603 break;
604 case 1:
605 switch (sub_opcode & 0x7) {
606 case 0: /* SB */
607 nds32_parse_type_3(opcode, &(instruction->info.rt),
608 &(instruction->info.ra),
609 &(instruction->info.rb), &(instruction->info.imm));
610 instruction->type = NDS32_INSN_LOAD_STORE;
611 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
612 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
613 instruction->access_start = val_ra +
614 (val_rb << ((instruction->info.imm >> 8) & 0x3));
615 instruction->access_end = instruction->access_start + 1;
616 snprintf(instruction->text,
617 128,
618 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
619 "\tSB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
620 address,
621 opcode, instruction->info.rt,
622 instruction->info.ra, instruction->info.rb,
623 (instruction->info.imm >> 8) & 0x3);
624 break;
625 case 1: /* SH */
626 nds32_parse_type_3(opcode, &(instruction->info.rt),
627 &(instruction->info.ra),
628 &(instruction->info.rb), &(instruction->info.imm));
629 instruction->type = NDS32_INSN_LOAD_STORE;
630 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
631 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
632 instruction->access_start = val_ra +
633 (val_rb << ((instruction->info.imm >> 8) & 0x3));
634 instruction->access_end = instruction->access_start + 2;
635 snprintf(instruction->text,
636 128,
637 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
638 "\tSH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
639 address,
640 opcode, instruction->info.rt, instruction->info.ra,
641 instruction->info.rb,
642 (instruction->info.imm >> 8) & 0x3);
643 break;
644 case 2: /* SW */
645 nds32_parse_type_3(opcode, &(instruction->info.rt),
646 &(instruction->info.ra),
647 &(instruction->info.rb), &(instruction->info.imm));
648 instruction->type = NDS32_INSN_LOAD_STORE;
649 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
650 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
651 instruction->access_start = val_ra +
652 (val_rb << ((instruction->info.imm >> 8) & 0x3));
653 instruction->access_end = instruction->access_start + 4;
654 snprintf(instruction->text,
655 128,
656 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
657 "\tSW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
658 address,
659 opcode, instruction->info.rt,
660 instruction->info.ra, instruction->info.rb,
661 (instruction->info.imm >> 8) & 0x3);
662 break;
663 case 4: /* SB.bi */
664 nds32_parse_type_3(opcode, &(instruction->info.rt),
665 &(instruction->info.ra),
666 &(instruction->info.rb), &(instruction->info.imm));
667 instruction->type = NDS32_INSN_LOAD_STORE;
668 nds32_get_mapped_reg(nds32, instruction->info.ra,
669 &(instruction->access_start));
670 instruction->access_end = instruction->access_start + 1;
671 snprintf(instruction->text,
672 128,
673 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
674 "\tSB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
675 address,
676 opcode, instruction->info.rt, instruction->info.ra,
677 instruction->info.rb,
678 (instruction->info.imm >> 8) & 0x3);
679 break;
680 case 5: /* SH.bi */
681 nds32_parse_type_3(opcode, &(instruction->info.rt),
682 &(instruction->info.ra),
683 &(instruction->info.rb), &(instruction->info.imm));
684 instruction->type = NDS32_INSN_LOAD_STORE;
685 nds32_get_mapped_reg(nds32, instruction->info.ra,
686 &(instruction->access_start));
687 instruction->access_end = instruction->access_start + 2;
688 snprintf(instruction->text,
689 128,
690 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
691 "\tSH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
692 address,
693 opcode, instruction->info.rt, instruction->info.ra,
694 instruction->info.rb,
695 (instruction->info.imm >> 8) & 0x3);
696 break;
697 case 6: /* SW.bi */
698 nds32_parse_type_3(opcode, &(instruction->info.rt),
699 &(instruction->info.ra),
700 &(instruction->info.rb), &(instruction->info.imm));
701 instruction->type = NDS32_INSN_LOAD_STORE;
702 nds32_get_mapped_reg(nds32, instruction->info.ra,
703 &(instruction->access_start));
704 instruction->access_end = instruction->access_start + 4;
705 snprintf(instruction->text,
706 128,
707 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
708 "\tSW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
709 address,
710 opcode, instruction->info.rt, instruction->info.ra,
711 instruction->info.rb,
712 (instruction->info.imm >> 8) & 0x3);
713 break;
714 }
715 break;
716 case 2:
717 switch (sub_opcode & 0x7) {
718 case 0: /* LBS */
719 nds32_parse_type_3(opcode, &(instruction->info.rt),
720 &(instruction->info.ra),
721 &(instruction->info.rb), &(instruction->info.imm));
722 instruction->type = NDS32_INSN_LOAD_STORE;
723 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
724 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
725 instruction->access_start = val_ra +
726 (val_rb << ((instruction->info.imm >> 8) & 0x3));
727 instruction->access_end = instruction->access_start + 1;
728 snprintf(instruction->text,
729 128,
730 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
731 "\tLBS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
732 address,
733 opcode, instruction->info.rt,
734 instruction->info.ra, instruction->info.rb,
735 (instruction->info.imm >> 8) & 0x3);
736 break;
737 case 1: /* LHS */
738 nds32_parse_type_3(opcode, &(instruction->info.rt),
739 &(instruction->info.ra),
740 &(instruction->info.rb), &(instruction->info.imm));
741 instruction->type = NDS32_INSN_LOAD_STORE;
742 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
743 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
744 instruction->access_start = val_ra +
745 (val_rb << ((instruction->info.imm >> 8) & 0x3));
746 instruction->access_end = instruction->access_start + 2;
747 snprintf(instruction->text,
748 128,
749 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
750 "\tLHS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
751 address,
752 opcode, instruction->info.rt, instruction->info.ra,
753 instruction->info.rb,
754 (instruction->info.imm >> 8) & 0x3);
755 break;
756 case 3: /* DPREF */
757 nds32_parse_type_3(opcode, &(instruction->info.sub_opc),
758 &(instruction->info.ra),
759 &(instruction->info.rb), &(instruction->info.imm));
760 instruction->type = NDS32_INSN_MISC;
761 snprintf(instruction->text,
762 128,
763 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
764 "\tDPREF\t#%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<#%" PRId32 ")]",
765 address,
766 opcode, instruction->info.sub_opc,
767 instruction->info.ra, instruction->info.rb,
768 (instruction->info.imm >> 8) & 0x3);
769 break;
770 case 4: /* LBS.bi */
771 nds32_parse_type_3(opcode, &(instruction->info.rt),
772 &(instruction->info.ra),
773 &(instruction->info.rb), &(instruction->info.imm));
774 instruction->type = NDS32_INSN_LOAD_STORE;
775 nds32_get_mapped_reg(nds32, instruction->info.ra,
776 &(instruction->access_start));
777 instruction->access_end = instruction->access_start + 1;
778 snprintf(instruction->text,
779 128,
780 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
781 "\tLBS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
782 address,
783 opcode, instruction->info.rt, instruction->info.ra,
784 instruction->info.rb,
785 (instruction->info.imm >> 8) & 0x3);
786 break;
787 case 5: /* LHS.bi */
788 nds32_parse_type_3(opcode, &(instruction->info.rt),
789 &(instruction->info.ra),
790 &(instruction->info.rb), &(instruction->info.imm));
791 instruction->type = NDS32_INSN_LOAD_STORE;
792 nds32_get_mapped_reg(nds32, instruction->info.ra,
793 &(instruction->access_start));
794 instruction->access_end = instruction->access_start + 2;
795 snprintf(instruction->text,
796 128,
797 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
798 "\tLHS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
799 address,
800 opcode, instruction->info.rt, instruction->info.ra,
801 instruction->info.rb,
802 (instruction->info.imm >> 8) & 0x3);
803 break;
804 }
805 break;
806 case 3:
807 switch (sub_opcode & 0x7) {
808 case 0: /* LLW */
809 nds32_parse_type_3(opcode, &(instruction->info.rt),
810 &(instruction->info.ra),
811 &(instruction->info.rb), &(instruction->info.imm));
812 instruction->type = NDS32_INSN_LOAD_STORE;
813 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
814 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
815 instruction->access_start = val_ra +
816 (val_rb << ((instruction->info.imm >> 8) & 0x3));
817 instruction->access_end = instruction->access_start + 4;
818 snprintf(instruction->text,
819 128,
820 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
821 "\tLLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
822 address,
823 opcode, instruction->info.rt, instruction->info.ra,
824 instruction->info.rb,
825 (instruction->info.imm >> 8) & 0x3);
826 break;
827 case 1: /* SCW */
828 nds32_parse_type_3(opcode, &(instruction->info.rt),
829 &(instruction->info.ra),
830 &(instruction->info.rb), &(instruction->info.imm));
831 instruction->type = NDS32_INSN_LOAD_STORE;
832 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
833 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
834 instruction->access_start = val_ra +
835 (val_rb << ((instruction->info.imm >> 8) & 0x3));
836 instruction->access_end = instruction->access_start + 4;
837 snprintf(instruction->text,
838 128,
839 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
840 "\tSCW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
841 address,
842 opcode, instruction->info.rt, instruction->info.ra,
843 instruction->info.rb,
844 (instruction->info.imm >> 8) & 0x3);
845 break;
846 }
847 break;
848 case 4:
849 switch (sub_opcode & 0x7) {
850 case 0: /* LBUP */
851 nds32_parse_type_3(opcode, &(instruction->info.rt),
852 &(instruction->info.ra),
853 &(instruction->info.rb), &(instruction->info.imm));
854 instruction->type = NDS32_INSN_LOAD_STORE;
855 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
856 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
857 instruction->access_start = val_ra +
858 (val_rb << ((instruction->info.imm >> 8) & 0x3));
859 instruction->access_end = instruction->access_start + 1;
860 snprintf(instruction->text,
861 128,
862 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
863 "\tLBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
864 address,
865 opcode, instruction->info.rt, instruction->info.ra,
866 instruction->info.rb,
867 (instruction->info.imm >> 8) & 0x3);
868 break;
869 case 2: /* LWUP */
870 nds32_parse_type_3(opcode, &(instruction->info.rt),
871 &(instruction->info.ra),
872 &(instruction->info.rb), &(instruction->info.imm));
873 instruction->type = NDS32_INSN_LOAD_STORE;
874 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
875 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
876 instruction->access_start = val_ra +
877 (val_rb << ((instruction->info.imm >> 8) & 0x3));
878 instruction->access_end = instruction->access_start + 4;
879 snprintf(instruction->text,
880 128,
881 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
882 "\tLWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
883 address,
884 opcode, instruction->info.rt, instruction->info.ra,
885 instruction->info.rb,
886 (instruction->info.imm >> 8) & 0x3);
887 break;
888 }
889 break;
890 case 5:
891 switch (sub_opcode & 0x7) {
892 case 0: /* SBUP */
893 nds32_parse_type_3(opcode, &(instruction->info.rt),
894 &(instruction->info.ra),
895 &(instruction->info.rb), &(instruction->info.imm));
896 instruction->type = NDS32_INSN_LOAD_STORE;
897 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
898 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
899 instruction->access_start = val_ra +
900 (val_rb << ((instruction->info.imm >> 8) & 0x3));
901 instruction->access_end = instruction->access_start + 1;
902 snprintf(instruction->text,
903 128,
904 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
905 "\tSBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
906 address,
907 opcode, instruction->info.rt, instruction->info.ra,
908 instruction->info.rb,
909 (instruction->info.imm >> 8) & 0x3);
910 break;
911 case 2: /* SWUP */
912 nds32_parse_type_3(opcode, &(instruction->info.rt),
913 &(instruction->info.ra),
914 &(instruction->info.rb), &(instruction->info.imm));
915 instruction->type = NDS32_INSN_LOAD_STORE;
916 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
917 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
918 instruction->access_start = val_ra +
919 (val_rb << ((instruction->info.imm >> 8) & 0x3));
920 instruction->access_end = instruction->access_start + 4;
921 snprintf(instruction->text,
922 128,
923 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
924 "\tSWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
925 address,
926 opcode, instruction->info.rt, instruction->info.ra,
927 instruction->info.rb,
928 (instruction->info.imm >> 8) & 0x3);
929 break;
930 }
931 break;
932 default:
933 snprintf(instruction->text,
934 128,
935 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
936 address,
937 opcode);
938 return ERROR_FAIL;
939 }
940
941 return ERROR_OK;
942 }
943
944 static int nds32_calculate_lsmw_access_range(struct nds32 *nds32,
945 struct nds32_instruction *instruction)
946 {
947 uint8_t ba;
948 uint8_t id;
949 uint8_t enable4;
950
951 enable4 = (instruction->info.imm >> 6) & 0xF;
952 ba = (instruction->info.imm >> 4) & 0x1;
953 id = (instruction->info.imm >> 3) & 0x1;
954
955 if (ba) {
956 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
957 if (id) { /* decrease */
958 /* access_end is the (last_element+1), so no need to minus 4 */
959 /* instruction->access_end -= 4; */
960 instruction->access_end = instruction->access_start;
961 } else { /* increase */
962 instruction->access_start += 4;
963 }
964 } else {
965 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
966 instruction->access_end = instruction->access_start - 4;
967 }
968
969 if (id) { /* decrease */
970 instruction->access_start = instruction->access_end -
971 4 * (instruction->info.rd - instruction->info.rb + 1);
972 instruction->access_start -= (4 * enable4_bits[enable4]);
973 } else { /* increase */
974 instruction->access_end = instruction->access_start +
975 4 * (instruction->info.rd - instruction->info.rb + 1);
976 instruction->access_end += (4 * enable4_bits[enable4]);
977 }
978
979 return ERROR_OK;
980 }
981
982 static int nds32_parse_lsmw(struct nds32 *nds32, uint32_t opcode, uint32_t address,
983 struct nds32_instruction *instruction)
984 {
985 if (opcode & 0x20) { /* SMW, SMWA, SMWZB */
986 switch (opcode & 0x3) {
987 /* TODO */
988 case 0: /* SMW */
989 /* use rd as re */
990 nds32_parse_type_3(opcode, &(instruction->info.rb),
991 &(instruction->info.ra),
992 &(instruction->info.rd), &(instruction->info.imm));
993 instruction->type = NDS32_INSN_LOAD_STORE;
994 nds32_calculate_lsmw_access_range(nds32, instruction);
995 snprintf(instruction->text,
996 128,
997 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
998 "\tSMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
999 address,
1000 opcode, instruction->info.rb, instruction->info.ra,
1001 instruction->info.rd,
1002 (instruction->info.imm >> 6) & 0xF);
1003 break;
1004 case 1: /* SMWA */
1005 nds32_parse_type_3(opcode, &(instruction->info.rb),
1006 &(instruction->info.ra),
1007 &(instruction->info.rd), &(instruction->info.imm));
1008 instruction->type = NDS32_INSN_LOAD_STORE;
1009 nds32_calculate_lsmw_access_range(nds32, instruction);
1010 snprintf(instruction->text,
1011 128,
1012 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1013 "\tSMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1014 address,
1015 opcode, instruction->info.rb, instruction->info.ra,
1016 instruction->info.rd,
1017 (instruction->info.imm >> 6) & 0xF);
1018 break;
1019 case 2: /* SMWZB */
1020 nds32_parse_type_3(opcode, &(instruction->info.rb),
1021 &(instruction->info.ra),
1022 &(instruction->info.rd), &(instruction->info.imm));
1023 instruction->type = NDS32_INSN_LOAD_STORE;
1024 /* TODO: calculate access_start/access_end */
1025 snprintf(instruction->text,
1026 128,
1027 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1028 "\tSMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1029 address,
1030 opcode, instruction->info.rb, instruction->info.ra,
1031 instruction->info.rd,
1032 (instruction->info.imm >> 6) & 0xF);
1033 break;
1034 default:
1035 snprintf(instruction->text,
1036 128,
1037 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1038 address,
1039 opcode);
1040 return ERROR_FAIL;
1041 }
1042 } else { /* LMW, LMWA, LMWZB */
1043 switch (opcode & 0x3) {
1044 case 0: /* LMW */
1045 nds32_parse_type_3(opcode, &(instruction->info.rb),
1046 &(instruction->info.ra),
1047 &(instruction->info.rd), &(instruction->info.imm));
1048 instruction->type = NDS32_INSN_LOAD_STORE;
1049 nds32_calculate_lsmw_access_range(nds32, instruction);
1050 snprintf(instruction->text,
1051 128,
1052 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1053 "\tLMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1054 address,
1055 opcode, instruction->info.rb, instruction->info.ra,
1056 instruction->info.rd,
1057 (instruction->info.imm >> 6) & 0xF);
1058 break;
1059 case 1: /* LMWA */
1060 nds32_parse_type_3(opcode, &(instruction->info.rb),
1061 &(instruction->info.ra),
1062 &(instruction->info.rd), &(instruction->info.imm));
1063 instruction->type = NDS32_INSN_LOAD_STORE;
1064 nds32_calculate_lsmw_access_range(nds32, instruction);
1065 snprintf(instruction->text,
1066 128,
1067 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1068 "\tLMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1069 address,
1070 opcode, instruction->info.rb, instruction->info.ra,
1071 instruction->info.rd,
1072 (instruction->info.imm >> 6) & 0xF);
1073 break;
1074 case 2: /* LMWZB */
1075 nds32_parse_type_3(opcode, &(instruction->info.rb),
1076 &(instruction->info.ra),
1077 &(instruction->info.rd), &(instruction->info.imm));
1078 instruction->type = NDS32_INSN_LOAD_STORE;
1079 /* TODO: calculate access_start/access_end */
1080 snprintf(instruction->text,
1081 128,
1082 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1083 "\tLMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1084 address,
1085 opcode, instruction->info.rb, instruction->info.ra,
1086 instruction->info.rd,
1087 (instruction->info.imm >> 6) & 0xF);
1088 break;
1089 default:
1090 snprintf(instruction->text,
1091 128,
1092 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1093 address,
1094 opcode);
1095 return ERROR_FAIL;
1096 }
1097 }
1098
1099 return ERROR_OK;
1100 }
1101
1102 static int nds32_parse_hwgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1103 struct nds32_instruction *instruction)
1104 {
1105 switch ((opcode >> 18) & 0x3) {
1106 case 0: /* LHI.gp */
1107 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1108 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1109 instruction->type = NDS32_INSN_LOAD_STORE;
1110 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1111 instruction->access_start += instruction->info.imm;
1112 instruction->access_end = instruction->access_start + 2;
1113 snprintf(instruction->text,
1114 128,
1115 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1116 "\tLHI.gp\t$r%" PRIu8 ",[#%" PRId32"]",
1117 address,
1118 opcode, instruction->info.rt, instruction->info.imm);
1119 break;
1120 case 1: /* LHSI.gp */
1121 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1122 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1123 instruction->type = NDS32_INSN_LOAD_STORE;
1124 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1125 instruction->access_start += instruction->info.imm;
1126 instruction->access_end = instruction->access_start + 2;
1127 snprintf(instruction->text,
1128 128,
1129 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1130 "\tLHSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1131 address,
1132 opcode, instruction->info.rt, instruction->info.imm);
1133 break;
1134 case 2: /* SHI.gp */
1135 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1136 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1137 instruction->type = NDS32_INSN_LOAD_STORE;
1138 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1139 instruction->access_start += instruction->info.imm;
1140 instruction->access_end = instruction->access_start + 2;
1141 snprintf(instruction->text,
1142 128,
1143 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1144 "\tSHI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1145 address,
1146 opcode, instruction->info.rt, instruction->info.imm);
1147 break;
1148 case 3:
1149 instruction->type = NDS32_INSN_LOAD_STORE;
1150 if ((opcode >> 17) & 0x1) { /* SWI.gp */
1151 nds32_parse_type_1(opcode, &(instruction->info.rt),
1152 &(instruction->info.imm));
1153 /* sign-extend */
1154 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1155 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1156 instruction->access_start += instruction->info.imm;
1157 instruction->access_end = instruction->access_start + 4;
1158 snprintf(instruction->text,
1159 128,
1160 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1161 "\tSWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1162 address,
1163 opcode, instruction->info.rt, instruction->info.imm);
1164 } else { /* LWI.gp */
1165 nds32_parse_type_1(opcode, &(instruction->info.rt),
1166 &(instruction->info.imm));
1167 /* sign-extend */
1168 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1169 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1170 instruction->access_start += instruction->info.imm;
1171 instruction->access_end = instruction->access_start + 4;
1172 snprintf(instruction->text,
1173 128,
1174 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1175 "\tLWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1176 address,
1177 opcode, instruction->info.rt, instruction->info.imm);
1178 }
1179
1180 break;
1181 default:
1182 snprintf(instruction->text,
1183 128,
1184 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1185 address,
1186 opcode);
1187 return ERROR_FAIL;
1188 }
1189
1190 return ERROR_OK;
1191 }
1192
1193 static int nds32_parse_sbgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1194 struct nds32_instruction *instruction)
1195 {
1196 switch ((opcode >> 19) & 0x1) {
1197 case 0: /* SBI.gp */
1198 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1199 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1200 instruction->type = NDS32_INSN_LOAD_STORE;
1201 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1202 instruction->access_start += instruction->info.imm;
1203 instruction->access_end = instruction->access_start + 1;
1204 snprintf(instruction->text,
1205 128,
1206 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1207 "\tSBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1208 address,
1209 opcode, instruction->info.rt, instruction->info.imm);
1210 break;
1211 case 1: /* ADDI.gp */
1212 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1213 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1214 instruction->type = NDS32_INSN_DATA_PROC;
1215 snprintf(instruction->text,
1216 128,
1217 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1218 "\tADDI.gp\t$r%" PRIu8 ",#%" PRId32 "",
1219 address,
1220 opcode, instruction->info.rt, instruction->info.imm);
1221 break;
1222 default:
1223 snprintf(instruction->text,
1224 128,
1225 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1226 address,
1227 opcode);
1228 return ERROR_FAIL;
1229 }
1230
1231 return ERROR_OK;
1232 }
1233
1234 static int nds32_parse_group_3_insn(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1235 struct nds32_instruction *instruction)
1236 {
1237 uint8_t opc_6;
1238
1239 opc_6 = instruction->info.opc_6;
1240
1241 switch (opc_6 & 0x7) {
1242 case 4: /* MEM */
1243 nds32_parse_mem(nds32, opcode, address, instruction);
1244 break;
1245 case 5: /* LSMW */
1246 nds32_parse_lsmw(nds32, opcode, address, instruction);
1247 break;
1248 case 6: /* HWGP */
1249 nds32_parse_hwgp(nds32, opcode, address, instruction);
1250 break;
1251 case 7: /* SBGP */
1252 nds32_parse_sbgp(nds32, opcode, address, instruction);
1253 break;
1254 default:
1255 snprintf(instruction->text,
1256 128,
1257 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1258 address,
1259 opcode);
1260 return ERROR_FAIL;
1261 }
1262
1263 return ERROR_OK;
1264 }
1265
1266 static int nds32_parse_alu_1(uint32_t opcode, uint32_t address,
1267 struct nds32_instruction *instruction)
1268 {
1269 switch (opcode & 0x1F) {
1270 case 0: /* ADD */
1271 nds32_parse_type_3(opcode, &(instruction->info.rt), &(instruction->info.ra),
1272 &(instruction->info.rb), &(instruction->info.imm));
1273 instruction->type = NDS32_INSN_DATA_PROC;
1274 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1275 if (instruction->info.imm)
1276 snprintf(instruction->text,
1277 128,
1278 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1279 "\tADD_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1280 address,
1281 opcode, instruction->info.rt, instruction->info.ra,
1282 instruction->info.rb,
1283 instruction->info.imm);
1284 else
1285 snprintf(instruction->text,
1286 128,
1287 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1288 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1289 address,
1290 opcode, instruction->info.rt, instruction->info.ra,
1291 instruction->info.rb);
1292 break;
1293 case 1: /* SUB */
1294 nds32_parse_type_3(opcode, &(instruction->info.rt),
1295 &(instruction->info.ra),
1296 &(instruction->info.rb), &(instruction->info.imm));
1297 instruction->type = NDS32_INSN_DATA_PROC;
1298 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1299 if (instruction->info.imm)
1300 snprintf(instruction->text,
1301 128,
1302 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1303 "\tSUB_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1304 address,
1305 opcode, instruction->info.rt, instruction->info.ra,
1306 instruction->info.rb,
1307 instruction->info.imm);
1308 else
1309 snprintf(instruction->text,
1310 128,
1311 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1312 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1313 address,
1314 opcode, instruction->info.rt, instruction->info.ra,
1315 instruction->info.rb);
1316 break;
1317 case 2: /* AND */
1318 nds32_parse_type_3(opcode, &(instruction->info.rt),
1319 &(instruction->info.ra),
1320 &(instruction->info.rb), &(instruction->info.imm));
1321 instruction->type = NDS32_INSN_DATA_PROC;
1322 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1323 if (instruction->info.imm)
1324 snprintf(instruction->text,
1325 128,
1326 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1327 "\tAND_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1328 address,
1329 opcode, instruction->info.rt, instruction->info.ra,
1330 instruction->info.rb,
1331 instruction->info.imm);
1332 else
1333 snprintf(instruction->text,
1334 128,
1335 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1336 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1337 address,
1338 opcode, instruction->info.rt, instruction->info.ra,
1339 instruction->info.rb);
1340 break;
1341 case 3: /* XOR */
1342 nds32_parse_type_3(opcode, &(instruction->info.rt),
1343 &(instruction->info.ra),
1344 &(instruction->info.rb), &(instruction->info.imm));
1345 instruction->type = NDS32_INSN_DATA_PROC;
1346 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1347 if (instruction->info.imm)
1348 snprintf(instruction->text,
1349 128,
1350 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1351 "\tXOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1352 address,
1353 opcode, instruction->info.rt, instruction->info.ra,
1354 instruction->info.rb,
1355 instruction->info.imm);
1356 else
1357 snprintf(instruction->text,
1358 128,
1359 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1360 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1361 address,
1362 opcode, instruction->info.rt, instruction->info.ra,
1363 instruction->info.rb);
1364 break;
1365 case 4: /* OR */
1366 nds32_parse_type_3(opcode, &(instruction->info.rt),
1367 &(instruction->info.ra),
1368 &(instruction->info.rb), &(instruction->info.imm));
1369 instruction->type = NDS32_INSN_DATA_PROC;
1370 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1371 if (instruction->info.imm)
1372 snprintf(instruction->text,
1373 128,
1374 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1375 "\tOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1376 address,
1377 opcode, instruction->info.rt, instruction->info.ra,
1378 instruction->info.rb,
1379 instruction->info.imm);
1380 else
1381 snprintf(instruction->text,
1382 128,
1383 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1384 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1385 address,
1386 opcode, instruction->info.rt, instruction->info.ra,
1387 instruction->info.rb);
1388 break;
1389 case 5: /* NOR */
1390 nds32_parse_type_3(opcode, &(instruction->info.rt),
1391 &(instruction->info.ra),
1392 &(instruction->info.rb), &(instruction->info.imm));
1393 instruction->type = NDS32_INSN_DATA_PROC;
1394 snprintf(instruction->text,
1395 128,
1396 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1397 "\tNOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1398 address,
1399 opcode, instruction->info.rt, instruction->info.ra,
1400 instruction->info.rb);
1401 break;
1402 case 6: /* SLT */
1403 nds32_parse_type_3(opcode, &(instruction->info.rt),
1404 &(instruction->info.ra),
1405 &(instruction->info.rb), &(instruction->info.imm));
1406 instruction->type = NDS32_INSN_DATA_PROC;
1407 snprintf(instruction->text,
1408 128,
1409 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1410 "\tSLT\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1411 address,
1412 opcode, instruction->info.rt, instruction->info.ra,
1413 instruction->info.rb);
1414 break;
1415 case 7: /* SLTS */
1416 nds32_parse_type_3(opcode, &(instruction->info.rt),
1417 &(instruction->info.ra),
1418 &(instruction->info.rb), &(instruction->info.imm));
1419 instruction->type = NDS32_INSN_DATA_PROC;
1420 snprintf(instruction->text,
1421 128,
1422 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1423 "\tSLTS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1424 address,
1425 opcode, instruction->info.rt, instruction->info.ra,
1426 instruction->info.rb);
1427 break;
1428 case 8: { /* SLLI */
1429 uint8_t imm;
1430 int32_t sub_op;
1431 nds32_parse_type_3(opcode, &(instruction->info.rt),
1432 &(instruction->info.ra),
1433 &imm, &sub_op);
1434 instruction->info.imm = imm;
1435 instruction->type = NDS32_INSN_DATA_PROC;
1436 snprintf(instruction->text,
1437 128,
1438 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1439 "\tSLLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1440 address,
1441 opcode, instruction->info.rt, instruction->info.ra,
1442 instruction->info.imm);
1443 }
1444 break;
1445 case 9: { /* SRLI */
1446 uint8_t imm;
1447 int32_t sub_op;
1448 nds32_parse_type_3(opcode, &(instruction->info.rt),
1449 &(instruction->info.ra),
1450 &imm, &sub_op);
1451 instruction->info.imm = imm;
1452 instruction->type = NDS32_INSN_DATA_PROC;
1453 snprintf(instruction->text,
1454 128,
1455 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1456 "\tSRLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1457 address,
1458 opcode, instruction->info.rt, instruction->info.ra,
1459 instruction->info.imm);
1460 }
1461 break;
1462 case 10: { /* SRAI */
1463 uint8_t imm;
1464 int32_t sub_op;
1465 nds32_parse_type_3(opcode, &(instruction->info.rt),
1466 &(instruction->info.ra),
1467 &imm, &sub_op);
1468 instruction->info.imm = imm;
1469 instruction->type = NDS32_INSN_DATA_PROC;
1470 snprintf(instruction->text,
1471 128,
1472 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1473 "\tSRAI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1474 address,
1475 opcode, instruction->info.rt, instruction->info.ra,
1476 instruction->info.imm);
1477 }
1478 break;
1479 case 11: { /* ROTRI */
1480 uint8_t imm;
1481 int32_t sub_op;
1482 nds32_parse_type_3(opcode, &(instruction->info.rt),
1483 &(instruction->info.ra),
1484 &imm, &sub_op);
1485 instruction->info.imm = imm;
1486 instruction->type = NDS32_INSN_DATA_PROC;
1487 snprintf(instruction->text,
1488 128,
1489 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1490 "\tROTRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1491 address,
1492 opcode, instruction->info.rt, instruction->info.ra,
1493 instruction->info.imm);
1494 }
1495 break;
1496 case 12: { /* SLL */
1497 nds32_parse_type_3(opcode, &(instruction->info.rt),
1498 &(instruction->info.ra),
1499 &(instruction->info.rb), &(instruction->info.imm));
1500 instruction->type = NDS32_INSN_DATA_PROC;
1501 snprintf(instruction->text,
1502 128,
1503 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1504 "\tSLL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1505 address,
1506 opcode, instruction->info.rt, instruction->info.ra,
1507 instruction->info.rb);
1508 }
1509 break;
1510 case 13: { /* SRL */
1511 nds32_parse_type_3(opcode, &(instruction->info.rt),
1512 &(instruction->info.ra),
1513 &(instruction->info.rb), &(instruction->info.imm));
1514 instruction->type = NDS32_INSN_DATA_PROC;
1515 snprintf(instruction->text,
1516 128,
1517 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1518 "\tSRL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1519 address,
1520 opcode, instruction->info.rt, instruction->info.ra,
1521 instruction->info.rb);
1522 }
1523 break;
1524 case 14: { /* SRA */
1525 nds32_parse_type_3(opcode, &(instruction->info.rt),
1526 &(instruction->info.ra),
1527 &(instruction->info.rb), &(instruction->info.imm));
1528 instruction->type = NDS32_INSN_DATA_PROC;
1529 snprintf(instruction->text,
1530 128,
1531 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1532 "\tSRA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1533 address,
1534 opcode, instruction->info.rt, instruction->info.ra,
1535 instruction->info.rb);
1536 }
1537 break;
1538 case 15: { /* ROTR */
1539 nds32_parse_type_3(opcode, &(instruction->info.rt),
1540 &(instruction->info.ra),
1541 &(instruction->info.rb), &(instruction->info.imm));
1542 instruction->type = NDS32_INSN_DATA_PROC;
1543 snprintf(instruction->text,
1544 128,
1545 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1546 "\tROTR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1547 address,
1548 opcode, instruction->info.rt, instruction->info.ra,
1549 instruction->info.rb);
1550 }
1551 break;
1552 case 16: { /* SEB */
1553 nds32_parse_type_2(opcode, &(instruction->info.rt),
1554 &(instruction->info.ra),
1555 &(instruction->info.imm));
1556 instruction->type = NDS32_INSN_DATA_PROC;
1557 snprintf(instruction->text,
1558 128,
1559 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1560 "\tSEB\t$r%" PRIu8 ",$r%" PRIu8,
1561 address,
1562 opcode, instruction->info.rt, instruction->info.ra);
1563 }
1564 break;
1565 case 17: { /* SEH */
1566 nds32_parse_type_2(opcode, &(instruction->info.rt),
1567 &(instruction->info.ra),
1568 &(instruction->info.imm));
1569 instruction->type = NDS32_INSN_DATA_PROC;
1570 snprintf(instruction->text,
1571 128,
1572 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1573 "\tSEH\t$r%" PRIu8 ",$r%" PRIu8,
1574 address,
1575 opcode, instruction->info.rt, instruction->info.ra);
1576 }
1577 break;
1578 case 18: /* BITC */
1579 nds32_parse_type_3(opcode, &(instruction->info.rt),
1580 &(instruction->info.ra),
1581 &(instruction->info.rb), &(instruction->info.imm));
1582 instruction->type = NDS32_INSN_DATA_PROC;
1583 snprintf(instruction->text,
1584 128,
1585 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1586 "\tBITC\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1587 address,
1588 opcode, instruction->info.rt, instruction->info.ra,
1589 instruction->info.rb);
1590 break;
1591 case 19: { /* ZEH */
1592 nds32_parse_type_2(opcode, &(instruction->info.rt),
1593 &(instruction->info.ra),
1594 &(instruction->info.imm));
1595 instruction->type = NDS32_INSN_DATA_PROC;
1596 snprintf(instruction->text,
1597 128,
1598 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1599 "\tZEH\t$r%" PRIu8 ",$r%" PRIu8,
1600 address,
1601 opcode, instruction->info.rt, instruction->info.ra);
1602 }
1603 break;
1604 case 20: { /* WSBH */
1605 nds32_parse_type_2(opcode, &(instruction->info.rt),
1606 &(instruction->info.ra),
1607 &(instruction->info.imm));
1608 instruction->type = NDS32_INSN_DATA_PROC;
1609 snprintf(instruction->text,
1610 128,
1611 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1612 "\tWSBH\t$r%" PRIu8 ",$r%" PRIu8,
1613 address,
1614 opcode, instruction->info.rt, instruction->info.ra);
1615 }
1616 break;
1617 case 21: /* OR_SRLI */
1618 nds32_parse_type_3(opcode, &(instruction->info.rt),
1619 &(instruction->info.ra),
1620 &(instruction->info.rb), &(instruction->info.imm));
1621 instruction->type = NDS32_INSN_DATA_PROC;
1622 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1623 if (instruction->info.imm)
1624 snprintf(instruction->text,
1625 128,
1626 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1627 "\tOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1628 address,
1629 opcode, instruction->info.rt, instruction->info.ra,
1630 instruction->info.rb,
1631 instruction->info.imm);
1632 else
1633 snprintf(instruction->text,
1634 128,
1635 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1636 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1637 address,
1638 opcode, instruction->info.rt, instruction->info.ra,
1639 instruction->info.rb);
1640 break;
1641 case 22: { /* DIVSR */
1642 nds32_parse_type_4(opcode, &(instruction->info.rt),
1643 &(instruction->info.ra),
1644 &(instruction->info.rb), &(instruction->info.rd),
1645 &(instruction->info.sub_opc));
1646 instruction->type = NDS32_INSN_DATA_PROC;
1647 snprintf(instruction->text,
1648 128,
1649 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1650 "\tDIVSR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1651 address,
1652 opcode, instruction->info.rt, instruction->info.ra,
1653 instruction->info.rb,
1654 instruction->info.rd);
1655 }
1656 break;
1657 case 23: { /* DIVR */
1658 nds32_parse_type_4(opcode, &(instruction->info.rt),
1659 &(instruction->info.ra),
1660 &(instruction->info.rb), &(instruction->info.rd),
1661 &(instruction->info.sub_opc));
1662 instruction->type = NDS32_INSN_DATA_PROC;
1663 snprintf(instruction->text,
1664 128,
1665 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1666 "\tDIVR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1667 address,
1668 opcode, instruction->info.rt, instruction->info.ra,
1669 instruction->info.rb,
1670 instruction->info.rd);
1671 }
1672 break;
1673 case 24: { /* SVA */
1674 nds32_parse_type_3(opcode, &(instruction->info.rt),
1675 &(instruction->info.ra),
1676 &(instruction->info.rb), &(instruction->info.imm));
1677 instruction->type = NDS32_INSN_DATA_PROC;
1678 snprintf(instruction->text,
1679 128,
1680 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1681 "\tSVA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1682 address,
1683 opcode, instruction->info.rt, instruction->info.ra,
1684 instruction->info.rb);
1685 }
1686 break;
1687 case 25: { /* SVS */
1688 nds32_parse_type_3(opcode, &(instruction->info.rt),
1689 &(instruction->info.ra),
1690 &(instruction->info.rb), &(instruction->info.imm));
1691 instruction->type = NDS32_INSN_DATA_PROC;
1692 snprintf(instruction->text,
1693 128,
1694 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1695 "\tSVS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1696 address,
1697 opcode, instruction->info.rt, instruction->info.ra,
1698 instruction->info.rb);
1699 }
1700 break;
1701 case 26: { /* CMOVZ */
1702 nds32_parse_type_3(opcode, &(instruction->info.rt),
1703 &(instruction->info.ra),
1704 &(instruction->info.rb), &(instruction->info.imm));
1705 instruction->type = NDS32_INSN_MISC;
1706 snprintf(instruction->text,
1707 128,
1708 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1709 "\tCMOVZ\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1710 address,
1711 opcode, instruction->info.rt, instruction->info.ra,
1712 instruction->info.rb);
1713 }
1714 break;
1715 case 27: { /* CMOVN */
1716 nds32_parse_type_3(opcode, &(instruction->info.rt),
1717 &(instruction->info.ra),
1718 &(instruction->info.rb), &(instruction->info.imm));
1719 instruction->type = NDS32_INSN_MISC;
1720 snprintf(instruction->text,
1721 128,
1722 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1723 "\tCMOVN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1724 address,
1725 opcode, instruction->info.rt, instruction->info.ra,
1726 instruction->info.rb);
1727 }
1728 break;
1729 case 28: /* ADD_SRLI */
1730 nds32_parse_type_3(opcode, &(instruction->info.rt),
1731 &(instruction->info.ra),
1732 &(instruction->info.rb), &(instruction->info.imm));
1733 instruction->type = NDS32_INSN_DATA_PROC;
1734 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1735 if (instruction->info.imm)
1736 snprintf(instruction->text,
1737 128,
1738 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1739 "\tADD_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1740 address,
1741 opcode, instruction->info.rt, instruction->info.ra,
1742 instruction->info.rb,
1743 instruction->info.imm);
1744 else
1745 snprintf(instruction->text,
1746 128,
1747 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1748 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1749 address,
1750 opcode, instruction->info.rt, instruction->info.ra,
1751 instruction->info.rb);
1752 break;
1753 case 29: /* SUB_SRLI */
1754 nds32_parse_type_3(opcode, &(instruction->info.rt),
1755 &(instruction->info.ra),
1756 &(instruction->info.rb), &(instruction->info.imm));
1757 instruction->type = NDS32_INSN_DATA_PROC;
1758 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1759 if (instruction->info.imm)
1760 snprintf(instruction->text,
1761 128,
1762 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1763 "\tSUB_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1764 address,
1765 opcode, instruction->info.rt, instruction->info.ra,
1766 instruction->info.rb,
1767 instruction->info.imm);
1768 else
1769 snprintf(instruction->text,
1770 128,
1771 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1772 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1773 address,
1774 opcode, instruction->info.rt, instruction->info.ra,
1775 instruction->info.rb);
1776 break;
1777 case 30: /* AND_SRLI */
1778 nds32_parse_type_3(opcode, &(instruction->info.rt),
1779 &(instruction->info.ra),
1780 &(instruction->info.rb), &(instruction->info.imm));
1781 instruction->type = NDS32_INSN_DATA_PROC;
1782 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1783 if (instruction->info.imm)
1784 snprintf(instruction->text,
1785 128,
1786 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1787 "\tAND_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1788 address,
1789 opcode, instruction->info.rt, instruction->info.ra,
1790 instruction->info.rb,
1791 instruction->info.imm);
1792 else
1793 snprintf(instruction->text,
1794 128,
1795 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1796 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1797 address,
1798 opcode, instruction->info.rt, instruction->info.ra,
1799 instruction->info.rb);
1800 break;
1801 case 31: /* XOR_SRLI */
1802 nds32_parse_type_3(opcode, &(instruction->info.rt),
1803 &(instruction->info.ra),
1804 &(instruction->info.rb), &(instruction->info.imm));
1805 instruction->type = NDS32_INSN_DATA_PROC;
1806 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1807 if (instruction->info.imm)
1808 snprintf(instruction->text,
1809 128,
1810 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1811 "\tXOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1812 address,
1813 opcode, instruction->info.rt, instruction->info.ra,
1814 instruction->info.rb,
1815 instruction->info.imm);
1816 else
1817 snprintf(instruction->text,
1818 128,
1819 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1820 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1821 address,
1822 opcode, instruction->info.rt, instruction->info.ra,
1823 instruction->info.rb);
1824 break;
1825 default:
1826 snprintf(instruction->text,
1827 128,
1828 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1829 address,
1830 opcode);
1831 return ERROR_FAIL;
1832 }
1833
1834 return ERROR_OK;
1835 }
1836
1837 static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
1838 struct nds32_instruction *instruction)
1839 {
1840 switch (opcode & 0x3F) {
1841 case 0: /* MAX */
1842 nds32_parse_type_3(opcode, &(instruction->info.rt),
1843 &(instruction->info.ra),
1844 &(instruction->info.rb), &(instruction->info.imm));
1845 instruction->type = NDS32_INSN_DATA_PROC;
1846 snprintf(instruction->text,
1847 128,
1848 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1849 "\tMAX\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1850 address,
1851 opcode, instruction->info.rt, instruction->info.ra,
1852 instruction->info.rb);
1853 break;
1854 case 1: /* MIN */
1855 nds32_parse_type_3(opcode, &(instruction->info.rt),
1856 &(instruction->info.ra),
1857 &(instruction->info.rb), &(instruction->info.imm));
1858 instruction->type = NDS32_INSN_DATA_PROC;
1859 snprintf(instruction->text,
1860 128,
1861 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1862 "\tMIN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1863 address,
1864 opcode, instruction->info.rt, instruction->info.ra,
1865 instruction->info.rb);
1866 break;
1867 case 2: /* AVE */
1868 nds32_parse_type_3(opcode, &(instruction->info.rt),
1869 &(instruction->info.ra),
1870 &(instruction->info.rb), &(instruction->info.imm));
1871 instruction->type = NDS32_INSN_DATA_PROC;
1872 snprintf(instruction->text,
1873 128,
1874 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1875 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1876 address,
1877 opcode, instruction->info.rt, instruction->info.ra,
1878 instruction->info.rb);
1879 break;
1880 case 3: /* ABS */
1881 nds32_parse_type_2(opcode, &(instruction->info.rt),
1882 &(instruction->info.ra),
1883 &(instruction->info.imm));
1884 instruction->type = NDS32_INSN_DATA_PROC;
1885 snprintf(instruction->text,
1886 128,
1887 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1888 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8,
1889 address,
1890 opcode, instruction->info.rt, instruction->info.ra);
1891 break;
1892 case 4: { /* CLIPS */
1893 uint8_t imm;
1894 nds32_parse_type_3(opcode, &(instruction->info.rt),
1895 &(instruction->info.ra),
1896 &imm, &(instruction->info.imm));
1897 instruction->info.imm = imm;
1898 instruction->type = NDS32_INSN_DATA_PROC;
1899 snprintf(instruction->text,
1900 128,
1901 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1902 "\tCLIPS\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1903 address,
1904 opcode, instruction->info.rt, instruction->info.ra,
1905 instruction->info.imm);
1906 }
1907 break;
1908 case 5: { /* CLIP */
1909 uint8_t imm;
1910 nds32_parse_type_3(opcode, &(instruction->info.rt),
1911 &(instruction->info.ra),
1912 &imm, &(instruction->info.imm));
1913 instruction->info.imm = imm;
1914 instruction->type = NDS32_INSN_DATA_PROC;
1915 snprintf(instruction->text,
1916 128,
1917 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1918 "\tCLIP\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1919 address,
1920 opcode, instruction->info.rt, instruction->info.ra,
1921 instruction->info.imm);
1922 }
1923 break;
1924 case 6: /* CLO */
1925 nds32_parse_type_2(opcode, &(instruction->info.rt),
1926 &(instruction->info.ra),
1927 &(instruction->info.imm));
1928 instruction->type = NDS32_INSN_DATA_PROC;
1929 snprintf(instruction->text,
1930 128,
1931 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1932 "\tCLO\t$r%" PRIu8 ",$r%" PRIu8,
1933 address,
1934 opcode, instruction->info.rt, instruction->info.ra);
1935 break;
1936 case 7: /* CLZ */
1937 nds32_parse_type_2(opcode, &(instruction->info.rt),
1938 &(instruction->info.ra),
1939 &(instruction->info.imm));
1940 instruction->type = NDS32_INSN_DATA_PROC;
1941 snprintf(instruction->text,
1942 128,
1943 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1944 "\tCLZ\t$r%" PRIu8 ",$r%" PRIu8,
1945 address,
1946 opcode, instruction->info.rt, instruction->info.ra);
1947 break;
1948 case 8: { /* BSET */
1949 uint8_t imm;
1950 nds32_parse_type_3(opcode, &(instruction->info.rt),
1951 &(instruction->info.ra),
1952 &imm, &(instruction->info.imm));
1953 instruction->info.imm = imm;
1954 instruction->type = NDS32_INSN_DATA_PROC;
1955 snprintf(instruction->text,
1956 128,
1957 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1958 "\tBSET\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1959 address,
1960 opcode, instruction->info.rt, instruction->info.ra,
1961 instruction->info.imm);
1962 }
1963 break;
1964 case 9: { /* BCLR */
1965 uint8_t imm;
1966 nds32_parse_type_3(opcode, &(instruction->info.rt),
1967 &(instruction->info.ra),
1968 &imm, &(instruction->info.imm));
1969 instruction->info.imm = imm;
1970 instruction->type = NDS32_INSN_DATA_PROC;
1971 snprintf(instruction->text,
1972 128,
1973 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1974 "\tBCLR\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1975 address,
1976 opcode, instruction->info.rt, instruction->info.ra,
1977 instruction->info.imm);
1978 }
1979 break;
1980 case 10: { /* BTGL */
1981 uint8_t imm;
1982 nds32_parse_type_3(opcode, &(instruction->info.rt),
1983 &(instruction->info.ra),
1984 &imm, &(instruction->info.imm));
1985 instruction->info.imm = imm;
1986 instruction->type = NDS32_INSN_DATA_PROC;
1987 snprintf(instruction->text,
1988 128,
1989 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1990 "\tBTGL\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1991 address,
1992 opcode, instruction->info.rt, instruction->info.ra,
1993 instruction->info.imm);
1994 }
1995 break;
1996 case 11: { /* BTST */
1997 uint8_t imm;
1998 nds32_parse_type_3(opcode, &(instruction->info.rt),
1999 &(instruction->info.ra),
2000 &imm, &(instruction->info.imm));
2001 instruction->info.imm = imm;
2002 instruction->type = NDS32_INSN_DATA_PROC;
2003 snprintf(instruction->text,
2004 128,
2005 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2006 "\tBTST\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2007 address,
2008 opcode, instruction->info.rt, instruction->info.ra,
2009 instruction->info.imm);
2010 }
2011 break;
2012 case 12: /* BSE */
2013 nds32_parse_type_3(opcode, &(instruction->info.rt),
2014 &(instruction->info.ra),
2015 &(instruction->info.rb), &(instruction->info.imm));
2016 instruction->type = NDS32_INSN_DATA_PROC;
2017 snprintf(instruction->text,
2018 128,
2019 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2020 "\tBSE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2021 address,
2022 opcode, instruction->info.rt, instruction->info.ra,
2023 instruction->info.rb);
2024 break;
2025 case 13: /* BSP */
2026 nds32_parse_type_3(opcode, &(instruction->info.rt),
2027 &(instruction->info.ra),
2028 &(instruction->info.rb), &(instruction->info.imm));
2029 instruction->type = NDS32_INSN_DATA_PROC;
2030 snprintf(instruction->text,
2031 128,
2032 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2033 "\tBSP\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2034 address,
2035 opcode, instruction->info.rt, instruction->info.ra,
2036 instruction->info.rb);
2037 break;
2038 case 14: /* FFB */
2039 nds32_parse_type_3(opcode, &(instruction->info.rt),
2040 &(instruction->info.ra),
2041 &(instruction->info.rb), &(instruction->info.imm));
2042 instruction->type = NDS32_INSN_DATA_PROC;
2043 snprintf(instruction->text,
2044 128,
2045 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2046 "\tFFB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2047 address,
2048 opcode, instruction->info.rt, instruction->info.ra,
2049 instruction->info.rb);
2050 break;
2051 case 15: /* FFMISM */
2052 nds32_parse_type_3(opcode, &(instruction->info.rt),
2053 &(instruction->info.ra),
2054 &(instruction->info.rb), &(instruction->info.imm));
2055 instruction->type = NDS32_INSN_DATA_PROC;
2056 snprintf(instruction->text,
2057 128,
2058 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2059 "\tFFMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2060 address,
2061 opcode, instruction->info.rt, instruction->info.ra,
2062 instruction->info.rb);
2063 break;
2064 case 23: /* FFZMISM */
2065 nds32_parse_type_3(opcode, &(instruction->info.rt),
2066 &(instruction->info.ra),
2067 &(instruction->info.rb), &(instruction->info.imm));
2068 instruction->type = NDS32_INSN_DATA_PROC;
2069 snprintf(instruction->text,
2070 128,
2071 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2072 "\tFFZMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2073 address,
2074 opcode, instruction->info.rt, instruction->info.ra,
2075 instruction->info.rb);
2076 break;
2077 case 32: /* MFUSR */
2078 nds32_parse_type_1(opcode, &(instruction->info.rt),
2079 &(instruction->info.imm));
2080 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2081 snprintf(instruction->text,
2082 128,
2083 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2084 "\tMFUSR\t$r%" PRIu8 ",#%" PRId32,
2085 address,
2086 opcode, instruction->info.rt,
2087 (instruction->info.imm >> 10) & 0x3FF);
2088 break;
2089 case 33: /* MTUSR */
2090 nds32_parse_type_1(opcode, &(instruction->info.rt),
2091 &(instruction->info.imm));
2092 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2093 snprintf(instruction->text,
2094 128,
2095 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2096 "\tMTUSR\t$r%" PRIu8 ",#%" PRId32,
2097 address,
2098 opcode, instruction->info.rt,
2099 (instruction->info.imm >> 10) & 0x3FF);
2100 break;
2101 case 36: /* MUL */
2102 nds32_parse_type_3(opcode, &(instruction->info.rt),
2103 &(instruction->info.ra),
2104 &(instruction->info.rb), &(instruction->info.imm));
2105 instruction->type = NDS32_INSN_DATA_PROC;
2106 snprintf(instruction->text,
2107 128,
2108 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2109 "\tMUL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2110 address,
2111 opcode, instruction->info.rt, instruction->info.ra,
2112 instruction->info.rb);
2113 break;
2114 case 40: { /* MULTS64 */
2115 uint8_t dt_val;
2116 nds32_parse_type_3(opcode, &dt_val,
2117 &(instruction->info.ra),
2118 &(instruction->info.rb), &(instruction->info.imm));
2119 instruction->type = NDS32_INSN_DATA_PROC;
2120 snprintf(instruction->text,
2121 128,
2122 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2123 "\tMULTS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2124 address,
2125 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2126 instruction->info.rb);
2127 }
2128 break;
2129 case 41: { /* MULT64 */
2130 uint8_t dt_val;
2131 nds32_parse_type_3(opcode, &dt_val,
2132 &(instruction->info.ra),
2133 &(instruction->info.rb), &(instruction->info.imm));
2134 instruction->type = NDS32_INSN_DATA_PROC;
2135 snprintf(instruction->text,
2136 128,
2137 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2138 "\tMULT64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2139 address,
2140 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2141 instruction->info.rb);
2142 }
2143 break;
2144 case 42: { /* MADDS64 */
2145 uint8_t dt_val;
2146 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2147 &(instruction->info.rb), &(instruction->info.imm));
2148 instruction->type = NDS32_INSN_DATA_PROC;
2149 snprintf(instruction->text,
2150 128,
2151 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2152 "\tMADDS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2153 address,
2154 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2155 instruction->info.rb);
2156 }
2157 break;
2158 case 43: { /* MADD64 */
2159 uint8_t dt_val;
2160 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2161 &(instruction->info.rb), &(instruction->info.imm));
2162 instruction->type = NDS32_INSN_DATA_PROC;
2163 snprintf(instruction->text,
2164 128,
2165 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2166 "\tMADD64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2167 address,
2168 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2169 instruction->info.rb);
2170 }
2171 break;
2172 case 44: { /* MSUBS64 */
2173 uint8_t dt_val;
2174 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2175 &(instruction->info.rb), &(instruction->info.imm));
2176 instruction->type = NDS32_INSN_DATA_PROC;
2177 snprintf(instruction->text,
2178 128,
2179 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2180 "\tMSUBS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2181 address,
2182 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2183 instruction->info.rb);
2184 }
2185 break;
2186 case 45: { /* MSUB64 */
2187 uint8_t dt_val;
2188 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2189 &(instruction->info.rb), &(instruction->info.imm));
2190 instruction->type = NDS32_INSN_DATA_PROC;
2191 snprintf(instruction->text,
2192 128,
2193 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2194 "\tMSUB64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2195 address,
2196 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2197 instruction->info.rb);
2198 }
2199 break;
2200 case 46: { /* DIVS */
2201 uint8_t dt_val;
2202 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2203 &(instruction->info.rb), &(instruction->info.imm));
2204 instruction->type = NDS32_INSN_DATA_PROC;
2205 snprintf(instruction->text,
2206 128,
2207 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2208 "\tDIVS\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2209 address,
2210 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2211 instruction->info.rb);
2212 }
2213 break;
2214 case 47: { /* DIV */
2215 uint8_t dt_val;
2216 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2217 &(instruction->info.rb), &(instruction->info.imm));
2218 instruction->type = NDS32_INSN_DATA_PROC;
2219 snprintf(instruction->text,
2220 128,
2221 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2222 "\tDIV\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2223 address,
2224 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2225 instruction->info.rb);
2226 }
2227 break;
2228 case 49: { /* MULT32 */
2229 uint8_t dt_val;
2230 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2231 &(instruction->info.rb), &(instruction->info.imm));
2232 instruction->type = NDS32_INSN_DATA_PROC;
2233 snprintf(instruction->text,
2234 128,
2235 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2236 "\tMULT32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2237 address,
2238 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2239 instruction->info.rb);
2240 }
2241 break;
2242 case 51: { /* MADD32 */
2243 uint8_t dt_val;
2244 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2245 &(instruction->info.rb), &(instruction->info.imm));
2246 instruction->type = NDS32_INSN_DATA_PROC;
2247 snprintf(instruction->text,
2248 128,
2249 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2250 "\tMADD32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2251 address,
2252 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2253 instruction->info.rb);
2254 }
2255 break;
2256 case 53: { /* MSUB32 */
2257 uint8_t dt_val;
2258 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2259 &(instruction->info.rb), &(instruction->info.imm));
2260 instruction->type = NDS32_INSN_DATA_PROC;
2261 snprintf(instruction->text,
2262 128,
2263 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2264 "\tMSUB32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2265 address,
2266 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2267 instruction->info.rb);
2268 }
2269 break;
2270 default:
2271 snprintf(instruction->text,
2272 128,
2273 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2274 address,
2275 opcode);
2276 return ERROR_FAIL;
2277 }
2278
2279 return ERROR_OK;
2280 }
2281
2282 static int nds32_parse_group_4_insn(struct nds32 *nds32, uint32_t opcode,
2283 uint32_t address, struct nds32_instruction *instruction)
2284 {
2285 uint8_t opc_6;
2286
2287 opc_6 = instruction->info.opc_6;
2288
2289 switch (opc_6 & 0x7) {
2290 case 0: /* ALU_1 */
2291 nds32_parse_alu_1(opcode, address, instruction);
2292 break;
2293 case 1: /* ALU_2 */
2294 nds32_parse_alu_2(opcode, address, instruction);
2295 break;
2296 case 2: /* MOVI */
2297 nds32_parse_type_1(opcode, &(instruction->info.rt),
2298 &(instruction->info.imm));
2299 /* sign-extend */
2300 instruction->info.imm = (instruction->info.imm << 12) >> 12;
2301 instruction->type = NDS32_INSN_DATA_PROC;
2302 snprintf(instruction->text,
2303 128,
2304 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2305 "\tMOVI\t$r%" PRIu8 ",#%" PRId32,
2306 address,
2307 opcode, instruction->info.rt, instruction->info.imm);
2308 break;
2309 case 3: /* SETHI */
2310 nds32_parse_type_1(opcode, &(instruction->info.rt),
2311 &(instruction->info.imm));
2312 instruction->type = NDS32_INSN_DATA_PROC;
2313 snprintf(instruction->text,
2314 128,
2315 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2316 "\tSETHI\t$r%" PRIu8 ",0x%8.8" PRIx32,
2317 address,
2318 opcode, instruction->info.rt, instruction->info.imm);
2319 break;
2320 case 4: /* JI */
2321 nds32_parse_type_0(opcode, &(instruction->info.imm));
2322 /* sign-extend */
2323 instruction->info.imm = (instruction->info.imm << 8) >> 8;
2324 instruction->type = NDS32_INSN_JUMP_BRANCH;
2325 if ((instruction->info.imm >> 24) & 0x1) { /* JAL */
2326 snprintf(instruction->text,
2327 128,
2328 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2329 "\tJAL\t#%" PRId32,
2330 address,
2331 opcode, instruction->info.imm);
2332 } else { /* J */
2333 snprintf(instruction->text,
2334 128,
2335 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2336 "\tJ\t#%" PRId32,
2337 address,
2338 opcode, instruction->info.imm);
2339 }
2340 break;
2341 case 5: { /* JREG */
2342 int32_t imm;
2343 nds32_parse_type_0(opcode, &imm);
2344 instruction->info.rb = (imm >> 10) & 0x1F;
2345 instruction->type = NDS32_INSN_JUMP_BRANCH;
2346 switch (imm & 0x1F) {
2347 /* TODO */
2348 case 0: /* JR */
2349 if (imm & 0x20) { /* RET */
2350 snprintf(instruction->text,
2351 128,
2352 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2353 "\tRET\t$r%" PRIu8,
2354 address,
2355 opcode, instruction->info.rb);
2356 } else { /* JR */
2357 snprintf(instruction->text,
2358 128,
2359 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2360 "\tJR\t$r%" PRIu8,
2361 address,
2362 opcode, instruction->info.rb);
2363 }
2364 break;
2365 case 1: /* JRAL */
2366 instruction->info.rt = (imm >> 20) & 0x1F;
2367 snprintf(instruction->text,
2368 128,
2369 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2370 "\tJRAL\t$r%" PRIu8 ",$r%" PRIu8,
2371 address,
2372 opcode, instruction->info.rt, instruction->info.rb);
2373 break;
2374 case 2: /* JRNEZ */
2375 snprintf(instruction->text,
2376 128,
2377 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2378 "\tJRNEZ\t$r%" PRIu8,
2379 address,
2380 opcode, instruction->info.rb);
2381 break;
2382 case 3: /* JRALNEZ */
2383 instruction->info.rt = (imm >> 20) & 0x1F;
2384 if (instruction->info.rt == R30)
2385 snprintf(instruction->text,
2386 128,
2387 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2388 "\tJRALNEZ\t$r%" PRIu8,
2389 address,
2390 opcode, instruction->info.rb);
2391 else
2392 snprintf(instruction->text,
2393 128,
2394 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2395 "\tJRALNEZ\t$r%" PRIu8 ",$r%" PRIu8,
2396 address,
2397 opcode,
2398 instruction->info.rt,
2399 instruction->info.rb);
2400 break;
2401 }
2402 }
2403 break;
2404 case 6: { /* BR1 */
2405 int32_t imm;
2406
2407 nds32_parse_type_0(opcode, &imm);
2408 instruction->type = NDS32_INSN_JUMP_BRANCH;
2409 if ((imm >> 14) & 0x1) { /* BNE */
2410 nds32_parse_type_2(opcode, &(instruction->info.rt),
2411 &(instruction->info.ra), &(instruction->info.imm));
2412 /* sign-extend */
2413 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2414 snprintf(instruction->text,
2415 128,
2416 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2417 "\tBNE\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2418 address,
2419 opcode, instruction->info.rt, instruction->info.ra,
2420 instruction->info.imm);
2421 } else { /* BEQ */
2422 nds32_parse_type_2(opcode, &(instruction->info.rt),
2423 &(instruction->info.ra), &(instruction->info.imm));
2424 /* sign-extend */
2425 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2426 snprintf(instruction->text,
2427 128,
2428 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2429 "\tBEQ\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2430 address,
2431 opcode, instruction->info.rt,
2432 instruction->info.ra,
2433 instruction->info.imm);
2434 }
2435 }
2436 break;
2437 case 7: { /* BR2 */
2438 int32_t imm;
2439
2440 nds32_parse_type_0(opcode, &imm);
2441 instruction->type = NDS32_INSN_JUMP_BRANCH;
2442 switch ((imm >> 16) & 0xF) {
2443 case 2: /* BEQZ */
2444 nds32_parse_type_1(opcode, &(instruction->info.rt),
2445 &(instruction->info.imm));
2446 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2447 snprintf(instruction->text,
2448 128,
2449 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2450 "\tBEQZ\t$r%" PRIu8 ",#%" PRId32,
2451 address,
2452 opcode, instruction->info.rt, instruction->info.imm);
2453 break;
2454 case 3: /* BNEZ */
2455 nds32_parse_type_1(opcode, &(instruction->info.rt),
2456 &(instruction->info.imm));
2457 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2458 snprintf(instruction->text,
2459 128,
2460 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2461 "\tBNEZ\t$r%" PRIu8 ",#%" PRId32,
2462 address,
2463 opcode, instruction->info.rt, instruction->info.imm);
2464 break;
2465 case 4: /* BGEZ */
2466 nds32_parse_type_1(opcode, &(instruction->info.rt),
2467 &(instruction->info.imm));
2468 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2469 snprintf(instruction->text,
2470 128,
2471 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2472 "\tBGEZ\t$r%" PRIu8 ",#%" PRId32,
2473 address,
2474 opcode, instruction->info.rt, instruction->info.imm);
2475 break;
2476 case 5: /* BLTZ */
2477 nds32_parse_type_1(opcode, &(instruction->info.rt),
2478 &(instruction->info.imm));
2479 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2480 snprintf(instruction->text,
2481 128,
2482 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2483 "\tBLTZ\t$r%" PRIu8 ",#%" PRId32,
2484 address,
2485 opcode, instruction->info.rt, instruction->info.imm);
2486 break;
2487 case 6: /* BGTZ */
2488 nds32_parse_type_1(opcode, &(instruction->info.rt),
2489 &(instruction->info.imm));
2490 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2491 snprintf(instruction->text,
2492 128,
2493 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2494 "\tBGTZ\t$r%" PRIu8 ",#%" PRId32,
2495 address,
2496 opcode, instruction->info.rt, instruction->info.imm);
2497 break;
2498 case 7: /* BLEZ */
2499 nds32_parse_type_1(opcode, &(instruction->info.rt),
2500 &(instruction->info.imm));
2501 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2502 snprintf(instruction->text,
2503 128,
2504 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2505 "\tBLEZ\t$r%" PRIu8 ",#%" PRId32,
2506 address,
2507 opcode, instruction->info.rt, instruction->info.imm);
2508 break;
2509 case 12: /* BGEZAL */
2510 nds32_parse_type_1(opcode, &(instruction->info.rt),
2511 &(instruction->info.imm));
2512 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2513 snprintf(instruction->text,
2514 128,
2515 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2516 "\tBGEZAL\t$r%" PRIu8 ",#%" PRId32,
2517 address,
2518 opcode, instruction->info.rt, instruction->info.imm);
2519 break;
2520 case 13: /* BLTZAL */
2521 nds32_parse_type_1(opcode, &(instruction->info.rt),
2522 &(instruction->info.imm));
2523 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2524 snprintf(instruction->text,
2525 128,
2526 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2527 "\tBLTZAL\t$r%" PRIu8 ",#%" PRId32,
2528 address,
2529 opcode, instruction->info.rt, instruction->info.imm);
2530 break;
2531 }
2532 }
2533 break;
2534 default:
2535 snprintf(instruction->text,
2536 128,
2537 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2538 address,
2539 opcode);
2540 return ERROR_FAIL;
2541 }
2542
2543 return ERROR_OK;
2544 }
2545
2546 static int nds32_parse_group_5_insn(struct nds32 *nds32, uint32_t opcode,
2547 uint32_t address, struct nds32_instruction *instruction)
2548 {
2549 uint8_t opc_6;
2550
2551 opc_6 = instruction->info.opc_6;
2552
2553 switch (opc_6 & 0x7) {
2554 case 0: /* ADDI */
2555 nds32_parse_type_2(opcode, &(instruction->info.rt),
2556 &(instruction->info.ra), &(instruction->info.imm));
2557 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2558 instruction->type = NDS32_INSN_DATA_PROC;
2559 snprintf(instruction->text,
2560 128,
2561 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2562 "\tADDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2563 address,
2564 opcode, instruction->info.rt, instruction->info.ra,
2565 instruction->info.imm);
2566 break;
2567 case 1: /* SUBRI */
2568 nds32_parse_type_2(opcode, &(instruction->info.rt),
2569 &(instruction->info.ra), &(instruction->info.imm));
2570 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2571 instruction->type = NDS32_INSN_DATA_PROC;
2572 snprintf(instruction->text,
2573 128,
2574 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2575 "\tSUBRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2576 address,
2577 opcode, instruction->info.rt, instruction->info.ra,
2578 instruction->info.imm);
2579 break;
2580 case 2: /* ANDI */
2581 nds32_parse_type_2(opcode, &(instruction->info.rt),
2582 &(instruction->info.ra), &(instruction->info.imm));
2583 instruction->type = NDS32_INSN_DATA_PROC;
2584 snprintf(instruction->text,
2585 128,
2586 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2587 "\tANDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2588 address,
2589 opcode, instruction->info.rt, instruction->info.ra,
2590 instruction->info.imm);
2591 break;
2592 case 3: /* XORI */
2593 nds32_parse_type_2(opcode, &(instruction->info.rt),
2594 &(instruction->info.ra), &(instruction->info.imm));
2595 instruction->type = NDS32_INSN_DATA_PROC;
2596 snprintf(instruction->text,
2597 128,
2598 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2599 "\tXORI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2600 address,
2601 opcode, instruction->info.rt, instruction->info.ra,
2602 instruction->info.imm);
2603 break;
2604 case 4: /* ORI */
2605 nds32_parse_type_2(opcode, &(instruction->info.rt),
2606 &(instruction->info.ra), &(instruction->info.imm));
2607 instruction->type = NDS32_INSN_DATA_PROC;
2608 snprintf(instruction->text,
2609 128,
2610 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2611 "\tORI\t$r%" PRIu8 ",$r%" PRIu8 ",0x%8.8" PRIx32,
2612 address,
2613 opcode, instruction->info.rt, instruction->info.ra,
2614 instruction->info.imm);
2615 break;
2616 case 6: /* SLTI */
2617 nds32_parse_type_2(opcode, &(instruction->info.rt),
2618 &(instruction->info.ra), &(instruction->info.imm));
2619 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2620 instruction->type = NDS32_INSN_DATA_PROC;
2621 snprintf(instruction->text,
2622 128,
2623 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2624 "\tSLTI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2625 address,
2626 opcode, instruction->info.rt, instruction->info.ra,
2627 instruction->info.imm);
2628 break;
2629 case 7: /* SLTSI */
2630 nds32_parse_type_2(opcode, &(instruction->info.rt),
2631 &(instruction->info.ra), &(instruction->info.imm));
2632 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2633 instruction->type = NDS32_INSN_DATA_PROC;
2634 snprintf(instruction->text,
2635 128,
2636 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2637 "\tSLTSI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2638 address,
2639 opcode, instruction->info.rt, instruction->info.ra,
2640 instruction->info.imm);
2641 break;
2642 default:
2643 snprintf(instruction->text,
2644 128,
2645 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2646 address,
2647 opcode);
2648 return ERROR_FAIL;
2649 }
2650
2651 return ERROR_OK;
2652 }
2653
2654 static int nds32_parse_group_6_insn(struct nds32 *nds32, uint32_t opcode,
2655 uint32_t address, struct nds32_instruction *instruction)
2656 {
2657 uint8_t opc_6;
2658
2659 opc_6 = instruction->info.opc_6;
2660
2661 switch (opc_6 & 0x7) {
2662 case 2: { /* MISC */
2663 int32_t imm;
2664 uint8_t sub_opc;
2665
2666 nds32_parse_type_0(opcode, &imm);
2667
2668 sub_opc = imm & 0x1F;
2669 switch (sub_opc) {
2670 case 0: /* STANDBY */
2671 instruction->type = NDS32_INSN_MISC;
2672 snprintf(instruction->text,
2673 128,
2674 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2675 "\tSTANDBY\t#%" PRIu32,
2676 address,
2677 opcode, (opcode >> 5) & 0x3);
2678 break;
2679 case 1: /* CCTL */
2680 /* TODO */
2681 nds32_parse_type_2(opcode, &(instruction->info.rt),
2682 &(instruction->info.ra), &(instruction->info.imm));
2683 instruction->type = NDS32_INSN_MISC;
2684 snprintf(instruction->text,
2685 128,
2686 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCCTL",
2687 address,
2688 opcode);
2689 break;
2690 case 2: /* MFSR */
2691 nds32_parse_type_1(opcode, &(instruction->info.rt),
2692 &(instruction->info.imm));
2693 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2694 snprintf(instruction->text,
2695 128,
2696 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2697 "\tMFSR\t$r%" PRIu8 ",#%" PRId32,
2698 address,
2699 opcode, instruction->info.rt,
2700 (instruction->info.imm >> 10) & 0x3FF);
2701 break;
2702 case 3: /* MTSR */
2703 nds32_parse_type_1(opcode, &(instruction->info.ra),
2704 &(instruction->info.imm));
2705 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2706 snprintf(instruction->text,
2707 128,
2708 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2709 "\tMTSR\t$r%" PRIu8 ",#%" PRId32,
2710 address,
2711 opcode, instruction->info.ra,
2712 (instruction->info.imm >> 10) & 0x3FF);
2713 break;
2714 case 4: /* IRET */
2715 instruction->type = NDS32_INSN_MISC;
2716 snprintf(instruction->text,
2717 128,
2718 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tIRET",
2719 address,
2720 opcode);
2721 break;
2722 case 5: /* TRAP */
2723 instruction->type = NDS32_INSN_MISC;
2724 snprintf(instruction->text,
2725 128,
2726 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2727 "\tTRAP\t#%" PRId32,
2728 address,
2729 opcode, (imm >> 5) & 0x7FFF);
2730 break;
2731 case 6: /* TEQZ */
2732 nds32_parse_type_1(opcode, &(instruction->info.ra),
2733 &(instruction->info.imm));
2734 instruction->type = NDS32_INSN_MISC;
2735 snprintf(instruction->text,
2736 128,
2737 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2738 "\tTEQZ\t$r%" PRIu8 ",#%" PRId32,
2739 address,
2740 opcode, instruction->info.ra,
2741 (instruction->info.imm >> 5) & 0x7FFF);
2742 break;
2743 case 7: /* TNEZ */
2744 nds32_parse_type_1(opcode, &(instruction->info.ra),
2745 &(instruction->info.imm));
2746 instruction->type = NDS32_INSN_MISC;
2747 snprintf(instruction->text,
2748 128,
2749 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2750 "\tTNEZ\t$r%" PRIu8 ",#%" PRId32,
2751 address,
2752 opcode, instruction->info.ra,
2753 (instruction->info.imm >> 5) & 0x7FFF);
2754 break;
2755 case 8: /* DSB */
2756 instruction->type = NDS32_INSN_MISC;
2757 snprintf(instruction->text,
2758 128,
2759 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB",
2760 address,
2761 opcode);
2762 break;
2763 case 9: /* ISB */
2764 instruction->type = NDS32_INSN_MISC;
2765 snprintf(instruction->text,
2766 128,
2767 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB",
2768 address,
2769 opcode);
2770 break;
2771 case 10: /* BREAK */
2772 instruction->type = NDS32_INSN_MISC;
2773 instruction->info.sub_opc = imm & 0x1F;
2774 instruction->info.imm = (imm >> 5) & 0x7FFF;
2775 snprintf(instruction->text,
2776 128,
2777 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2778 "\tBREAK\t#%" PRId32,
2779 address,
2780 opcode, instruction->info.imm);
2781 break;
2782 case 11: /* SYSCALL */
2783 instruction->type = NDS32_INSN_MISC;
2784 snprintf(instruction->text,
2785 128,
2786 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2787 "\tSYSCALL\t#%" PRId32,
2788 address,
2789 opcode, (imm >> 5) & 0x7FFF);
2790 break;
2791 case 12: /* MSYNC */
2792 instruction->type = NDS32_INSN_MISC;
2793 snprintf(instruction->text,
2794 128,
2795 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2796 "\tMSYNC\t#%" PRId32,
2797 address,
2798 opcode, (imm >> 5) & 0x7);
2799 break;
2800 case 13: /* ISYNC */
2801 nds32_parse_type_1(opcode, &(instruction->info.ra),
2802 &(instruction->info.imm));
2803 instruction->type = NDS32_INSN_MISC;
2804 snprintf(instruction->text,
2805 128,
2806 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2807 "\tISYNC\t$r%" PRIu8,
2808 address,
2809 opcode, instruction->info.ra);
2810 break;
2811 case 14: /* TLBOP */
2812 /* TODO */
2813 nds32_parse_type_2(opcode, &(instruction->info.rt),
2814 &(instruction->info.ra), &(instruction->info.imm));
2815 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2816 snprintf(instruction->text,
2817 128,
2818 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tTLBOP",
2819 address,
2820 opcode);
2821 break;
2822 }
2823
2824 break;
2825 }
2826 default:
2827 snprintf(instruction->text,
2828 128,
2829 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2830 address,
2831 opcode);
2832 return ERROR_FAIL;
2833 }
2834
2835 return ERROR_OK;
2836 }
2837
2838 static uint32_t field_mask[9] = {
2839 0x0,
2840 0x1,
2841 0x3,
2842 0x7,
2843 0xF,
2844 0x1F,
2845 0x3F,
2846 0x7F,
2847 0xFF,
2848 };
2849
2850 static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length)
2851 {
2852 if (0 < length && length < 9)
2853 return (opcode >> start) & field_mask[length];
2854
2855 return 0;
2856 }
2857
2858 static int nds32_parse_group_0_insn_16(struct nds32 *nds32, uint16_t opcode,
2859 uint32_t address, struct nds32_instruction *instruction)
2860 {
2861 switch ((opcode >> 10) & 0x7) {
2862 case 0: /* MOV55 */
2863 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2864 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
2865 instruction->type = NDS32_INSN_MISC;
2866 snprintf(instruction->text,
2867 128,
2868 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2869 "\t\tMOV55\t$r%" PRIu8 ",$r%" PRIu8,
2870 address,
2871 opcode, instruction->info.rt, instruction->info.ra);
2872 break;
2873 case 1: /* MOVI55 */
2874 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2875 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2876 instruction->info.imm = (instruction->info.imm << 27) >> 27;
2877 instruction->type = NDS32_INSN_MISC;
2878 snprintf(instruction->text,
2879 128,
2880 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2881 "\t\tMOVI55\t$r%" PRIu8 ",#%" PRId32,
2882 address,
2883 opcode, instruction->info.rt, instruction->info.imm);
2884 break;
2885 case 2: /* ADD45, SUB45 */
2886 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2887 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
2888 instruction->type = NDS32_INSN_DATA_PROC;
2889 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD45 */
2890 snprintf(instruction->text,
2891 128,
2892 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2893 "\t\tADD45\t$r%" PRIu8 ",$r%" PRIu8,
2894 address,
2895 opcode, instruction->info.rt, instruction->info.rb);
2896 } else { /* SUB45 */
2897 snprintf(instruction->text,
2898 128,
2899 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2900 "\t\tSUB45\t$r%" PRIu8 ",$r%" PRIu8,
2901 address,
2902 opcode, instruction->info.rt, instruction->info.rb);
2903 }
2904
2905 break;
2906 case 3: /* ADDI45, SUBI45 */
2907 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2908 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2909 instruction->type = NDS32_INSN_DATA_PROC;
2910 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI45 */
2911 snprintf(instruction->text,
2912 128,
2913 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2914 "\t\tADDI45\t$r%" PRIu8 ",#%" PRId32,
2915 address,
2916 opcode, instruction->info.rt, instruction->info.imm);
2917 } else { /* SUBI45 */
2918 snprintf(instruction->text,
2919 128,
2920 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2921 "\t\tSUBI45\t$r%" PRIu8 ",#%" PRId32,
2922 address,
2923 opcode, instruction->info.rt, instruction->info.imm);
2924 }
2925 break;
2926 case 4: /* SRAI45, SRLI45 */
2927 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2928 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2929 instruction->type = NDS32_INSN_DATA_PROC;
2930 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SRAI45 */
2931 snprintf(instruction->text,
2932 128,
2933 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2934 "\t\tSRAI45\t$r%" PRIu8 ",#%" PRId32,
2935 address,
2936 opcode, instruction->info.rt, instruction->info.imm);
2937 } else { /* SRLI45 */
2938 if ((instruction->info.rt == 0) && (instruction->info.imm == 0)) {
2939 snprintf(instruction->text,
2940 128,
2941 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 "\t\tNOP",
2942 address,
2943 opcode);
2944 } else {
2945 snprintf(instruction->text,
2946 128,
2947 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2948 "\t\tSRLI45\t$r%" PRIu8 ",#%" PRId32,
2949 address,
2950 opcode, instruction->info.rt, instruction->info.imm);
2951 }
2952 }
2953 break;
2954 case 5:
2955 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
2956 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
2957 instruction->type = NDS32_INSN_DATA_PROC;
2958 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SLLI333 */
2959 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
2960 snprintf(instruction->text,
2961 128,
2962 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2963 "\t\tSLLI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2964 address,
2965 opcode, instruction->info.rt, instruction->info.ra,
2966 instruction->info.imm);
2967 } else {
2968 instruction->info.sub_opc = nds32_extract_field_8u(opcode, 0, 3);
2969 switch (instruction->info.sub_opc) {
2970 case 0: /* ZEB33 */
2971 snprintf(instruction->text,
2972 128,
2973 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2974 "\t\tZEB33\t$r%" PRIu8 ",$r%" PRIu8,
2975 address,
2976 opcode, instruction->info.rt, instruction->info.ra);
2977 break;
2978 case 1: /* ZEH33 */
2979 snprintf(instruction->text,
2980 128,
2981 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2982 "\t\tZEH33\t$r%" PRIu8 ",$r%" PRIu8,
2983 address,
2984 opcode, instruction->info.rt, instruction->info.ra);
2985 break;
2986 case 2: /* SEB33 */
2987 snprintf(instruction->text,
2988 128,
2989 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2990 "\t\tSEB33\t$r%" PRIu8 ",$r%" PRIu8,
2991 address,
2992 opcode, instruction->info.rt, instruction->info.ra);
2993 break;
2994 case 3: /* SEH33 */
2995 snprintf(instruction->text,
2996 128,
2997 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2998 "\t\tSEH33\t$r%" PRIu8 ",$r%" PRIu8,
2999 address,
3000 opcode, instruction->info.rt, instruction->info.ra);
3001 break;
3002 case 4: /* XLSB33 */
3003 snprintf(instruction->text,
3004 128,
3005 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3006 "\t\tXLSB33\t$r%" PRIu8 ",$r%" PRIu8,
3007 address,
3008 opcode, instruction->info.rt, instruction->info.ra);
3009 break;
3010 case 5: /* XLLB33 */
3011 snprintf(instruction->text,
3012 128,
3013 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3014 "\t\tXLLB33\t$r%" PRIu8 ",$r%" PRIu8,
3015 address,
3016 opcode, instruction->info.rt, instruction->info.ra);
3017 break;
3018 case 6: /* BMSKI33 */
3019 instruction->info.ra = 0;
3020 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3021 snprintf(instruction->text,
3022 128,
3023 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3024 "\t\tBMSKI33\t$r%" PRIu8 ",$r%" PRId32,
3025 address,
3026 opcode, instruction->info.rt, instruction->info.imm);
3027 break;
3028 case 7: /* FEXTI33 */
3029 instruction->info.ra = 0;
3030 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3031 snprintf(instruction->text,
3032 128,
3033 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3034 "\t\tFEXTI33\t$r%" PRIu8 ",$r%" PRId32,
3035 address,
3036 opcode, instruction->info.rt, instruction->info.imm);
3037 break;
3038 default:
3039 snprintf(instruction->text,
3040 128,
3041 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3042 "\tUNDEFINED INSTRUCTION",
3043 address,
3044 opcode);
3045 return ERROR_FAIL;
3046 }
3047 }
3048 break;
3049 case 6: /* ADD333, SUB333 */
3050 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3051 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3052 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 3);
3053 instruction->type = NDS32_INSN_DATA_PROC;
3054 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD333 */
3055 snprintf(instruction->text,
3056 128,
3057 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3058 "\t\tADD333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3059 address,
3060 opcode, instruction->info.rt, instruction->info.ra,
3061 instruction->info.rb);
3062 } else { /* SUB333 */
3063 snprintf(instruction->text,
3064 128,
3065 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3066 "\t\tSUB333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3067 address,
3068 opcode, instruction->info.rt, instruction->info.ra,
3069 instruction->info.rb);
3070 }
3071 break;
3072 case 7: /* ADDI333, SUBI333 */
3073 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3074 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3075 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3076 instruction->type = NDS32_INSN_DATA_PROC;
3077 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI333 */
3078 snprintf(instruction->text,
3079 128,
3080 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3081 "\t\tADDI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3082 address,
3083 opcode, instruction->info.rt, instruction->info.ra,
3084 instruction->info.imm);
3085 } else { /* SUBI333 */
3086 snprintf(instruction->text,
3087 128,
3088 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3089 "\t\tSUBI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3090 address,
3091 opcode, instruction->info.rt, instruction->info.ra,
3092 instruction->info.imm);
3093 }
3094 break;
3095 default:
3096 snprintf(instruction->text,
3097 128,
3098 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3099 address,
3100 opcode);
3101 return ERROR_FAIL;
3102 }
3103
3104 return ERROR_OK;
3105 }
3106
3107 static int nds32_parse_group_1_insn_16(struct nds32 *nds32, uint16_t opcode,
3108 uint32_t address, struct nds32_instruction *instruction)
3109 {
3110 switch ((opcode >> 9) & 0xF) {
3111 case 0: /* LWI333 */
3112 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3113 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3114 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3115 instruction->type = NDS32_INSN_LOAD_STORE;
3116 nds32_get_mapped_reg(nds32, instruction->info.ra,
3117 &(instruction->access_start));
3118 instruction->access_start += instruction->info.imm;
3119 instruction->access_end = instruction->access_start + 4;
3120 snprintf(instruction->text,
3121 128,
3122 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3123 "\t\tLWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3124 address,
3125 opcode, instruction->info.rt, instruction->info.ra,
3126 instruction->info.imm);
3127 break;
3128 case 1: /* LWI333.BI */
3129 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3130 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3131 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3132 instruction->type = NDS32_INSN_LOAD_STORE;
3133 nds32_get_mapped_reg(nds32, instruction->info.ra,
3134 &(instruction->access_start));
3135 instruction->access_end = instruction->access_start + 4;
3136 snprintf(instruction->text,
3137 128,
3138 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3139 "\t\tLWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3140 address,
3141 opcode, instruction->info.rt, instruction->info.ra,
3142 instruction->info.imm << 2);
3143 break;
3144 case 2: /* LHI333 */
3145 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3146 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3147 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3148 instruction->type = NDS32_INSN_LOAD_STORE;
3149 nds32_get_mapped_reg(nds32, instruction->info.ra,
3150 &(instruction->access_start));
3151 instruction->access_start += instruction->info.imm;
3152 instruction->access_end = instruction->access_start + 2;
3153 snprintf(instruction->text,
3154 128,
3155 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3156 "\t\tLHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3157 address,
3158 opcode, instruction->info.rt, instruction->info.ra,
3159 instruction->info.imm);
3160 break;
3161 case 3: /* LBI333 */
3162 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3163 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3164 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3165 instruction->type = NDS32_INSN_LOAD_STORE;
3166 nds32_get_mapped_reg(nds32, instruction->info.ra,
3167 &(instruction->access_start));
3168 instruction->access_start += instruction->info.imm;
3169 instruction->access_end = instruction->access_start + 1;
3170 snprintf(instruction->text,
3171 128,
3172 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3173 "\t\tLBI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3174 address,
3175 opcode, instruction->info.rt, instruction->info.ra,
3176 instruction->info.imm);
3177 break;
3178 case 4: /* SWI333 */
3179 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3180 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3181 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3182 instruction->type = NDS32_INSN_LOAD_STORE;
3183 nds32_get_mapped_reg(nds32, instruction->info.ra,
3184 &(instruction->access_start));
3185 instruction->access_start += instruction->info.imm;
3186 instruction->access_end = instruction->access_start + 4;
3187 snprintf(instruction->text,
3188 128,
3189 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3190 "\t\tSWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3191 address,
3192 opcode, instruction->info.rt, instruction->info.ra,
3193 instruction->info.imm);
3194 break;
3195 case 5: /* SWI333.BI */
3196 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3197 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3198 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3199 instruction->type = NDS32_INSN_LOAD_STORE;
3200 nds32_get_mapped_reg(nds32, instruction->info.ra,
3201 &(instruction->access_start));
3202 instruction->access_end = instruction->access_start + 4;
3203 snprintf(instruction->text,
3204 128,
3205 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3206 "\t\tSWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3207 address,
3208 opcode, instruction->info.rt, instruction->info.ra,
3209 instruction->info.imm);
3210 break;
3211 case 6: /* SHI333 */
3212 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3213 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3214 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3215 instruction->type = NDS32_INSN_LOAD_STORE;
3216 nds32_get_mapped_reg(nds32, instruction->info.ra,
3217 &(instruction->access_start));
3218 instruction->access_start += instruction->info.imm;
3219 instruction->access_end = instruction->access_start + 2;
3220 snprintf(instruction->text,
3221 128,
3222 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3223 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3224 address,
3225 opcode, instruction->info.rt, instruction->info.ra,
3226 instruction->info.imm);
3227 break;
3228 case 7: /* SBI333 */
3229 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3230 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3231 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3232 instruction->type = NDS32_INSN_LOAD_STORE;
3233 nds32_get_mapped_reg(nds32, instruction->info.ra,
3234 &(instruction->access_start));
3235 instruction->access_start += instruction->info.imm;
3236 instruction->access_end = instruction->access_start + 1;
3237 snprintf(instruction->text,
3238 128,
3239 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3240 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3241 address,
3242 opcode, instruction->info.rt, instruction->info.ra,
3243 instruction->info.imm);
3244 break;
3245 case 8: /* ADDRI36.SP */
3246 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3247 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 6) << 2;
3248 instruction->type = NDS32_INSN_DATA_PROC;
3249 snprintf(instruction->text,
3250 128,
3251 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3252 "\t\tADDRI36.SP\t$r%" PRIu8 ",#%" PRId32,
3253 address,
3254 opcode, instruction->info.rt, instruction->info.imm);
3255 break;
3256 case 9: /* LWI45.FE */
3257 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3258 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3259 instruction->info.imm -= 32;
3260 instruction->info.imm <<= 2;
3261 instruction->type = NDS32_INSN_LOAD_STORE;
3262 nds32_get_mapped_reg(nds32, R8, &(instruction->access_start));
3263 instruction->access_start += instruction->info.imm;
3264 instruction->access_end = instruction->access_start + 4;
3265 snprintf(instruction->text,
3266 128,
3267 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3268 "\t\tLWI45.FE\t$r%" PRIu8 ",[#%" PRId32 "]",
3269 address,
3270 opcode, instruction->info.rt, instruction->info.imm);
3271 break;
3272 case 10: /* LWI450 */
3273 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3274 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3275 instruction->type = NDS32_INSN_LOAD_STORE;
3276 nds32_get_mapped_reg(nds32, instruction->info.ra,
3277 &(instruction->access_start));
3278 instruction->access_end = instruction->access_start + 4;
3279 snprintf(instruction->text,
3280 128,
3281 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3282 "\t\tLWI450\t$r%" PRIu8 ",$r%" PRIu8,
3283 address,
3284 opcode, instruction->info.rt, instruction->info.ra);
3285 break;
3286 case 11: /* SWI450 */
3287 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3288 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3289 instruction->type = NDS32_INSN_LOAD_STORE;
3290 nds32_get_mapped_reg(nds32, instruction->info.ra,
3291 &(instruction->access_start));
3292 instruction->access_end = instruction->access_start + 4;
3293 snprintf(instruction->text,
3294 128,
3295 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3296 "\t\tSWI450\t$r%" PRIu8 ",$r%" PRIu8,
3297 address,
3298 opcode, instruction->info.rt, instruction->info.ra);
3299 break;
3300 case 12:
3301 case 13:
3302 case 14:
3303 case 15: /* LWI37, SWI37 */
3304 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3305 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3306 instruction->type = NDS32_INSN_LOAD_STORE;
3307 nds32_get_mapped_reg(nds32, R28, &(instruction->access_start));
3308 instruction->access_start += instruction->info.imm;
3309 instruction->access_end = instruction->access_start + 4;
3310 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37 */
3311 snprintf(instruction->text,
3312 128,
3313 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3314 "\t\tLWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3315 address,
3316 opcode, instruction->info.rt, instruction->info.imm);
3317 } else { /* SWI37 */
3318 snprintf(instruction->text,
3319 128,
3320 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3321 "\t\tSWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3322 address,
3323 opcode, instruction->info.rt, instruction->info.imm);
3324 }
3325 break;
3326 default: /* ERROR */
3327 snprintf(instruction->text,
3328 128,
3329 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3330 address,
3331 opcode);
3332 return ERROR_FAIL;
3333 }
3334
3335 return ERROR_OK;
3336 }
3337
3338 static int nds32_parse_group_2_insn_16(struct nds32 *nds32, uint16_t opcode,
3339 uint32_t address, struct nds32_instruction *instruction)
3340 {
3341 switch ((opcode >> 11) & 0x3) {
3342 case 0: /* BEQZ38 */
3343 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3344 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3345 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3346 instruction->type = NDS32_INSN_JUMP_BRANCH;
3347 snprintf(instruction->text,
3348 128,
3349 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3350 "\t\tBEQZ38\t$r%" PRIu8 ",#%" PRId32,
3351 address,
3352 opcode, instruction->info.rt, instruction->info.imm);
3353 break;
3354 case 1: /* BNEZ38 */
3355 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3356 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3357 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3358 instruction->type = NDS32_INSN_JUMP_BRANCH;
3359 snprintf(instruction->text,
3360 128,
3361 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3362 "\t\tBNEZ38\t$r%" PRIu8 ",#%" PRId32,
3363 address,
3364 opcode, instruction->info.rt, instruction->info.imm);
3365 break;
3366 case 2: /* BEQS38,J8 */
3367 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3368 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3369 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3370 instruction->type = NDS32_INSN_JUMP_BRANCH;
3371 if (instruction->info.rt == 5) { /* J8 */
3372 snprintf(instruction->text,
3373 128,
3374 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3375 "\t\tJ8\t#%" PRId32,
3376 address,
3377 opcode, instruction->info.imm);
3378 } else { /* BEQS38 */
3379 snprintf(instruction->text,
3380 128,
3381 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3382 "\t\tBEQS38\t$r%" PRIu8 ",#%" PRId32,
3383 address,
3384 opcode, instruction->info.rt, instruction->info.imm);
3385 }
3386 break;
3387 case 3: /* BNES38, JR5, RET5, JRAL5 */
3388 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3389 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3390 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3391 instruction->type = NDS32_INSN_JUMP_BRANCH;
3392 if (instruction->info.rt == 5) {
3393 instruction->info.imm = 0;
3394 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3395 switch (nds32_extract_field_8u(opcode, 5, 3)) {
3396 case 0: /* JR5 */
3397 snprintf(instruction->text,
3398 128,
3399 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3400 "\t\tJR5\t$r%" PRIu8,
3401 address,
3402 opcode, instruction->info.rb);
3403 break;
3404 case 1: /* JRAL5 */
3405 snprintf(instruction->text,
3406 128,
3407 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3408 "\t\tJRAL5\t$r%" PRIu8,
3409 address,
3410 opcode, instruction->info.rb);
3411 break;
3412 case 2: /* EX9.IT */
3413 instruction->info.rb = 0;
3414 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3415 /* TODO: implement real instruction semantics */
3416 snprintf(instruction->text,
3417 128,
3418 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3419 "\t\tEX9.IT\t#%" PRId32,
3420 address,
3421 opcode, instruction->info.imm);
3422 break;
3423 case 4: /* RET5 */
3424 snprintf(instruction->text,
3425 128,
3426 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3427 "\t\tRET5\t$r%" PRIu8,
3428 address,
3429 opcode, instruction->info.rb);
3430 break;
3431 case 5: /* ADD5.PC */
3432 instruction->info.rt = 0;
3433 instruction->info.rt = nds32_extract_field_8u(opcode, 0, 5);
3434 instruction->type = NDS32_INSN_DATA_PROC;
3435 snprintf(instruction->text,
3436 128,
3437 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3438 "\t\tADD5.PC\t$r%" PRIu8,
3439 address,
3440 opcode, instruction->info.rt);
3441 break;
3442 default:
3443 snprintf(instruction->text,
3444 128,
3445 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3446 "\tUNDEFINED INSTRUCTION",
3447 address,
3448 opcode);
3449 return ERROR_FAIL;
3450 }
3451 } else { /* BNES38 */
3452 snprintf(instruction->text,
3453 128,
3454 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3455 "\t\tBNES38\t$r%" PRIu8 ",#%" PRId32,
3456 address,
3457 opcode, instruction->info.rt, instruction->info.imm);
3458 }
3459 break;
3460 }
3461
3462 return ERROR_OK;
3463 }
3464
3465 static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode,
3466 uint32_t address, struct nds32_instruction *instruction)
3467 {
3468 switch ((opcode >> 11) & 0x3) {
3469 case 0:
3470 switch ((opcode >> 9) & 0x3) {
3471 case 0: /* SLTS45 */
3472 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3473 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3474 instruction->type = NDS32_INSN_DATA_PROC;
3475 snprintf(instruction->text,
3476 128,
3477 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3478 "\t\tSLTS45\t$r%" PRIu8 ",$r%" PRIu8,
3479 address,
3480 opcode, instruction->info.ra, instruction->info.rb);
3481 break;
3482 case 1: /* SLT45 */
3483 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3484 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3485 instruction->type = NDS32_INSN_DATA_PROC;
3486 snprintf(instruction->text,
3487 128,
3488 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3489 "\t\tSLT45\t$r%" PRIu8 ",$r%" PRIu8,
3490 address,
3491 opcode, instruction->info.ra, instruction->info.rb);
3492 break;
3493 case 2: /* SLTSI45 */
3494 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3495 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3496 instruction->type = NDS32_INSN_DATA_PROC;
3497 snprintf(instruction->text,
3498 128,
3499 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3500 "\t\tSLTSI45\t$r%" PRIu8 ",#%" PRId32,
3501 address,
3502 opcode, instruction->info.ra, instruction->info.imm);
3503 break;
3504 case 3: /* SLTI45 */
3505 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3506 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3507 instruction->type = NDS32_INSN_DATA_PROC;
3508 snprintf(instruction->text,
3509 128,
3510 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3511 "\t\tSLTI45\t$r%" PRIu8 ",#%" PRId32,
3512 address,
3513 opcode, instruction->info.ra, instruction->info.imm);
3514 break;
3515 }
3516 break;
3517 case 1:
3518 switch ((opcode >> 9) & 0x3) {
3519 case 0:
3520 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3521 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3522 instruction->type = NDS32_INSN_JUMP_BRANCH;
3523 if (nds32_extract_field_8u(opcode, 8, 1) == 0) { /* BEQZS8 */
3524 snprintf(instruction->text,
3525 128,
3526 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3527 "\t\tBEQZS8\t#%" PRId32,
3528 address,
3529 opcode, instruction->info.imm);
3530 } else { /* BNEZS8 */
3531 snprintf(instruction->text,
3532 128,
3533 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3534 "\t\tBNEZS8\t#%" PRId32,
3535 address,
3536 opcode, instruction->info.imm);
3537 }
3538 break;
3539 case 1: /* BREAK16 */
3540 if (((opcode >> 5) & 0xF) == 0) {
3541 instruction->type = NDS32_INSN_MISC;
3542 snprintf(instruction->text,
3543 128,
3544 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3545 "\t\tBREAK16\t#%" PRId16,
3546 address,
3547 opcode, (int16_t)(opcode & 0x1F));
3548 } else { /* EX9.IT */
3549 instruction->type = NDS32_INSN_MISC;
3550 /* TODO: implement real instruction semantics */
3551 snprintf(instruction->text,
3552 128,
3553 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3554 "\t\tEX9.IT\t#%" PRId16,
3555 address,
3556 opcode, (int16_t)(opcode & 0x1FF));
3557 }
3558 break;
3559 case 2: /* ADDI10S */
3560 case 3:
3561 instruction->info.imm = opcode & 0x3FF;
3562 instruction->info.imm = (instruction->info.imm << 22) >> 22;
3563 instruction->type = NDS32_INSN_DATA_PROC;
3564 snprintf(instruction->text,
3565 128,
3566 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3567 "\t\tADDI10.SP\t#%" PRId32,
3568 address,
3569 opcode, instruction->info.imm);
3570 break;
3571 }
3572 break;
3573 case 2:
3574 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3575 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3576 instruction->type = NDS32_INSN_LOAD_STORE;
3577 nds32_get_mapped_reg(nds32, R31, &(instruction->access_start));
3578 instruction->access_start += instruction->info.imm;
3579 instruction->access_end = instruction->access_start + 4;
3580 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37.SP */
3581 snprintf(instruction->text,
3582 128,
3583 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3584 "\t\tLWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3585 address,
3586 opcode, instruction->info.rt, instruction->info.imm);
3587 } else { /* SWI37.SP */
3588 snprintf(instruction->text,
3589 128,
3590 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3591 "\t\tSWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3592 address,
3593 opcode, instruction->info.rt, instruction->info.imm);
3594 }
3595 break;
3596 case 3:
3597 switch ((opcode >> 9) & 0x3) {
3598 case 0: /* IFCALL9 */
3599 instruction->info.imm = opcode & 0x1FF;
3600 instruction->type = NDS32_INSN_JUMP_BRANCH;
3601 snprintf(instruction->text,
3602 128,
3603 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3604 "\t\tIFCALL9\t#%" PRId32 "",
3605 address,
3606 opcode, instruction->info.imm);
3607 break;
3608 case 1: /* MOVPI45 */
3609 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5) + 16;
3610 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3611 instruction->type = NDS32_INSN_MISC;
3612 snprintf(instruction->text,
3613 128,
3614 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3615 "\t\tMOVPI45\t$r%" PRIu8 ",#%" PRId32 "",
3616 address,
3617 opcode, instruction->info.rt, instruction->info.imm);
3618 break;
3619 case 2: /* PUSH25, POP25, MOVD44 */
3620 switch ((opcode >> 7) & 0x3) {
3621 case 0: /* PUSH25 */
3622 {
3623 uint8_t re;
3624 uint8_t gpr_count;
3625
3626 instruction->type = NDS32_INSN_LOAD_STORE;
3627 instruction->info.imm =
3628 nds32_extract_field_8u(opcode, 0, 5) << 3;
3629 re = nds32_extract_field_8u(opcode, 5, 2);
3630
3631 if (re == 0)
3632 re = 6;
3633 else if (re == 1)
3634 re = 8;
3635 else if (re == 2)
3636 re = 10;
3637 else if (re == 3)
3638 re = 14;
3639
3640 instruction->info.rd = re;
3641 /* GPRs list: R6 ~ Re and fp, gp, lp */
3642 gpr_count = 3 + (re - 5);
3643
3644 nds32_get_mapped_reg(nds32, R31,
3645 &(instruction->access_end));
3646 instruction->access_start =
3647 instruction->access_end - (gpr_count * 4);
3648
3649 snprintf(instruction->text,
3650 128,
3651 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3652 "\t\tPUSH25\t$r%" PRIu8 ",#%" PRId32,
3653 address,
3654 opcode, instruction->info.rd,
3655 instruction->info.imm);
3656 }
3657 break;
3658 case 1: /* POP25 */
3659 {
3660 uint8_t re;
3661 uint8_t gpr_count;
3662
3663 instruction->type = NDS32_INSN_LOAD_STORE;
3664 instruction->info.imm =
3665 nds32_extract_field_8u(opcode, 0, 5) << 3;
3666 re = nds32_extract_field_8u(opcode, 5, 2);
3667
3668 if (re == 0)
3669 re = 6;
3670 else if (re == 1)
3671 re = 8;
3672 else if (re == 2)
3673 re = 10;
3674 else if (re == 3)
3675 re = 14;
3676
3677 instruction->info.rd = re;
3678 /* GPRs list: R6 ~ Re and fp, gp, lp */
3679 gpr_count = 3 + (re - 5);
3680
3681 nds32_get_mapped_reg(nds32, R31,
3682 &(instruction->access_start));
3683 instruction->access_start += instruction->info.imm;
3684 instruction->access_end =
3685 instruction->access_start + (gpr_count * 4);
3686
3687 snprintf(instruction->text,
3688 128,
3689 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3690 "\t\tPOP25\t$r%" PRIu8 ",#%" PRId32,
3691 address,
3692 opcode, instruction->info.rd,
3693 instruction->info.imm);
3694 }
3695 break;
3696 case 2: /* MOVD44 */
3697 case 3:
3698 instruction->info.ra =
3699 nds32_extract_field_8u(opcode, 0, 4) * 2;
3700 instruction->info.rt =
3701 nds32_extract_field_8u(opcode, 4, 4) * 2;
3702 instruction->type = NDS32_INSN_MISC;
3703 snprintf(instruction->text,
3704 128,
3705 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3706 "\t\tMOVD44\t$r%" PRIu8 ",$r%" PRIu8,
3707 address,
3708 opcode, instruction->info.rt, instruction->info.ra);
3709 break;
3710 }
3711 break;
3712 case 3: /* NEG33, NOT33, MUL33, XOR33, AND33, OR33 */
3713 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3714 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3715 instruction->type = NDS32_INSN_DATA_PROC;
3716 switch (opcode & 0x7) {
3717 case 2: /* NEG33 */
3718 snprintf(instruction->text,
3719 128,
3720 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3721 "\t\tNEG33\t$r%" PRIu8 ",$r%" PRIu8,
3722 address,
3723 opcode, instruction->info.rt, instruction->info.ra);
3724 break;
3725 case 3: /* NOT33 */
3726 snprintf(instruction->text,
3727 128,
3728 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3729 "\t\tNOT33\t$r%" PRIu8 ",$r%" PRIu8,
3730 address,
3731 opcode, instruction->info.rt, instruction->info.ra);
3732 break;
3733 case 4: /* MUL33 */
3734 snprintf(instruction->text,
3735 128,
3736 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3737 "\t\tMUL33\t$r%" PRIu8 ",$r%" PRIu8,
3738 address,
3739 opcode, instruction->info.rt, instruction->info.ra);
3740 break;
3741 case 5: /* XOR33 */
3742 snprintf(instruction->text,
3743 128,
3744 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3745 "\t\tXOR33\t$r%" PRIu8 ",$r%" PRIu8,
3746 address,
3747 opcode, instruction->info.rt, instruction->info.ra);
3748 break;
3749 case 6: /* AND33 */
3750 snprintf(instruction->text,
3751 128,
3752 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3753 "\t\tAND33\t$r%" PRIu8 ",$r%" PRIu8,
3754 address,
3755 opcode, instruction->info.rt, instruction->info.ra);
3756 break;
3757 case 7: /* OR33 */
3758 snprintf(instruction->text,
3759 128,
3760 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3761 "\t\tOR33\t$r%" PRIu8 ",$r%" PRIu8,
3762 address,
3763 opcode, instruction->info.rt, instruction->info.ra);
3764 break;
3765 }
3766 break;
3767 }
3768 break;
3769 default:
3770 snprintf(instruction->text,
3771 128,
3772 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3773 address,
3774 opcode);
3775 return ERROR_FAIL;
3776 }
3777
3778 return ERROR_OK;
3779 }
3780
3781 int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address,
3782 struct nds32_instruction *instruction)
3783 {
3784 int retval = ERROR_OK;
3785
3786 /* clear fields, to avoid confusion */
3787 memset(instruction, 0, sizeof(struct nds32_instruction));
3788
3789 if (opcode >> 31) {
3790 /* 16 bits instruction */
3791 instruction->instruction_size = 2;
3792 opcode = (opcode >> 16) & 0xFFFF;
3793 instruction->opcode = opcode;
3794
3795 switch ((opcode >> 13) & 0x3) {
3796 case 0:
3797 retval = nds32_parse_group_0_insn_16(nds32, opcode, address, instruction);
3798 break;
3799 case 1:
3800 retval = nds32_parse_group_1_insn_16(nds32, opcode, address, instruction);
3801 break;
3802 case 2:
3803 retval = nds32_parse_group_2_insn_16(nds32, opcode, address, instruction);
3804 break;
3805 case 3:
3806 retval = nds32_parse_group_3_insn_16(nds32, opcode, address, instruction);
3807 break;
3808 default:
3809 snprintf(instruction->text,
3810 128,
3811 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
3812 address,
3813 opcode);
3814 return ERROR_FAIL;
3815 }
3816 } else {
3817 /* 32 bits instruction */
3818 instruction->instruction_size = 4;
3819 instruction->opcode = opcode;
3820
3821 uint8_t opc_6;
3822 opc_6 = opcode >> 25;
3823 instruction->info.opc_6 = opc_6;
3824
3825 switch ((opc_6 >> 3) & 0x7) {
3826 case 0: /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
3827 retval = nds32_parse_group_0_insn(nds32, opcode, address, instruction);
3828 break;
3829 case 1: /* SBI, SHI, SWI, SBI.bi, SHI.bi, SWI.bi */
3830 retval = nds32_parse_group_1_insn(nds32, opcode, address, instruction);
3831 break;
3832 case 2: /* LBSI, LHSI, DPREFI, LBSI.bi, LHSI.bi, LBGP */
3833 retval = nds32_parse_group_2_insn(nds32, opcode, address, instruction);
3834 break;
3835 case 3: /* MEM, LSMW, HWGP, SBGP */
3836 retval = nds32_parse_group_3_insn(nds32, opcode, address, instruction);
3837 break;
3838 case 4: /* ALU_1, ALU_2, MOVI, SETHI, JI, JREG, BR1, BR2 */
3839 retval = nds32_parse_group_4_insn(nds32, opcode, address, instruction);
3840 break;
3841 case 5: /* ADDI, SUBRI, ANDI, XORI, ORI, SLTI, SLTSI */
3842 retval = nds32_parse_group_5_insn(nds32, opcode, address, instruction);
3843 break;
3844 case 6: /* MISC */
3845 retval = nds32_parse_group_6_insn(nds32, opcode, address, instruction);
3846 break;
3847 default: /* ERROR */
3848 snprintf(instruction->text,
3849 128,
3850 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
3851 address,
3852 opcode);
3853 return ERROR_FAIL;
3854 }
3855 }
3856
3857 return retval;
3858 }
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