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[openocd.git] / src / target / nds32_reg.h
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18 #ifndef __NDS32_REG_H__
19 #define __NDS32_REG_H__
20
21 #define SRIDX(a, b, c) ((a << 7) | (b << 3) | c)
22 #define NDS32_REGISTER_DISABLE (0x0)
23
24 enum nds32_reg_number_s {
25 R0 = 0, /* general registers */
26 R1,
27 R2,
28 R3,
29 R4,
30 R5,
31 R6,
32 R7,
33 R8,
34 R9,
35 R10,
36 R11,
37 R12,
38 R13,
39 R14,
40 R15,
41 R16,
42 R17,
43 R18,
44 R19,
45 R20,
46 R21,
47 R22,
48 R23,
49 R24,
50 R25,
51 R26,
52 R27,
53 R28,
54 R29,
55 R30,
56 R31,
57 PC,
58 D0LO,
59 D0HI,
60 D1LO,
61 D1HI,
62 ITB,
63 IFC_LP,
64 CR0, /* system registers */
65 CR1,
66 CR2,
67 CR3,
68 CR4,
69 CR5,
70 CR6,
71 IR0,
72 IR1,
73 IR2,
74 IR3,
75 IR4,
76 IR5,
77 IR6,
78 IR7,
79 IR8,
80 IR9,
81 IR10,
82 IR11,
83 IR12,
84 IR13,
85 IR14,
86 IR15,
87 IR16,
88 IR17,
89 IR18,
90 IR19,
91 IR20,
92 IR21,
93 IR22,
94 IR23,
95 IR24,
96 IR25,
97 IR26,
98 IR27,
99 IR28,
100 IR29,
101 IR30,
102 MR0,
103 MR1,
104 MR2,
105 MR3,
106 MR4,
107 MR5,
108 MR6,
109 MR7,
110 MR8,
111 MR9,
112 MR10,
113 MR11,
114 DR0,
115 DR1,
116 DR2,
117 DR3,
118 DR4,
119 DR5,
120 DR6,
121 DR7,
122 DR8,
123 DR9,
124 DR10,
125 DR11,
126 DR12,
127 DR13,
128 DR14,
129 DR15,
130 DR16,
131 DR17,
132 DR18,
133 DR19,
134 DR20,
135 DR21,
136 DR22,
137 DR23,
138 DR24,
139 DR25,
140 DR26,
141 DR27,
142 DR28,
143 DR29,
144 DR30,
145 DR31,
146 DR32,
147 DR33,
148 DR34,
149 DR35,
150 DR36,
151 DR37,
152 DR38,
153 DR39,
154 DR40,
155 DR41,
156 DR42,
157 DR43,
158 DR44,
159 DR45,
160 DR46,
161 DR47,
162 DR48,
163 PFR0,
164 PFR1,
165 PFR2,
166 PFR3,
167 DMAR0,
168 DMAR1,
169 DMAR2,
170 DMAR3,
171 DMAR4,
172 DMAR5,
173 DMAR6,
174 DMAR7,
175 DMAR8,
176 DMAR9,
177 DMAR10,
178 RACR,
179 FUCPR,
180 IDR0,
181 IDR1,
182 SECUR0,
183 D0L24, /* audio registers */
184 D1L24,
185 I0,
186 I1,
187 I2,
188 I3,
189 I4,
190 I5,
191 I6,
192 I7,
193 M1,
194 M2,
195 M3,
196 M5,
197 M6,
198 M7,
199 MOD,
200 LBE,
201 LE,
202 LC,
203 ADM_VBASE,
204 SHFT_CTL0,
205 SHFT_CTL1,
206 CB_CTL,
207 CBB0,
208 CBB1,
209 CBB2,
210 CBB3,
211 CBE0,
212 CBE1,
213 CBE2,
214 CBE3,
215 FPCSR, /* fpu */
216 FPCFG,
217 FS0,
218 FS1,
219 FS2,
220 FS3,
221 FS4,
222 FS5,
223 FS6,
224 FS7,
225 FS8,
226 FS9,
227 FS10,
228 FS11,
229 FS12,
230 FS13,
231 FS14,
232 FS15,
233 FS16,
234 FS17,
235 FS18,
236 FS19,
237 FS20,
238 FS21,
239 FS22,
240 FS23,
241 FS24,
242 FS25,
243 FS26,
244 FS27,
245 FS28,
246 FS29,
247 FS30,
248 FS31,
249 FD0,
250 FD1,
251 FD2,
252 FD3,
253 FD4,
254 FD5,
255 FD6,
256 FD7,
257 FD8,
258 FD9,
259 FD10,
260 FD11,
261 FD12,
262 FD13,
263 FD14,
264 FD15,
265 FD16,
266 FD17,
267 FD18,
268 FD19,
269 FD20,
270 FD21,
271 FD22,
272 FD23,
273 FD24,
274 FD25,
275 FD26,
276 FD27,
277 FD28,
278 FD29,
279 FD30,
280 FD31,
281
282 TOTAL_REG_NUM,
283 };
284
285 enum nds32_reg_type_s {
286 NDS32_REG_TYPE_GPR = 0,
287 NDS32_REG_TYPE_SPR,
288 NDS32_REG_TYPE_CR,
289 NDS32_REG_TYPE_IR,
290 NDS32_REG_TYPE_MR,
291 NDS32_REG_TYPE_DR,
292 NDS32_REG_TYPE_PFR,
293 NDS32_REG_TYPE_DMAR,
294 NDS32_REG_TYPE_RACR,
295 NDS32_REG_TYPE_IDR,
296 NDS32_REG_TYPE_AUMR,
297 NDS32_REG_TYPE_SECURE,
298 NDS32_REG_TYPE_FPU,
299 };
300
301 struct nds32_reg_s {
302 const char *simple_mnemonic;
303 const char *symbolic_mnemonic;
304 uint32_t sr_index;
305 enum nds32_reg_type_s type;
306 uint8_t size;
307 };
308
309 struct nds32_reg_exception_s {
310 uint32_t reg_num;
311 uint32_t ex_value_bit_pos;
312 uint32_t ex_value_mask;
313 uint32_t ex_value;
314 };
315
316 void nds32_reg_init(void);
317 uint32_t nds32_reg_sr_index(uint32_t number);
318 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
319 uint8_t nds32_reg_size(uint32_t number);
320 const char *nds32_reg_simple_name(uint32_t number);
321 const char *nds32_reg_symbolic_name(uint32_t number);
322 bool nds32_reg_exception(uint32_t number, uint32_t value);
323
324 #endif
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