src/target/nds32_reg.h

   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes Technology                                   *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_NDS32_REG_H
  20 #define OPENOCD_TARGET_NDS32_REG_H
  21
  22 #define SRIDX(a, b, c)                  ((a << 7) | (b << 3) | c)
  23 #define NDS32_REGISTER_DISABLE          (0x0)
  24
  25 enum nds32_reg_number_s {
  26         R0 = 0, /* general registers */
  27         R1,
  28         R2,
  29         R3,
  30         R4,
  31         R5,
  32         R6,
  33         R7,
  34         R8,
  35         R9,
  36         R10,
  37         R11,
  38         R12,
  39         R13,
  40         R14,
  41         R15,
  42         R16,
  43         R17,
  44         R18,
  45         R19,
  46         R20,
  47         R21,
  48         R22,
  49         R23,
  50         R24,
  51         R25,
  52         R26,
  53         R27,
  54         R28,
  55         R29,
  56         R30,
  57         R31,
  58         PC,
  59         D0LO,
  60         D0HI,
  61         D1LO,
  62         D1HI,
  63         ITB,
  64         IFC_LP,
  65         CR0, /* system registers */
  66         CR1,
  67         CR2,
  68         CR3,
  69         CR4,
  70         CR5,
  71         CR6,
  72         IR0,
  73         IR1,
  74         IR2,
  75         IR3,
  76         IR4,
  77         IR5,
  78         IR6,
  79         IR7,
  80         IR8,
  81         IR9,
  82         IR10,
  83         IR11,
  84         IR12,
  85         IR13,
  86         IR14,
  87         IR15,
  88         IR16,
  89         IR17,
  90         IR18,
  91         IR19,
  92         IR20,
  93         IR21,
  94         IR22,
  95         IR23,
  96         IR24,
  97         IR25,
  98         IR26,
  99         IR27,
 100         IR28,
 101         IR29,
 102         IR30,
 103         MR0,
 104         MR1,
 105         MR2,
 106         MR3,
 107         MR4,
 108         MR5,
 109         MR6,
 110         MR7,
 111         MR8,
 112         MR9,
 113         MR10,
 114         MR11,
 115         DR0,
 116         DR1,
 117         DR2,
 118         DR3,
 119         DR4,
 120         DR5,
 121         DR6,
 122         DR7,
 123         DR8,
 124         DR9,
 125         DR10,
 126         DR11,
 127         DR12,
 128         DR13,
 129         DR14,
 130         DR15,
 131         DR16,
 132         DR17,
 133         DR18,
 134         DR19,
 135         DR20,
 136         DR21,
 137         DR22,
 138         DR23,
 139         DR24,
 140         DR25,
 141         DR26,
 142         DR27,
 143         DR28,
 144         DR29,
 145         DR30,
 146         DR31,
 147         DR32,
 148         DR33,
 149         DR34,
 150         DR35,
 151         DR36,
 152         DR37,
 153         DR38,
 154         DR39,
 155         DR40,
 156         DR41,
 157         DR42,
 158         DR43,
 159         DR44,
 160         DR45,
 161         DR46,
 162         DR47,
 163         DR48,
 164         PFR0,
 165         PFR1,
 166         PFR2,
 167         PFR3,
 168         DMAR0,
 169         DMAR1,
 170         DMAR2,
 171         DMAR3,
 172         DMAR4,
 173         DMAR5,
 174         DMAR6,
 175         DMAR7,
 176         DMAR8,
 177         DMAR9,
 178         DMAR10,
 179         RACR,
 180         FUCPR,
 181         IDR0,
 182         IDR1,
 183         SECUR0,
 184         D0L24, /* audio registers */
 185         D1L24,
 186         I0,
 187         I1,
 188         I2,
 189         I3,
 190         I4,
 191         I5,
 192         I6,
 193         I7,
 194         M1,
 195         M2,
 196         M3,
 197         M5,
 198         M6,
 199         M7,
 200         MOD,
 201         LBE,
 202         LE,
 203         LC,
 204         ADM_VBASE,
 205         SHFT_CTL0,
 206         SHFT_CTL1,
 207         CB_CTL,
 208         CBB0,
 209         CBB1,
 210         CBB2,
 211         CBB3,
 212         CBE0,
 213         CBE1,
 214         CBE2,
 215         CBE3,
 216         FPCSR, /* fpu */
 217         FPCFG,
 218         FS0,
 219         FS1,
 220         FS2,
 221         FS3,
 222         FS4,
 223         FS5,
 224         FS6,
 225         FS7,
 226         FS8,
 227         FS9,
 228         FS10,
 229         FS11,
 230         FS12,
 231         FS13,
 232         FS14,
 233         FS15,
 234         FS16,
 235         FS17,
 236         FS18,
 237         FS19,
 238         FS20,
 239         FS21,
 240         FS22,
 241         FS23,
 242         FS24,
 243         FS25,
 244         FS26,
 245         FS27,
 246         FS28,
 247         FS29,
 248         FS30,
 249         FS31,
 250         FD0,
 251         FD1,
 252         FD2,
 253         FD3,
 254         FD4,
 255         FD5,
 256         FD6,
 257         FD7,
 258         FD8,
 259         FD9,
 260         FD10,
 261         FD11,
 262         FD12,
 263         FD13,
 264         FD14,
 265         FD15,
 266         FD16,
 267         FD17,
 268         FD18,
 269         FD19,
 270         FD20,
 271         FD21,
 272         FD22,
 273         FD23,
 274         FD24,
 275         FD25,
 276         FD26,
 277         FD27,
 278         FD28,
 279         FD29,
 280         FD30,
 281         FD31,
 282
 283         TOTAL_REG_NUM,
 284 };
 285
 286 enum nds32_reg_type_s {
 287         NDS32_REG_TYPE_GPR = 0,
 288         NDS32_REG_TYPE_SPR,
 289         NDS32_REG_TYPE_CR,
 290         NDS32_REG_TYPE_IR,
 291         NDS32_REG_TYPE_MR,
 292         NDS32_REG_TYPE_DR,
 293         NDS32_REG_TYPE_PFR,
 294         NDS32_REG_TYPE_DMAR,
 295         NDS32_REG_TYPE_RACR,
 296         NDS32_REG_TYPE_IDR,
 297         NDS32_REG_TYPE_AUMR,
 298         NDS32_REG_TYPE_SECURE,
 299         NDS32_REG_TYPE_FPU,
 300 };
 301
 302 struct nds32_reg_s {
 303         const char *simple_mnemonic;
 304         const char *symbolic_mnemonic;
 305         uint32_t sr_index;
 306         enum nds32_reg_type_s type;
 307         uint8_t size;
 308 };
 309
 310 struct nds32_reg_exception_s {
 311         uint32_t reg_num;
 312         uint32_t ex_value_bit_pos;
 313         uint32_t ex_value_mask;
 314         uint32_t ex_value;
 315 };
 316
 317 void nds32_reg_init(void);
 318 uint32_t nds32_reg_sr_index(uint32_t number);
 319 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
 320 uint8_t nds32_reg_size(uint32_t number);
 321 const char *nds32_reg_simple_name(uint32_t number);
 322 const char *nds32_reg_symbolic_name(uint32_t number);
 323 bool nds32_reg_exception(uint32_t number, uint32_t value);
 324
 325 #endif /* OPENOCD_TARGET_NDS32_REG_H */