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adi_v5: Remove unused features of the DAP and SWD interfaces
[openocd.git] / src / target / nds32_v3.c
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "breakpoints.h"
26 #include "nds32_cmd.h"
27 #include "nds32_aice.h"
28 #include "nds32_v3.h"
29 #include "nds32_v3_common.h"
30
31 static int nds32_v3_activate_hardware_breakpoint(struct target *target)
32 {
33 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
34 struct aice_port_s *aice = target_to_aice(target);
35 struct breakpoint *bp;
36 int32_t hbr_index = nds32_v3->next_hbr_index;
37
38 for (bp = target->breakpoints; bp; bp = bp->next) {
39 if (bp->type == BKPT_SOFT) {
40 /* already set at nds32_v3_add_breakpoint() */
41 continue;
42 } else if (bp->type == BKPT_HARD) {
43 hbr_index--;
44 /* set address */
45 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
46 /* set mask */
47 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
48 /* set value */
49 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
50
51 if (nds32_v3->nds32.memory.address_translation)
52 /* enable breakpoint (virtual address) */
53 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
54 else
55 /* enable breakpoint (physical address) */
56 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
57
58 LOG_DEBUG("Add hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
59 bp->address);
60 } else {
61 return ERROR_FAIL;
62 }
63 }
64
65 return ERROR_OK;
66 }
67
68 static int nds32_v3_deactivate_hardware_breakpoint(struct target *target)
69 {
70 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
71 struct aice_port_s *aice = target_to_aice(target);
72 struct breakpoint *bp;
73 int32_t hbr_index = nds32_v3->next_hbr_index;
74
75 for (bp = target->breakpoints; bp; bp = bp->next) {
76 if (bp->type == BKPT_SOFT) {
77 continue;
78 } else if (bp->type == BKPT_HARD) {
79 hbr_index--;
80 /* disable breakpoint */
81 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
82 } else {
83 return ERROR_FAIL;
84 }
85
86 LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
87 bp->address);
88 }
89
90 return ERROR_OK;
91 }
92
93 static int nds32_v3_activate_hardware_watchpoint(struct target *target)
94 {
95 struct aice_port_s *aice = target_to_aice(target);
96 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
97 struct watchpoint *wp;
98 int32_t wp_num = 0;
99 uint32_t wp_config = 0;
100 bool ld_stop, st_stop;
101
102 if (nds32_v3->nds32.global_stop)
103 ld_stop = st_stop = false;
104
105 for (wp = target->watchpoints; wp; wp = wp->next) {
106
107 if (wp_num < nds32_v3->used_n_wp) {
108 wp->mask = wp->length - 1;
109 if ((wp->address % wp->length) != 0)
110 wp->mask = (wp->mask << 1) + 1;
111
112 if (wp->rw == WPT_READ)
113 wp_config = 0x3;
114 else if (wp->rw == WPT_WRITE)
115 wp_config = 0x5;
116 else if (wp->rw == WPT_ACCESS)
117 wp_config = 0x7;
118
119 /* set/unset physical address bit of BPCn according to PSW.DT */
120 if (nds32_v3->nds32.memory.address_translation == false)
121 wp_config |= 0x8;
122
123 /* set address */
124 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
125 wp->address - (wp->address % wp->length));
126 /* set mask */
127 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
128 /* enable watchpoint */
129 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
130 /* set value */
131 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
132
133 LOG_DEBUG("Add hardware wathcpoint %" PRId32 " at %08" PRIx32 " mask %08" PRIx32,
134 wp_num, wp->address, wp->mask);
135
136 wp_num++;
137 } else if (nds32_v3->nds32.global_stop) {
138 if (wp->rw == WPT_READ)
139 ld_stop = true;
140 else if (wp->rw == WPT_WRITE)
141 st_stop = true;
142 else if (wp->rw == WPT_ACCESS)
143 ld_stop = st_stop = true;
144 }
145 }
146
147 if (nds32_v3->nds32.global_stop) {
148 uint32_t edm_ctl;
149 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
150 if (ld_stop)
151 edm_ctl |= 0x10;
152 if (st_stop)
153 edm_ctl |= 0x20;
154 aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
155 }
156
157 return ERROR_OK;
158 }
159
160 static int nds32_v3_deactivate_hardware_watchpoint(struct target *target)
161 {
162 struct aice_port_s *aice = target_to_aice(target);
163 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
164 int32_t wp_num = 0;
165 struct watchpoint *wp;
166 bool clean_global_stop = false;
167
168 for (wp = target->watchpoints; wp; wp = wp->next) {
169
170 if (wp_num < nds32_v3->used_n_wp) {
171 /* disable watchpoint */
172 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
173
174 LOG_DEBUG("Remove hardware wathcpoint %" PRId32 " at %08" PRIx32
175 " mask %08" PRIx32, wp_num,
176 wp->address, wp->mask);
177 wp_num++;
178 } else if (nds32_v3->nds32.global_stop) {
179 clean_global_stop = true;
180 }
181 }
182
183 if (clean_global_stop) {
184 uint32_t edm_ctl;
185 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
186 edm_ctl = edm_ctl & (~0x30);
187 aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
188 }
189
190 return ERROR_OK;
191 }
192
193 static int nds32_v3_check_interrupt_stack(struct nds32 *nds32)
194 {
195 uint32_t val_ir0;
196 uint32_t value;
197
198 /* Save interrupt level */
199 nds32_get_mapped_reg(nds32, IR0, &val_ir0);
200 nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
201
202 if (nds32_reach_max_interrupt_level(nds32))
203 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->",
204 nds32->current_interrupt_level);
205
206 /* backup $ir4 & $ir6 to avoid suppressed exception overwrite */
207 nds32_get_mapped_reg(nds32, IR4, &value);
208 nds32_get_mapped_reg(nds32, IR6, &value);
209
210 return ERROR_OK;
211 }
212
213 static int nds32_v3_restore_interrupt_stack(struct nds32 *nds32)
214 {
215 uint32_t value;
216
217 /* get backup value from cache */
218 /* then set back to make the register dirty */
219 nds32_get_mapped_reg(nds32, IR0, &value);
220 nds32_set_mapped_reg(nds32, IR0, value);
221
222 nds32_get_mapped_reg(nds32, IR4, &value);
223 nds32_set_mapped_reg(nds32, IR4, value);
224
225 nds32_get_mapped_reg(nds32, IR6, &value);
226 nds32_set_mapped_reg(nds32, IR6, value);
227
228 return ERROR_OK;
229 }
230
231 static int nds32_v3_deassert_reset(struct target *target)
232 {
233 int retval;
234 struct aice_port_s *aice = target_to_aice(target);
235 bool switch_to_v3_stack = false;
236 uint32_t value_edm_ctl;
237
238 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
239 if (((value_edm_ctl >> 6) & 0x1) == 0) { /* reset to V2 EDM mode */
240 aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, value_edm_ctl | (0x1 << 6));
241 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
242 if (((value_edm_ctl >> 6) & 0x1) == 1)
243 switch_to_v3_stack = true;
244 } else
245 switch_to_v3_stack = false;
246
247 CHECK_RETVAL(nds32_poll(target));
248
249 if (target->state != TARGET_HALTED) {
250 /* reset only */
251 LOG_WARNING("%s: ran after reset and before halt ...",
252 target_name(target));
253 retval = target_halt(target);
254 if (retval != ERROR_OK)
255 return retval;
256
257 } else {
258 /* reset-halt */
259 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
260 struct nds32 *nds32 = &(nds32_v3->nds32);
261 uint32_t value;
262 uint32_t interrupt_level;
263
264 if (switch_to_v3_stack == true) {
265 /* PSW.INTL-- */
266 nds32_get_mapped_reg(nds32, IR0, &value);
267 interrupt_level = (value >> 1) & 0x3;
268 interrupt_level--;
269 value &= ~(0x6);
270 value |= (interrupt_level << 1);
271 value |= 0x400; /* set PSW.DEX */
272 nds32_set_mapped_reg(nds32, IR0, value);
273
274 /* copy IPC to OIPC */
275 if ((interrupt_level + 1) < nds32->max_interrupt_level) {
276 nds32_get_mapped_reg(nds32, IR9, &value);
277 nds32_set_mapped_reg(nds32, IR11, value);
278 }
279 }
280 }
281
282 return ERROR_OK;
283 }
284
285 static int nds32_v3_add_breakpoint(struct target *target,
286 struct breakpoint *breakpoint)
287 {
288 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
289 struct nds32 *nds32 = &(nds32_v3->nds32);
290 int result;
291
292 if (breakpoint->type == BKPT_HARD) {
293 /* check hardware resource */
294 if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
295 LOG_WARNING("<-- TARGET WARNING! Insert too many "
296 "hardware breakpoints/watchpoints! "
297 "The limit of combined hardware "
298 "breakpoints/watchpoints is %" PRId32 ". -->",
299 nds32_v3->n_hbr);
300 LOG_WARNING("<-- TARGET STATUS: Inserted number of "
301 "hardware breakpoint: %" PRId32 ", hardware "
302 "watchpoints: %" PRId32 ". -->",
303 nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
304 nds32_v3->used_n_wp);
305 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
306 }
307
308 /* update next place to put hardware breakpoint */
309 nds32_v3->next_hbr_index++;
310
311 /* hardware breakpoint insertion occurs before 'continue' actually */
312 return ERROR_OK;
313 } else if (breakpoint->type == BKPT_SOFT) {
314 result = nds32_add_software_breakpoint(target, breakpoint);
315 if (ERROR_OK != result) {
316 /* auto convert to hardware breakpoint if failed */
317 if (nds32->auto_convert_hw_bp) {
318 /* convert to hardware breakpoint */
319 breakpoint->type = BKPT_HARD;
320
321 return nds32_v3_add_breakpoint(target, breakpoint);
322 }
323 }
324
325 return result;
326 } else /* unrecognized breakpoint type */
327 return ERROR_FAIL;
328
329 return ERROR_OK;
330 }
331
332 static int nds32_v3_remove_breakpoint(struct target *target,
333 struct breakpoint *breakpoint)
334 {
335 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
336
337 if (breakpoint->type == BKPT_HARD) {
338 if (nds32_v3->next_hbr_index <= 0)
339 return ERROR_FAIL;
340
341 /* update next place to put hardware breakpoint */
342 nds32_v3->next_hbr_index--;
343
344 /* hardware breakpoint removal occurs after 'halted' actually */
345 return ERROR_OK;
346 } else if (breakpoint->type == BKPT_SOFT) {
347 return nds32_remove_software_breakpoint(target, breakpoint);
348 } else /* unrecognized breakpoint type */
349 return ERROR_FAIL;
350
351 return ERROR_OK;
352 }
353
354 static int nds32_v3_add_watchpoint(struct target *target,
355 struct watchpoint *watchpoint)
356 {
357 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
358
359 /* check hardware resource */
360 if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
361 /* No hardware resource */
362 if (nds32_v3->nds32.global_stop) {
363 LOG_WARNING("<-- TARGET WARNING! The number of "
364 "watchpoints exceeds the hardware "
365 "resources. Stop at every load/store "
366 "instruction to check for watchpoint matches. -->");
367 return ERROR_OK;
368 }
369
370 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
371 "breakpoints/watchpoints! The limit of combined "
372 "hardware breakpoints/watchpoints is %" PRId32 ". -->",
373 nds32_v3->n_hbr);
374 LOG_WARNING("<-- TARGET STATUS: Inserted number of "
375 "hardware breakpoint: %" PRId32 ", hardware "
376 "watchpoints: %" PRId32 ". -->",
377 nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
378 nds32_v3->used_n_wp);
379
380 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
381 }
382
383 /* update next place to put hardware watchpoint */
384 nds32_v3->next_hbr_index++;
385 nds32_v3->used_n_wp++;
386
387 return ERROR_OK;
388 }
389
390 static int nds32_v3_remove_watchpoint(struct target *target,
391 struct watchpoint *watchpoint)
392 {
393 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
394
395 if (nds32_v3->next_hbr_index <= 0) {
396 if (nds32_v3->nds32.global_stop)
397 return ERROR_OK;
398
399 return ERROR_FAIL;
400 }
401
402 /* update next place to put hardware breakpoint */
403 nds32_v3->next_hbr_index--;
404 nds32_v3->used_n_wp--;
405
406 return ERROR_OK;
407 }
408
409 struct nds32_v3_common_callback nds32_v3_common_callback = {
410 .check_interrupt_stack = nds32_v3_check_interrupt_stack,
411 .restore_interrupt_stack = nds32_v3_restore_interrupt_stack,
412 .activate_hardware_breakpoint = nds32_v3_activate_hardware_breakpoint,
413 .activate_hardware_watchpoint = nds32_v3_activate_hardware_watchpoint,
414 .deactivate_hardware_breakpoint = nds32_v3_deactivate_hardware_breakpoint,
415 .deactivate_hardware_watchpoint = nds32_v3_deactivate_hardware_watchpoint,
416 };
417
418 static int nds32_v3_target_create(struct target *target, Jim_Interp *interp)
419 {
420 struct nds32_v3_common *nds32_v3;
421
422 nds32_v3 = calloc(1, sizeof(*nds32_v3));
423 if (!nds32_v3)
424 return ERROR_FAIL;
425
426 nds32_v3_common_register_callback(&nds32_v3_common_callback);
427 nds32_v3_target_create_common(target, &(nds32_v3->nds32));
428
429 return ERROR_OK;
430 }
431
432 /* talk to the target and set things up */
433 static int nds32_v3_examine(struct target *target)
434 {
435 struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
436 struct nds32 *nds32 = &(nds32_v3->nds32);
437 struct aice_port_s *aice = target_to_aice(target);
438
439 if (!target_was_examined(target)) {
440 CHECK_RETVAL(nds32_edm_config(nds32));
441
442 if (nds32->reset_halt_as_examine)
443 CHECK_RETVAL(nds32_reset_halt(nds32));
444 }
445
446 uint32_t edm_cfg;
447 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
448
449 /* get the number of hardware breakpoints */
450 nds32_v3->n_hbr = (edm_cfg & 0x7) + 1;
451
452 /* low interference profiling */
453 if (edm_cfg & 0x100)
454 nds32_v3->low_interference_profile = true;
455 else
456 nds32_v3->low_interference_profile = false;
457
458 nds32_v3->next_hbr_index = 0;
459 nds32_v3->used_n_wp = 0;
460
461 LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target),
462 nds32_v3->n_hbr);
463
464 nds32->target->state = TARGET_RUNNING;
465 nds32->target->debug_reason = DBG_REASON_NOTHALTED;
466
467 target_set_examined(target);
468
469 return ERROR_OK;
470 }
471
472 /** Holds methods for Andes1337 targets. */
473 struct target_type nds32_v3_target = {
474 .name = "nds32_v3",
475
476 .poll = nds32_poll,
477 .arch_state = nds32_arch_state,
478
479 .target_request_data = nds32_v3_target_request_data,
480
481 .halt = nds32_halt,
482 .resume = nds32_resume,
483 .step = nds32_step,
484
485 .assert_reset = nds32_assert_reset,
486 .deassert_reset = nds32_v3_deassert_reset,
487
488 /* register access */
489 .get_gdb_reg_list = nds32_get_gdb_reg_list,
490
491 /* memory access */
492 .read_buffer = nds32_v3_read_buffer,
493 .write_buffer = nds32_v3_write_buffer,
494 .read_memory = nds32_v3_read_memory,
495 .write_memory = nds32_v3_write_memory,
496
497 .checksum_memory = nds32_v3_checksum_memory,
498
499 /* breakpoint/watchpoint */
500 .add_breakpoint = nds32_v3_add_breakpoint,
501 .remove_breakpoint = nds32_v3_remove_breakpoint,
502 .add_watchpoint = nds32_v3_add_watchpoint,
503 .remove_watchpoint = nds32_v3_remove_watchpoint,
504 .hit_watchpoint = nds32_v3_hit_watchpoint,
505
506 /* MMU */
507 .mmu = nds32_mmu,
508 .virt2phys = nds32_virtual_to_physical,
509 .read_phys_memory = nds32_read_phys_memory,
510 .write_phys_memory = nds32_write_phys_memory,
511
512 .run_algorithm = nds32_v3_run_algorithm,
513
514 .commands = nds32_command_handlers,
515 .target_create = nds32_v3_target_create,
516 .init_target = nds32_v3_init_target,
517 .examine = nds32_v3_examine,
518
519 .get_gdb_fileio_info = nds32_get_gdb_fileio_info,
520 .gdb_fileio_end = nds32_gdb_fileio_end,
521
522 .profiling = nds32_profiling,
523 };
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