src/target/riscv/program.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef TARGET__RISCV__PROGRAM_H
   4 #define TARGET__RISCV__PROGRAM_H
   5
   6 #include "riscv.h"
   7
   8 #define RISCV_MAX_DEBUG_BUFFER_SIZE 32
   9 #define RISCV_REGISTER_COUNT 32
  10 #define RISCV_DSCRATCH_COUNT 2
  11
  12 /* The various RISC-V debug specifications all revolve around setting up
  13  * program buffers and executing them on the target.  This structure contains a
  14  * single program, which can then be executed on targets.  */
  15 struct riscv_program {
  16         struct target *target;
  17
  18         uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE];
  19
  20         /* Number of 32-bit instructions in the program. */
  21         size_t instruction_count;
  22
  23         /* Side effects of executing this program.  These must be accounted for
  24          * in order to maintain correct executing of the target system.  */
  25         bool writes_xreg[RISCV_REGISTER_COUNT];
  26
  27         /* XLEN on the target. */
  28         int target_xlen;
  29 };
  30
  31 /* Initializes a program with the header. */
  32 int riscv_program_init(struct riscv_program *p, struct target *t);
  33
  34 /* Write the program to the program buffer. */
  35 int riscv_program_write(struct riscv_program *program);
  36
  37 /* Executes a program, returning 0 if the program successfully executed.  Note
  38  * that this may cause registers to be saved or restored, which could result to
  39  * calls to things like riscv_save_register which itself could require a
  40  * program to execute.  That's OK, just make sure this eventually terminates.
  41  * */
  42 int riscv_program_exec(struct riscv_program *p, struct target *t);
  43
  44 /* A lower level interface, you shouldn't use this unless you have a reason. */
  45 int riscv_program_insert(struct riscv_program *p, riscv_insn_t i);
  46
  47 /* Helpers to assemble various instructions.  Return 0 on success.  These might
  48  * assemble into a multi-instruction sequence that overwrites some other
  49  * register, but those will be properly saved and restored. */
  50 int riscv_program_ldr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
  51 int riscv_program_lwr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
  52 int riscv_program_lhr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
  53 int riscv_program_lbr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno a, int o);
  54
  55 int riscv_program_sdr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
  56 int riscv_program_swr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
  57 int riscv_program_shr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
  58 int riscv_program_sbr(struct riscv_program *p, enum gdb_regno s, enum gdb_regno a, int o);
  59
  60 int riscv_program_csrrsi(struct riscv_program *p, enum gdb_regno d, unsigned int z, enum gdb_regno csr);
  61 int riscv_program_csrrci(struct riscv_program *p, enum gdb_regno d, unsigned int z, enum gdb_regno csr);
  62 int riscv_program_csrr(struct riscv_program *p, enum gdb_regno d, enum gdb_regno csr);
  63 int riscv_program_csrw(struct riscv_program *p, enum gdb_regno s, enum gdb_regno csr);
  64
  65 int riscv_program_fence_i(struct riscv_program *p);
  66 int riscv_program_fence(struct riscv_program *p);
  67 int riscv_program_ebreak(struct riscv_program *p);
  68
  69 int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
  70
  71 #endif