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[openocd.git] / src / target / riscv / riscv-011.c
1 /*
2 * Support for RISC-V, debug version 0.11. This was never an officially adopted
3 * spec, but SiFive made some silicon that uses it.
4 */
5
6 #include <assert.h>
7 #include <stdlib.h>
8 #include <time.h>
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "target/target.h"
15 #include "target/algorithm.h"
16 #include "target/target_type.h"
17 #include "log.h"
18 #include "jtag/jtag.h"
19 #include "target/register.h"
20 #include "target/breakpoints.h"
21 #include "helper/time_support.h"
22 #include "riscv.h"
23 #include "asm.h"
24 #include "gdb_regs.h"
25
26 /**
27 * Since almost everything can be accomplish by scanning the dbus register, all
28 * functions here assume dbus is already selected. The exception are functions
29 * called directly by OpenOCD, which can't assume anything about what's
30 * currently in IR. They should set IR to dbus explicitly.
31 */
32
33 /**
34 * Code structure
35 *
36 * At the bottom of the stack are the OpenOCD JTAG functions:
37 * jtag_add_[id]r_scan
38 * jtag_execute_query
39 * jtag_add_runtest
40 *
41 * There are a few functions to just instantly shift a register and get its
42 * value:
43 * dtmcontrol_scan
44 * idcode_scan
45 * dbus_scan
46 *
47 * Because doing one scan and waiting for the result is slow, most functions
48 * batch up a bunch of dbus writes and then execute them all at once. They use
49 * the scans "class" for this:
50 * scans_new
51 * scans_delete
52 * scans_execute
53 * scans_add_...
54 * Usually you new(), call a bunch of add functions, then execute() and look
55 * at the results by calling scans_get...()
56 *
57 * Optimized functions will directly use the scans class above, but slightly
58 * lazier code will use the cache functions that in turn use the scans
59 * functions:
60 * cache_get...
61 * cache_set...
62 * cache_write
63 * cache_set... update a local structure, which is then synced to the target
64 * with cache_write(). Only Debug RAM words that are actually changed are sent
65 * to the target. Afterwards use cache_get... to read results.
66 */
67
68 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
69 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
70
71 #define DIM(x) (sizeof(x)/sizeof(*x))
72
73 /* Constants for legacy SiFive hardware breakpoints. */
74 #define CSR_BPCONTROL_X (1<<0)
75 #define CSR_BPCONTROL_W (1<<1)
76 #define CSR_BPCONTROL_R (1<<2)
77 #define CSR_BPCONTROL_U (1<<3)
78 #define CSR_BPCONTROL_S (1<<4)
79 #define CSR_BPCONTROL_H (1<<5)
80 #define CSR_BPCONTROL_M (1<<6)
81 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
82 #define CSR_BPCONTROL_BPACTION (0xff<<11)
83
84 #define DEBUG_ROM_START 0x800
85 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
86 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
87 #define DEBUG_RAM_START 0x400
88
89 #define SETHALTNOT 0x10c
90
91 /*** JTAG registers. ***/
92
93 #define DTMCONTROL 0x10
94 #define DTMCONTROL_DBUS_RESET (1<<16)
95 #define DTMCONTROL_IDLE (7<<10)
96 #define DTMCONTROL_ADDRBITS (0xf<<4)
97 #define DTMCONTROL_VERSION (0xf)
98
99 #define DBUS 0x11
100 #define DBUS_OP_START 0
101 #define DBUS_OP_SIZE 2
102 typedef enum {
103 DBUS_OP_NOP = 0,
104 DBUS_OP_READ = 1,
105 DBUS_OP_WRITE = 2
106 } dbus_op_t;
107 typedef enum {
108 DBUS_STATUS_SUCCESS = 0,
109 DBUS_STATUS_FAILED = 2,
110 DBUS_STATUS_BUSY = 3
111 } dbus_status_t;
112 #define DBUS_DATA_START 2
113 #define DBUS_DATA_SIZE 34
114 #define DBUS_ADDRESS_START 36
115
116 typedef enum {
117 RE_OK,
118 RE_FAIL,
119 RE_AGAIN
120 } riscv_error_t;
121
122 typedef enum slot {
123 SLOT0,
124 SLOT1,
125 SLOT_LAST,
126 } slot_t;
127
128 /*** Debug Bus registers. ***/
129
130 #define DMCONTROL 0x10
131 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
132 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
133 #define DMCONTROL_BUSERROR (7<<19)
134 #define DMCONTROL_SERIAL (3<<16)
135 #define DMCONTROL_AUTOINCREMENT (1<<15)
136 #define DMCONTROL_ACCESS (7<<12)
137 #define DMCONTROL_HARTID (0x3ff<<2)
138 #define DMCONTROL_NDRESET (1<<1)
139 #define DMCONTROL_FULLRESET 1
140
141 #define DMINFO 0x11
142 #define DMINFO_ABUSSIZE (0x7fU<<25)
143 #define DMINFO_SERIALCOUNT (0xf<<21)
144 #define DMINFO_ACCESS128 (1<<20)
145 #define DMINFO_ACCESS64 (1<<19)
146 #define DMINFO_ACCESS32 (1<<18)
147 #define DMINFO_ACCESS16 (1<<17)
148 #define DMINFO_ACCESS8 (1<<16)
149 #define DMINFO_DRAMSIZE (0x3f<<10)
150 #define DMINFO_AUTHENTICATED (1<<5)
151 #define DMINFO_AUTHBUSY (1<<4)
152 #define DMINFO_AUTHTYPE (3<<2)
153 #define DMINFO_VERSION 3
154
155 /*** Info about the core being debugged. ***/
156
157 #define DBUS_ADDRESS_UNKNOWN 0xffff
158
159 #define DRAM_CACHE_SIZE 16
160
161 struct trigger {
162 uint64_t address;
163 uint32_t length;
164 uint64_t mask;
165 uint64_t value;
166 bool read, write, execute;
167 int unique_id;
168 };
169
170 struct memory_cache_line {
171 uint32_t data;
172 bool valid;
173 bool dirty;
174 };
175
176 typedef struct {
177 /* Number of address bits in the dbus register. */
178 uint8_t addrbits;
179 /* Number of words in Debug RAM. */
180 unsigned int dramsize;
181 uint64_t dcsr;
182 uint64_t dpc;
183 uint64_t tselect;
184 bool tselect_dirty;
185 /* The value that mstatus actually has on the target right now. This is not
186 * the value we present to the user. That one may be stored in the
187 * reg_cache. */
188 uint64_t mstatus_actual;
189
190 struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
191
192 /* Number of run-test/idle cycles the target requests we do after each dbus
193 * access. */
194 unsigned int dtmcontrol_idle;
195
196 /* This value is incremented every time a dbus access comes back as "busy".
197 * It's used to determine how many run-test/idle cycles to feed the target
198 * in between accesses. */
199 unsigned int dbus_busy_delay;
200
201 /* This value is incremented every time we read the debug interrupt as
202 * high. It's used to add extra run-test/idle cycles after setting debug
203 * interrupt high, so ideally we never have to perform a whole extra scan
204 * before the interrupt is cleared. */
205 unsigned int interrupt_high_delay;
206
207 bool need_strict_step;
208 bool never_halted;
209 } riscv011_info_t;
210
211 typedef struct {
212 bool haltnot;
213 bool interrupt;
214 } bits_t;
215
216 /*** Necessary prototypes. ***/
217
218 static int poll_target(struct target *target, bool announce);
219 static int riscv011_poll(struct target *target);
220 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
221 int regid);
222
223 /*** Utility functions. ***/
224
225 #define DEBUG_LENGTH 264
226
227 static riscv011_info_t *get_info(const struct target *target)
228 {
229 riscv_info_t *info = (riscv_info_t *) target->arch_info;
230 return (riscv011_info_t *) info->version_specific;
231 }
232
233 static unsigned int slot_offset(const struct target *target, slot_t slot)
234 {
235 riscv011_info_t *info = get_info(target);
236 switch (riscv_xlen(target)) {
237 case 32:
238 switch (slot) {
239 case SLOT0: return 4;
240 case SLOT1: return 5;
241 case SLOT_LAST: return info->dramsize-1;
242 }
243 break;
244 case 64:
245 switch (slot) {
246 case SLOT0: return 4;
247 case SLOT1: return 6;
248 case SLOT_LAST: return info->dramsize-2;
249 }
250 }
251 LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
252 riscv_xlen(target), slot);
253 assert(0);
254 return 0; /* Silence -Werror=return-type */
255 }
256
257 static uint32_t load_slot(const struct target *target, unsigned int dest,
258 slot_t slot)
259 {
260 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
261 return load(target, dest, ZERO, offset);
262 }
263
264 static uint32_t store_slot(const struct target *target, unsigned int src,
265 slot_t slot)
266 {
267 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
268 return store(target, src, ZERO, offset);
269 }
270
271 static uint16_t dram_address(unsigned int index)
272 {
273 if (index < 0x10)
274 return index;
275 else
276 return 0x40 + index - 0x10;
277 }
278
279 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
280 {
281 struct scan_field field;
282 uint8_t in_value[4];
283 uint8_t out_value[4];
284
285 buf_set_u32(out_value, 0, 32, out);
286
287 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
288
289 field.num_bits = 32;
290 field.out_value = out_value;
291 field.in_value = in_value;
292 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
293
294 /* Always return to dbus. */
295 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
296
297 int retval = jtag_execute_queue();
298 if (retval != ERROR_OK) {
299 LOG_ERROR("failed jtag scan: %d", retval);
300 return retval;
301 }
302
303 uint32_t in = buf_get_u32(field.in_value, 0, 32);
304 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
305
306 return in;
307 }
308
309 static uint32_t idcode_scan(struct target *target)
310 {
311 struct scan_field field;
312 uint8_t in_value[4];
313
314 jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
315
316 field.num_bits = 32;
317 field.out_value = NULL;
318 field.in_value = in_value;
319 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
320
321 int retval = jtag_execute_queue();
322 if (retval != ERROR_OK) {
323 LOG_ERROR("failed jtag scan: %d", retval);
324 return retval;
325 }
326
327 /* Always return to dbus. */
328 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
329
330 uint32_t in = buf_get_u32(field.in_value, 0, 32);
331 LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
332
333 return in;
334 }
335
336 static void increase_dbus_busy_delay(struct target *target)
337 {
338 riscv011_info_t *info = get_info(target);
339 info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
340 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
341 info->dtmcontrol_idle, info->dbus_busy_delay,
342 info->interrupt_high_delay);
343
344 dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
345 }
346
347 static void increase_interrupt_high_delay(struct target *target)
348 {
349 riscv011_info_t *info = get_info(target);
350 info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
351 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
352 info->dtmcontrol_idle, info->dbus_busy_delay,
353 info->interrupt_high_delay);
354 }
355
356 static void add_dbus_scan(const struct target *target, struct scan_field *field,
357 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
358 uint16_t address, uint64_t data)
359 {
360 riscv011_info_t *info = get_info(target);
361
362 field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
363 field->in_value = in_value;
364 field->out_value = out_value;
365
366 buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
367 buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
368 buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
369
370 jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
371
372 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
373 if (data & DMCONTROL_INTERRUPT)
374 idle_count += info->interrupt_high_delay;
375
376 if (idle_count)
377 jtag_add_runtest(idle_count, TAP_IDLE);
378 }
379
380 static void dump_field(const struct scan_field *field)
381 {
382 static const char * const op_string[] = {"nop", "r", "w", "?"};
383 static const char * const status_string[] = {"+", "?", "F", "b"};
384
385 if (debug_level < LOG_LVL_DEBUG)
386 return;
387
388 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
389 unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
390 char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
391 char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
392 unsigned int out_data = out >> 2;
393 unsigned int out_address = out >> DBUS_ADDRESS_START;
394 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
395 unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
396 char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
397 char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
398 unsigned int in_data = in >> 2;
399 unsigned int in_address = in >> DBUS_ADDRESS_START;
400
401 log_printf_lf(LOG_LVL_DEBUG,
402 __FILE__, __LINE__, "scan",
403 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
404 field->num_bits,
405 op_string[out_op], out_interrupt, out_haltnot, out_data,
406 out_address,
407 status_string[in_op], in_interrupt, in_haltnot, in_data,
408 in_address);
409 }
410
411 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
412 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
413 {
414 riscv011_info_t *info = get_info(target);
415 uint8_t in[8] = {0};
416 uint8_t out[8];
417 struct scan_field field = {
418 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
419 .out_value = out,
420 .in_value = in
421 };
422
423 assert(info->addrbits != 0);
424
425 buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
426 buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
427 buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
428
429 /* Assume dbus is already selected. */
430 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
431
432 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
433
434 if (idle_count)
435 jtag_add_runtest(idle_count, TAP_IDLE);
436
437 int retval = jtag_execute_queue();
438 if (retval != ERROR_OK) {
439 LOG_ERROR("dbus_scan failed jtag scan");
440 return DBUS_STATUS_FAILED;
441 }
442
443 if (data_in)
444 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
445
446 if (address_in)
447 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
448
449 dump_field(&field);
450
451 return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
452 }
453
454 static uint64_t dbus_read(struct target *target, uint16_t address)
455 {
456 uint64_t value;
457 dbus_status_t status;
458 uint16_t address_in;
459
460 /* If the previous read/write was to the same address, we will get the read data
461 * from the previous access.
462 * While somewhat nonintuitive, this is an efficient way to get the data.
463 */
464
465 unsigned i = 0;
466 do {
467 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
468 if (status == DBUS_STATUS_BUSY)
469 increase_dbus_busy_delay(target);
470 if (status == DBUS_STATUS_FAILED) {
471 LOG_ERROR("dbus_read(0x%x) failed!", address);
472 return 0;
473 }
474 } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
475 i++ < 256);
476
477 if (status != DBUS_STATUS_SUCCESS)
478 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
479
480 return value;
481 }
482
483 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
484 {
485 dbus_status_t status = DBUS_STATUS_BUSY;
486 unsigned i = 0;
487 while (status == DBUS_STATUS_BUSY && i++ < 256) {
488 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
489 if (status == DBUS_STATUS_BUSY)
490 increase_dbus_busy_delay(target);
491 }
492 if (status != DBUS_STATUS_SUCCESS)
493 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
494 }
495
496 /*** scans "class" ***/
497
498 typedef struct {
499 /* Number of scans that space is reserved for. */
500 unsigned int scan_count;
501 /* Size reserved in memory for each scan, in bytes. */
502 unsigned int scan_size;
503 unsigned int next_scan;
504 uint8_t *in;
505 uint8_t *out;
506 struct scan_field *field;
507 const struct target *target;
508 } scans_t;
509
510 static scans_t *scans_new(struct target *target, unsigned int scan_count)
511 {
512 scans_t *scans = malloc(sizeof(scans_t));
513 scans->scan_count = scan_count;
514 /* This code also gets called before xlen is detected. */
515 if (riscv_xlen(target))
516 scans->scan_size = 2 + riscv_xlen(target) / 8;
517 else
518 scans->scan_size = 2 + 128 / 8;
519 scans->next_scan = 0;
520 scans->in = calloc(scans->scan_size, scans->scan_count);
521 scans->out = calloc(scans->scan_size, scans->scan_count);
522 scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
523 scans->target = target;
524 return scans;
525 }
526
527 static scans_t *scans_delete(scans_t *scans)
528 {
529 assert(scans);
530 free(scans->field);
531 free(scans->out);
532 free(scans->in);
533 free(scans);
534 return NULL;
535 }
536
537 static void scans_reset(scans_t *scans)
538 {
539 scans->next_scan = 0;
540 }
541
542 static void scans_dump(scans_t *scans)
543 {
544 for (unsigned int i = 0; i < scans->next_scan; i++)
545 dump_field(&scans->field[i]);
546 }
547
548 static int scans_execute(scans_t *scans)
549 {
550 int retval = jtag_execute_queue();
551 if (retval != ERROR_OK) {
552 LOG_ERROR("failed jtag scan: %d", retval);
553 return retval;
554 }
555
556 scans_dump(scans);
557
558 return ERROR_OK;
559 }
560
561 /** Add a 32-bit dbus write to the scans structure. */
562 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
563 bool set_interrupt)
564 {
565 const unsigned int i = scans->next_scan;
566 int data_offset = scans->scan_size * i;
567 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
568 scans->in + data_offset, DBUS_OP_WRITE, address,
569 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
570 scans->next_scan++;
571 assert(scans->next_scan <= scans->scan_count);
572 }
573
574 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
575 * debug RAM. */
576 static void scans_add_write_jump(scans_t *scans, uint16_t address,
577 bool set_interrupt)
578 {
579 scans_add_write32(scans, address,
580 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
581 set_interrupt);
582 }
583
584 /** Add a 32-bit dbus write for an instruction that loads from the indicated
585 * slot. */
586 static void scans_add_write_load(scans_t *scans, uint16_t address,
587 unsigned int reg, slot_t slot, bool set_interrupt)
588 {
589 scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
590 set_interrupt);
591 }
592
593 /** Add a 32-bit dbus write for an instruction that stores to the indicated
594 * slot. */
595 static void scans_add_write_store(scans_t *scans, uint16_t address,
596 unsigned int reg, slot_t slot, bool set_interrupt)
597 {
598 scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
599 set_interrupt);
600 }
601
602 /** Add a 32-bit dbus read. */
603 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
604 {
605 assert(scans->next_scan < scans->scan_count);
606 const unsigned int i = scans->next_scan;
607 int data_offset = scans->scan_size * i;
608 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
609 scans->in + data_offset, DBUS_OP_READ, address,
610 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
611 scans->next_scan++;
612 }
613
614 /** Add one or more scans to read the indicated slot. */
615 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
616 {
617 const struct target *target = scans->target;
618 switch (riscv_xlen(target)) {
619 case 32:
620 scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
621 break;
622 case 64:
623 scans_add_read32(scans, slot_offset(target, slot), false);
624 scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
625 break;
626 }
627 }
628
629 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
630 unsigned first, unsigned num)
631 {
632 return buf_get_u32(scans->in + scans->scan_size * index, first, num);
633 }
634
635 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
636 unsigned first, unsigned num)
637 {
638 return buf_get_u64(scans->in + scans->scan_size * index, first, num);
639 }
640
641 /*** end of scans class ***/
642
643 static uint32_t dram_read32(struct target *target, unsigned int index)
644 {
645 uint16_t address = dram_address(index);
646 uint32_t value = dbus_read(target, address);
647 return value;
648 }
649
650 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
651 bool set_interrupt)
652 {
653 uint64_t dbus_value = DMCONTROL_HALTNOT | value;
654 if (set_interrupt)
655 dbus_value |= DMCONTROL_INTERRUPT;
656 dbus_write(target, dram_address(index), dbus_value);
657 }
658
659 /** Read the haltnot and interrupt bits. */
660 static bits_t read_bits(struct target *target)
661 {
662 uint64_t value;
663 dbus_status_t status;
664 uint16_t address_in;
665 riscv011_info_t *info = get_info(target);
666
667 bits_t err_result = {
668 .haltnot = 0,
669 .interrupt = 0
670 };
671
672 do {
673 unsigned i = 0;
674 do {
675 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
676 if (status == DBUS_STATUS_BUSY) {
677 if (address_in == (1<<info->addrbits) - 1 &&
678 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
679 LOG_ERROR("TDO seems to be stuck high.");
680 return err_result;
681 }
682 increase_dbus_busy_delay(target);
683 } else if (status == DBUS_STATUS_FAILED) {
684 /* TODO: return an actual error */
685 return err_result;
686 }
687 } while (status == DBUS_STATUS_BUSY && i++ < 256);
688
689 if (i >= 256) {
690 LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
691 return err_result;
692 }
693 } while (address_in > 0x10 && address_in != DMCONTROL);
694
695 bits_t result = {
696 .haltnot = get_field(value, DMCONTROL_HALTNOT),
697 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
698 };
699 return result;
700 }
701
702 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
703 {
704 time_t start = time(NULL);
705 if (ignore_first) {
706 /* Throw away the results of the first read, since they'll contain the
707 * result of the read that happened just before debugint was set.
708 * (Assuming the last scan before calling this function was one that
709 * sets debugint.) */
710 read_bits(target);
711 }
712 while (1) {
713 bits_t bits = read_bits(target);
714 if (!bits.interrupt)
715 return ERROR_OK;
716 if (time(NULL) - start > riscv_command_timeout_sec) {
717 LOG_ERROR("Timed out waiting for debug int to clear."
718 "Increase timeout with riscv set_command_timeout_sec.");
719 return ERROR_FAIL;
720 }
721 }
722 }
723
724 static int dram_check32(struct target *target, unsigned int index,
725 uint32_t expected)
726 {
727 uint16_t address = dram_address(index);
728 uint32_t actual = dbus_read(target, address);
729 if (expected != actual) {
730 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
731 expected, index, actual);
732 return ERROR_FAIL;
733 }
734 return ERROR_OK;
735 }
736
737 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
738 {
739 riscv011_info_t *info = get_info(target);
740 if (info->dram_cache[index].valid &&
741 info->dram_cache[index].data == data) {
742 /* This is already preset on the target. */
743 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
744 return;
745 }
746 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
747 info->dram_cache[index].data = data;
748 info->dram_cache[index].valid = true;
749 info->dram_cache[index].dirty = true;
750 }
751
752 static void cache_set(struct target *target, slot_t slot, uint64_t data)
753 {
754 unsigned int offset = slot_offset(target, slot);
755 cache_set32(target, offset, data);
756 if (riscv_xlen(target) > 32)
757 cache_set32(target, offset + 1, data >> 32);
758 }
759
760 static void cache_set_jump(struct target *target, unsigned int index)
761 {
762 cache_set32(target, index,
763 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
764 }
765
766 static void cache_set_load(struct target *target, unsigned int index,
767 unsigned int reg, slot_t slot)
768 {
769 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
770 cache_set32(target, index, load(target, reg, ZERO, offset));
771 }
772
773 static void cache_set_store(struct target *target, unsigned int index,
774 unsigned int reg, slot_t slot)
775 {
776 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
777 cache_set32(target, index, store(target, reg, ZERO, offset));
778 }
779
780 static void dump_debug_ram(struct target *target)
781 {
782 for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
783 uint32_t value = dram_read32(target, i);
784 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
785 }
786 }
787
788 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
789 static void cache_invalidate(struct target *target)
790 {
791 riscv011_info_t *info = get_info(target);
792 for (unsigned int i = 0; i < info->dramsize; i++) {
793 info->dram_cache[i].valid = false;
794 info->dram_cache[i].dirty = false;
795 }
796 }
797
798 /* Called by cache_write() after the program has run. Also call this if you're
799 * running programs without calling cache_write(). */
800 static void cache_clean(struct target *target)
801 {
802 riscv011_info_t *info = get_info(target);
803 for (unsigned int i = 0; i < info->dramsize; i++) {
804 if (i >= 4)
805 info->dram_cache[i].valid = false;
806 info->dram_cache[i].dirty = false;
807 }
808 }
809
810 static int cache_check(struct target *target)
811 {
812 riscv011_info_t *info = get_info(target);
813 int error = 0;
814
815 for (unsigned int i = 0; i < info->dramsize; i++) {
816 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
817 if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
818 error++;
819 }
820 }
821
822 if (error) {
823 dump_debug_ram(target);
824 return ERROR_FAIL;
825 }
826
827 return ERROR_OK;
828 }
829
830 /** Write cache to the target, and optionally run the program.
831 * Then read the value at address into the cache, assuming address < 128. */
832 #define CACHE_NO_READ 128
833 static int cache_write(struct target *target, unsigned int address, bool run)
834 {
835 LOG_DEBUG("enter");
836 riscv011_info_t *info = get_info(target);
837 scans_t *scans = scans_new(target, info->dramsize + 2);
838
839 unsigned int last = info->dramsize;
840 for (unsigned int i = 0; i < info->dramsize; i++) {
841 if (info->dram_cache[i].dirty)
842 last = i;
843 }
844
845 if (last == info->dramsize) {
846 /* Nothing needs to be written to RAM. */
847 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
848
849 } else {
850 for (unsigned int i = 0; i < info->dramsize; i++) {
851 if (info->dram_cache[i].dirty) {
852 bool set_interrupt = (i == last && run);
853 scans_add_write32(scans, i, info->dram_cache[i].data,
854 set_interrupt);
855 }
856 }
857 }
858
859 if (run || address < CACHE_NO_READ) {
860 /* Throw away the results of the first read, since it'll contain the
861 * result of the read that happened just before debugint was set. */
862 scans_add_read32(scans, address, false);
863
864 /* This scan contains the results of the read the caller requested, as
865 * well as an interrupt bit worth looking at. */
866 scans_add_read32(scans, address, false);
867 }
868
869 int retval = scans_execute(scans);
870 if (retval != ERROR_OK) {
871 scans_delete(scans);
872 LOG_ERROR("JTAG execute failed.");
873 return retval;
874 }
875
876 int errors = 0;
877 for (unsigned int i = 0; i < scans->next_scan; i++) {
878 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
879 DBUS_OP_SIZE);
880 switch (status) {
881 case DBUS_STATUS_SUCCESS:
882 break;
883 case DBUS_STATUS_FAILED:
884 LOG_ERROR("Debug RAM write failed. Hardware error?");
885 scans_delete(scans);
886 return ERROR_FAIL;
887 case DBUS_STATUS_BUSY:
888 errors++;
889 break;
890 default:
891 LOG_ERROR("Got invalid bus access status: %d", status);
892 scans_delete(scans);
893 return ERROR_FAIL;
894 }
895 }
896
897 if (errors) {
898 increase_dbus_busy_delay(target);
899
900 /* Try again, using the slow careful code.
901 * Write all RAM, just to be extra cautious. */
902 for (unsigned int i = 0; i < info->dramsize; i++) {
903 if (i == last && run)
904 dram_write32(target, last, info->dram_cache[last].data, true);
905 else
906 dram_write32(target, i, info->dram_cache[i].data, false);
907 info->dram_cache[i].dirty = false;
908 }
909 if (run)
910 cache_clean(target);
911
912 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
913 LOG_ERROR("Debug interrupt didn't clear.");
914 dump_debug_ram(target);
915 scans_delete(scans);
916 return ERROR_FAIL;
917 }
918
919 } else {
920 if (run) {
921 cache_clean(target);
922 } else {
923 for (unsigned int i = 0; i < info->dramsize; i++)
924 info->dram_cache[i].dirty = false;
925 }
926
927 if (run || address < CACHE_NO_READ) {
928 int interrupt = scans_get_u32(scans, scans->next_scan-1,
929 DBUS_DATA_START + 33, 1);
930 if (interrupt) {
931 increase_interrupt_high_delay(target);
932 /* Slow path wait for it to clear. */
933 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
934 LOG_ERROR("Debug interrupt didn't clear.");
935 dump_debug_ram(target);
936 scans_delete(scans);
937 return ERROR_FAIL;
938 }
939 } else {
940 /* We read a useful value in that last scan. */
941 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
942 DBUS_ADDRESS_START, info->addrbits);
943 if (read_addr != address) {
944 LOG_INFO("Got data from 0x%x but expected it from 0x%x",
945 read_addr, address);
946 }
947 info->dram_cache[read_addr].data =
948 scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
949 info->dram_cache[read_addr].valid = true;
950 }
951 }
952 }
953
954 scans_delete(scans);
955 LOG_DEBUG("exit");
956
957 return ERROR_OK;
958 }
959
960 static uint32_t cache_get32(struct target *target, unsigned int address)
961 {
962 riscv011_info_t *info = get_info(target);
963 if (!info->dram_cache[address].valid) {
964 info->dram_cache[address].data = dram_read32(target, address);
965 info->dram_cache[address].valid = true;
966 }
967 return info->dram_cache[address].data;
968 }
969
970 static uint64_t cache_get(struct target *target, slot_t slot)
971 {
972 unsigned int offset = slot_offset(target, slot);
973 uint64_t value = cache_get32(target, offset);
974 if (riscv_xlen(target) > 32)
975 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
976 return value;
977 }
978
979 /* Write instruction that jumps from the specified word in Debug RAM to resume
980 * in Debug ROM. */
981 static void dram_write_jump(struct target *target, unsigned int index,
982 bool set_interrupt)
983 {
984 dram_write32(target, index,
985 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
986 set_interrupt);
987 }
988
989 static int wait_for_state(struct target *target, enum target_state state)
990 {
991 time_t start = time(NULL);
992 while (1) {
993 int result = riscv011_poll(target);
994 if (result != ERROR_OK)
995 return result;
996 if (target->state == state)
997 return ERROR_OK;
998 if (time(NULL) - start > riscv_command_timeout_sec) {
999 LOG_ERROR("Timed out waiting for state %d. "
1000 "Increase timeout with riscv set_command_timeout_sec.", state);
1001 return ERROR_FAIL;
1002 }
1003 }
1004 }
1005
1006 static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
1007 {
1008 riscv011_info_t *info = get_info(target);
1009 cache_set32(target, 0, csrr(S0, csr));
1010 cache_set_store(target, 1, S0, SLOT0);
1011 cache_set_jump(target, 2);
1012 if (cache_write(target, 4, true) != ERROR_OK)
1013 return ERROR_FAIL;
1014 *value = cache_get(target, SLOT0);
1015 LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1016
1017 uint32_t exception = cache_get32(target, info->dramsize-1);
1018 if (exception) {
1019 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1020 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1021 *value = ~0;
1022 return ERROR_FAIL;
1023 }
1024
1025 return ERROR_OK;
1026 }
1027
1028 static int write_csr(struct target *target, uint32_t csr, uint64_t value)
1029 {
1030 LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1031 cache_set_load(target, 0, S0, SLOT0);
1032 cache_set32(target, 1, csrw(S0, csr));
1033 cache_set_jump(target, 2);
1034 cache_set(target, SLOT0, value);
1035 if (cache_write(target, 4, true) != ERROR_OK)
1036 return ERROR_FAIL;
1037
1038 return ERROR_OK;
1039 }
1040
1041 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1042 {
1043 cache_set_load(target, 0, gpr, SLOT0);
1044 cache_set_jump(target, 1);
1045 cache_set(target, SLOT0, value);
1046 if (cache_write(target, 4, true) != ERROR_OK)
1047 return ERROR_FAIL;
1048 return ERROR_OK;
1049 }
1050
1051 static int maybe_read_tselect(struct target *target)
1052 {
1053 riscv011_info_t *info = get_info(target);
1054
1055 if (info->tselect_dirty) {
1056 int result = read_csr(target, &info->tselect, CSR_TSELECT);
1057 if (result != ERROR_OK)
1058 return result;
1059 info->tselect_dirty = false;
1060 }
1061
1062 return ERROR_OK;
1063 }
1064
1065 static int maybe_write_tselect(struct target *target)
1066 {
1067 riscv011_info_t *info = get_info(target);
1068
1069 if (!info->tselect_dirty) {
1070 int result = write_csr(target, CSR_TSELECT, info->tselect);
1071 if (result != ERROR_OK)
1072 return result;
1073 info->tselect_dirty = true;
1074 }
1075
1076 return ERROR_OK;
1077 }
1078
1079 static int execute_resume(struct target *target, bool step)
1080 {
1081 riscv011_info_t *info = get_info(target);
1082
1083 LOG_DEBUG("step=%d", step);
1084
1085 maybe_write_tselect(target);
1086
1087 /* TODO: check if dpc is dirty (which also is true if an exception was hit
1088 * at any time) */
1089 cache_set_load(target, 0, S0, SLOT0);
1090 cache_set32(target, 1, csrw(S0, CSR_DPC));
1091 cache_set_jump(target, 2);
1092 cache_set(target, SLOT0, info->dpc);
1093 if (cache_write(target, 4, true) != ERROR_OK)
1094 return ERROR_FAIL;
1095
1096 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1097 if (mstatus_reg->valid) {
1098 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1099 if (mstatus_user != info->mstatus_actual) {
1100 cache_set_load(target, 0, S0, SLOT0);
1101 cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1102 cache_set_jump(target, 2);
1103 cache_set(target, SLOT0, mstatus_user);
1104 if (cache_write(target, 4, true) != ERROR_OK)
1105 return ERROR_FAIL;
1106 }
1107 }
1108
1109 info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
1110 info->dcsr &= ~DCSR_HALT;
1111
1112 if (step)
1113 info->dcsr |= DCSR_STEP;
1114 else
1115 info->dcsr &= ~DCSR_STEP;
1116
1117 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1118 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1119 dram_write32(target, 2, fence_i(), false);
1120 dram_write_jump(target, 3, false);
1121
1122 /* Write DCSR value, set interrupt and clear haltnot. */
1123 uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1124 dbus_write(target, dram_address(4), dbus_value);
1125
1126 cache_invalidate(target);
1127
1128 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1129 LOG_ERROR("Debug interrupt didn't clear.");
1130 return ERROR_FAIL;
1131 }
1132
1133 target->state = TARGET_RUNNING;
1134 register_cache_invalidate(target->reg_cache);
1135
1136 return ERROR_OK;
1137 }
1138
1139 /* Execute a step, and wait for reentry into Debug Mode. */
1140 static int full_step(struct target *target, bool announce)
1141 {
1142 int result = execute_resume(target, true);
1143 if (result != ERROR_OK)
1144 return result;
1145 time_t start = time(NULL);
1146 while (1) {
1147 result = poll_target(target, announce);
1148 if (result != ERROR_OK)
1149 return result;
1150 if (target->state != TARGET_DEBUG_RUNNING)
1151 break;
1152 if (time(NULL) - start > riscv_command_timeout_sec) {
1153 LOG_ERROR("Timed out waiting for step to complete."
1154 "Increase timeout with riscv set_command_timeout_sec");
1155 return ERROR_FAIL;
1156 }
1157 }
1158 return ERROR_OK;
1159 }
1160
1161 static int resume(struct target *target, int debug_execution, bool step)
1162 {
1163 if (debug_execution) {
1164 LOG_ERROR("TODO: debug_execution is true");
1165 return ERROR_FAIL;
1166 }
1167
1168 return execute_resume(target, step);
1169 }
1170
1171 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1172 {
1173 struct reg *r = &target->reg_cache->reg_list[number];
1174 if (!r->valid) {
1175 LOG_ERROR("Register cache entry for %d is invalid!", number);
1176 assert(r->valid);
1177 }
1178 uint64_t value = buf_get_u64(r->value, 0, r->size);
1179 LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1180 return value;
1181 }
1182
1183 static void reg_cache_set(struct target *target, unsigned int number,
1184 uint64_t value)
1185 {
1186 struct reg *r = &target->reg_cache->reg_list[number];
1187 LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1188 r->valid = true;
1189 buf_set_u64(r->value, 0, r->size, value);
1190 }
1191
1192 static int update_mstatus_actual(struct target *target)
1193 {
1194 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1195 if (mstatus_reg->valid) {
1196 /* We previously made it valid. */
1197 return ERROR_OK;
1198 }
1199
1200 /* Force reading the register. In that process mstatus_actual will be
1201 * updated. */
1202 riscv_reg_t mstatus;
1203 return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
1204 }
1205
1206 /*** OpenOCD target functions. ***/
1207
1208 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1209 {
1210 riscv011_info_t *info = get_info(target);
1211 if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1212 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1213 cache_set_store(target, 1, S0, SLOT0);
1214 cache_set_jump(target, 2);
1215 } else {
1216 LOG_ERROR("Don't know how to read register %d", regnum);
1217 return ERROR_FAIL;
1218 }
1219
1220 if (cache_write(target, 4, true) != ERROR_OK)
1221 return ERROR_FAIL;
1222
1223 uint32_t exception = cache_get32(target, info->dramsize-1);
1224 if (exception) {
1225 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1226 *value = ~0;
1227 return ERROR_FAIL;
1228 }
1229
1230 *value = cache_get(target, SLOT0);
1231 LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1232
1233 if (regnum == GDB_REGNO_MSTATUS)
1234 info->mstatus_actual = *value;
1235
1236 return ERROR_OK;
1237 }
1238
1239 /* Write the register. No caching or games. */
1240 static int register_write(struct target *target, unsigned int number,
1241 uint64_t value)
1242 {
1243 riscv011_info_t *info = get_info(target);
1244
1245 maybe_write_tselect(target);
1246
1247 if (number == S0) {
1248 cache_set_load(target, 0, S0, SLOT0);
1249 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
1250 cache_set_jump(target, 2);
1251 } else if (number == S1) {
1252 cache_set_load(target, 0, S0, SLOT0);
1253 cache_set_store(target, 1, S0, SLOT_LAST);
1254 cache_set_jump(target, 2);
1255 } else if (number <= GDB_REGNO_XPR31) {
1256 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1257 cache_set_jump(target, 1);
1258 } else if (number == GDB_REGNO_PC) {
1259 info->dpc = value;
1260 return ERROR_OK;
1261 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1262 int result = update_mstatus_actual(target);
1263 if (result != ERROR_OK)
1264 return result;
1265 unsigned i = 0;
1266 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1267 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1268 cache_set_load(target, i++, S0, SLOT1);
1269 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1270 cache_set(target, SLOT1, info->mstatus_actual);
1271 }
1272
1273 if (riscv_xlen(target) == 32)
1274 cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1275 else
1276 cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1277 cache_set_jump(target, i++);
1278 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1279 cache_set_load(target, 0, S0, SLOT0);
1280 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1281 cache_set_jump(target, 2);
1282
1283 if (number == GDB_REGNO_MSTATUS)
1284 info->mstatus_actual = value;
1285 } else if (number == GDB_REGNO_PRIV) {
1286 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1287 return ERROR_OK;
1288 } else {
1289 LOG_ERROR("Don't know how to write register %d", number);
1290 return ERROR_FAIL;
1291 }
1292
1293 cache_set(target, SLOT0, value);
1294 if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1295 return ERROR_FAIL;
1296
1297 uint32_t exception = cache_get32(target, info->dramsize-1);
1298 if (exception) {
1299 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1300 gdb_regno_name(number));
1301 return ERROR_FAIL;
1302 }
1303
1304 return ERROR_OK;
1305 }
1306
1307 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
1308 int regid)
1309 {
1310 assert(hartid == 0);
1311 riscv011_info_t *info = get_info(target);
1312
1313 maybe_write_tselect(target);
1314
1315 if (regid <= GDB_REGNO_XPR31) {
1316 *value = reg_cache_get(target, regid);
1317 } else if (regid == GDB_REGNO_PC) {
1318 *value = info->dpc;
1319 } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1320 int result = update_mstatus_actual(target);
1321 if (result != ERROR_OK)
1322 return result;
1323 unsigned i = 0;
1324 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1325 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1326 cache_set_load(target, i++, S0, SLOT1);
1327 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1328 cache_set(target, SLOT1, info->mstatus_actual);
1329 }
1330
1331 if (riscv_xlen(target) == 32)
1332 cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1333 else
1334 cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1335 cache_set_jump(target, i++);
1336
1337 if (cache_write(target, 4, true) != ERROR_OK)
1338 return ERROR_FAIL;
1339 } else if (regid == GDB_REGNO_PRIV) {
1340 *value = get_field(info->dcsr, DCSR_PRV);
1341 } else {
1342 int result = register_read(target, value, regid);
1343 if (result != ERROR_OK)
1344 return result;
1345 }
1346
1347 if (regid == GDB_REGNO_MSTATUS)
1348 target->reg_cache->reg_list[regid].valid = true;
1349
1350 return ERROR_OK;
1351 }
1352
1353 static int set_register(struct target *target, int hartid, int regid,
1354 uint64_t value)
1355 {
1356 assert(hartid == 0);
1357 return register_write(target, regid, value);
1358 }
1359
1360 static int halt(struct target *target)
1361 {
1362 LOG_DEBUG("riscv_halt()");
1363 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1364
1365 cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1366 cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1367 cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1368 cache_set_jump(target, 3);
1369
1370 if (cache_write(target, 4, true) != ERROR_OK) {
1371 LOG_ERROR("cache_write() failed.");
1372 return ERROR_FAIL;
1373 }
1374
1375 return ERROR_OK;
1376 }
1377
1378 static int init_target(struct command_context *cmd_ctx,
1379 struct target *target)
1380 {
1381 LOG_DEBUG("init");
1382 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1383 generic_info->get_register = get_register;
1384 generic_info->set_register = set_register;
1385
1386 generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
1387 if (!generic_info->version_specific)
1388 return ERROR_FAIL;
1389
1390 /* Assume 32-bit until we discover the real value in examine(). */
1391 generic_info->xlen[0] = 32;
1392 riscv_init_registers(target);
1393
1394 return ERROR_OK;
1395 }
1396
1397 static void deinit_target(struct target *target)
1398 {
1399 LOG_DEBUG("riscv_deinit_target()");
1400 riscv_info_t *info = (riscv_info_t *) target->arch_info;
1401 free(info->version_specific);
1402 info->version_specific = NULL;
1403 }
1404
1405 static int strict_step(struct target *target, bool announce)
1406 {
1407 riscv011_info_t *info = get_info(target);
1408
1409 LOG_DEBUG("enter");
1410
1411 struct breakpoint *breakpoint = target->breakpoints;
1412 while (breakpoint) {
1413 riscv_remove_breakpoint(target, breakpoint);
1414 breakpoint = breakpoint->next;
1415 }
1416
1417 struct watchpoint *watchpoint = target->watchpoints;
1418 while (watchpoint) {
1419 riscv_remove_watchpoint(target, watchpoint);
1420 watchpoint = watchpoint->next;
1421 }
1422
1423 int result = full_step(target, announce);
1424 if (result != ERROR_OK)
1425 return result;
1426
1427 breakpoint = target->breakpoints;
1428 while (breakpoint) {
1429 riscv_add_breakpoint(target, breakpoint);
1430 breakpoint = breakpoint->next;
1431 }
1432
1433 watchpoint = target->watchpoints;
1434 while (watchpoint) {
1435 riscv_add_watchpoint(target, watchpoint);
1436 watchpoint = watchpoint->next;
1437 }
1438
1439 info->need_strict_step = false;
1440
1441 return ERROR_OK;
1442 }
1443
1444 static int step(struct target *target, int current, target_addr_t address,
1445 int handle_breakpoints)
1446 {
1447 riscv011_info_t *info = get_info(target);
1448
1449 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1450
1451 if (!current) {
1452 if (riscv_xlen(target) > 32) {
1453 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1454 riscv_xlen(target));
1455 }
1456 int result = register_write(target, GDB_REGNO_PC, address);
1457 if (result != ERROR_OK)
1458 return result;
1459 }
1460
1461 if (info->need_strict_step || handle_breakpoints) {
1462 int result = strict_step(target, true);
1463 if (result != ERROR_OK)
1464 return result;
1465 } else {
1466 return resume(target, 0, true);
1467 }
1468
1469 return ERROR_OK;
1470 }
1471
1472 static int examine(struct target *target)
1473 {
1474 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1475
1476 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1477 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1478 LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1479 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1480 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1481 if (dtmcontrol == 0) {
1482 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1483 return ERROR_FAIL;
1484 }
1485 if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1486 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1487 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1488 return ERROR_FAIL;
1489 }
1490
1491 RISCV_INFO(r);
1492 r->hart_count = 1;
1493
1494 riscv011_info_t *info = get_info(target);
1495 info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1496 info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1497 if (info->dtmcontrol_idle == 0) {
1498 /* Some old SiFive cores don't set idle but need it to be 1. */
1499 uint32_t idcode = idcode_scan(target);
1500 if (idcode == 0x10e31913)
1501 info->dtmcontrol_idle = 1;
1502 }
1503
1504 uint32_t dminfo = dbus_read(target, DMINFO);
1505 LOG_DEBUG("dminfo: 0x%08x", dminfo);
1506 LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1507 LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1508 LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1509 LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1510 LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1511 LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1512 LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1513 LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1514 LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1515 LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1516 LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1517 LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
1518
1519 if (get_field(dminfo, DMINFO_VERSION) != 1) {
1520 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1521 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1522 return ERROR_FAIL;
1523 }
1524
1525 info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1526
1527 if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1528 LOG_ERROR("Authentication required by RISC-V core but not "
1529 "supported by OpenOCD. dminfo=0x%x", dminfo);
1530 return ERROR_FAIL;
1531 }
1532
1533 /* Pretend this is a 32-bit system until we have found out the true value. */
1534 r->xlen[0] = 32;
1535
1536 /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1537 cache_set32(target, 0, xori(S1, ZERO, -1));
1538 /* 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff */
1539 cache_set32(target, 1, srli(S1, S1, 31));
1540 /* 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff */
1541 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1542 cache_set32(target, 3, srli(S1, S1, 31));
1543 /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
1544 cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1545 cache_set_jump(target, 5);
1546 for (unsigned i = 6; i < info->dramsize; i++)
1547 cache_set32(target, i, i * 0x01020304);
1548
1549 cache_write(target, 0, false);
1550
1551 /* Check that we can actually read/write dram. */
1552 if (cache_check(target) != ERROR_OK)
1553 return ERROR_FAIL;
1554
1555 cache_write(target, 0, true);
1556 cache_invalidate(target);
1557
1558 uint32_t word0 = cache_get32(target, 0);
1559 uint32_t word1 = cache_get32(target, 1);
1560 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1561 if (word0 == 1 && word1 == 0) {
1562 generic_info->xlen[0] = 32;
1563 } else if (word0 == 0xffffffff && word1 == 3) {
1564 generic_info->xlen[0] = 64;
1565 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1566 generic_info->xlen[0] = 128;
1567 } else {
1568 uint32_t exception = cache_get32(target, info->dramsize-1);
1569 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1570 word0, word1, exception);
1571 dump_debug_ram(target);
1572 return ERROR_FAIL;
1573 }
1574 LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1575
1576 if (read_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) {
1577 const unsigned old_csr_misa = 0xf10;
1578 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1579 old_csr_misa);
1580 if (read_csr(target, &r->misa[0], old_csr_misa) != ERROR_OK) {
1581 /* Maybe this is an old core that still has $misa at the old
1582 * address. */
1583 LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1584 return ERROR_FAIL;
1585 }
1586 }
1587
1588 /* Update register list to match discovered XLEN/supported extensions. */
1589 riscv_init_registers(target);
1590
1591 info->never_halted = true;
1592
1593 int result = riscv011_poll(target);
1594 if (result != ERROR_OK)
1595 return result;
1596
1597 target_set_examined(target);
1598 riscv_set_current_hartid(target, 0);
1599 for (size_t i = 0; i < 32; ++i)
1600 reg_cache_set(target, i, -1);
1601 LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1602 riscv_xlen(target), r->misa[0]);
1603
1604 return ERROR_OK;
1605 }
1606
1607 static riscv_error_t handle_halt_routine(struct target *target)
1608 {
1609 riscv011_info_t *info = get_info(target);
1610
1611 scans_t *scans = scans_new(target, 256);
1612
1613 /* Read all GPRs as fast as we can, because gdb is going to ask for them
1614 * anyway. Reading them one at a time is much slower. */
1615
1616 /* Write the jump back to address 1. */
1617 scans_add_write_jump(scans, 1, false);
1618 for (int reg = 1; reg < 32; reg++) {
1619 if (reg == S0 || reg == S1)
1620 continue;
1621
1622 /* Write store instruction. */
1623 scans_add_write_store(scans, 0, reg, SLOT0, true);
1624
1625 /* Read value. */
1626 scans_add_read(scans, SLOT0, false);
1627 }
1628
1629 /* Write store of s0 at index 1. */
1630 scans_add_write_store(scans, 1, S0, SLOT0, false);
1631 /* Write jump at index 2. */
1632 scans_add_write_jump(scans, 2, false);
1633
1634 /* Read S1 from debug RAM */
1635 scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1636 /* Read value. */
1637 scans_add_read(scans, SLOT0, false);
1638
1639 /* Read S0 from dscratch */
1640 unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
1641 for (unsigned int i = 0; i < DIM(csr); i++) {
1642 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1643 scans_add_read(scans, SLOT0, false);
1644 }
1645
1646 /* Final read to get the last value out. */
1647 scans_add_read32(scans, 4, false);
1648
1649 int retval = scans_execute(scans);
1650 if (retval != ERROR_OK) {
1651 LOG_ERROR("JTAG execute failed: %d", retval);
1652 goto error;
1653 }
1654
1655 unsigned int dbus_busy = 0;
1656 unsigned int interrupt_set = 0;
1657 unsigned result = 0;
1658 uint64_t value = 0;
1659 reg_cache_set(target, 0, 0);
1660 /* The first scan result is the result from something old we don't care
1661 * about. */
1662 for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1663 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1664 DBUS_OP_SIZE);
1665 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1666 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1667 info->addrbits);
1668 switch (status) {
1669 case DBUS_STATUS_SUCCESS:
1670 break;
1671 case DBUS_STATUS_FAILED:
1672 LOG_ERROR("Debug access failed. Hardware error?");
1673 goto error;
1674 case DBUS_STATUS_BUSY:
1675 dbus_busy++;
1676 break;
1677 default:
1678 LOG_ERROR("Got invalid bus access status: %d", status);
1679 return ERROR_FAIL;
1680 }
1681 if (data & DMCONTROL_INTERRUPT) {
1682 interrupt_set++;
1683 break;
1684 }
1685 if (address == 4 || address == 5) {
1686 unsigned int reg;
1687 switch (result) {
1688 case 0:
1689 reg = 1;
1690 break;
1691 case 1:
1692 reg = 2;
1693 break;
1694 case 2:
1695 reg = 3;
1696 break;
1697 case 3:
1698 reg = 4;
1699 break;
1700 case 4:
1701 reg = 5;
1702 break;
1703 case 5:
1704 reg = 6;
1705 break;
1706 case 6:
1707 reg = 7;
1708 break;
1709 /* S0 */
1710 /* S1 */
1711 case 7:
1712 reg = 10;
1713 break;
1714 case 8:
1715 reg = 11;
1716 break;
1717 case 9:
1718 reg = 12;
1719 break;
1720 case 10:
1721 reg = 13;
1722 break;
1723 case 11:
1724 reg = 14;
1725 break;
1726 case 12:
1727 reg = 15;
1728 break;
1729 case 13:
1730 reg = 16;
1731 break;
1732 case 14:
1733 reg = 17;
1734 break;
1735 case 15:
1736 reg = 18;
1737 break;
1738 case 16:
1739 reg = 19;
1740 break;
1741 case 17:
1742 reg = 20;
1743 break;
1744 case 18:
1745 reg = 21;
1746 break;
1747 case 19:
1748 reg = 22;
1749 break;
1750 case 20:
1751 reg = 23;
1752 break;
1753 case 21:
1754 reg = 24;
1755 break;
1756 case 22:
1757 reg = 25;
1758 break;
1759 case 23:
1760 reg = 26;
1761 break;
1762 case 24:
1763 reg = 27;
1764 break;
1765 case 25:
1766 reg = 28;
1767 break;
1768 case 26:
1769 reg = 29;
1770 break;
1771 case 27:
1772 reg = 30;
1773 break;
1774 case 28:
1775 reg = 31;
1776 break;
1777 case 29:
1778 reg = S1;
1779 break;
1780 case 30:
1781 reg = S0;
1782 break;
1783 case 31:
1784 reg = CSR_DPC;
1785 break;
1786 case 32:
1787 reg = CSR_DCSR;
1788 break;
1789 default:
1790 assert(0);
1791 LOG_ERROR("Got invalid register result %d", result);
1792 goto error;
1793 }
1794 if (riscv_xlen(target) == 32) {
1795 reg_cache_set(target, reg, data & 0xffffffff);
1796 result++;
1797 } else if (riscv_xlen(target) == 64) {
1798 if (address == 4) {
1799 value = data & 0xffffffff;
1800 } else if (address == 5) {
1801 reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1802 value = 0;
1803 result++;
1804 }
1805 }
1806 }
1807 }
1808
1809 scans_delete(scans);
1810
1811 if (dbus_busy) {
1812 increase_dbus_busy_delay(target);
1813 return RE_AGAIN;
1814 }
1815 if (interrupt_set) {
1816 increase_interrupt_high_delay(target);
1817 return RE_AGAIN;
1818 }
1819
1820 /* TODO: get rid of those 2 variables and talk to the cache directly. */
1821 info->dpc = reg_cache_get(target, CSR_DPC);
1822 info->dcsr = reg_cache_get(target, CSR_DCSR);
1823
1824 cache_invalidate(target);
1825
1826 return RE_OK;
1827
1828 error:
1829 scans_delete(scans);
1830 return RE_FAIL;
1831 }
1832
1833 static int handle_halt(struct target *target, bool announce)
1834 {
1835 riscv011_info_t *info = get_info(target);
1836 target->state = TARGET_HALTED;
1837
1838 riscv_error_t re;
1839 do {
1840 re = handle_halt_routine(target);
1841 } while (re == RE_AGAIN);
1842 if (re != RE_OK) {
1843 LOG_ERROR("handle_halt_routine failed");
1844 return ERROR_FAIL;
1845 }
1846
1847 int cause = get_field(info->dcsr, DCSR_CAUSE);
1848 switch (cause) {
1849 case DCSR_CAUSE_SWBP:
1850 target->debug_reason = DBG_REASON_BREAKPOINT;
1851 break;
1852 case DCSR_CAUSE_HWBP:
1853 target->debug_reason = DBG_REASON_WPTANDBKPT;
1854 /* If we halted because of a data trigger, gdb doesn't know to do
1855 * the disable-breakpoints-step-enable-breakpoints dance. */
1856 info->need_strict_step = true;
1857 break;
1858 case DCSR_CAUSE_DEBUGINT:
1859 target->debug_reason = DBG_REASON_DBGRQ;
1860 break;
1861 case DCSR_CAUSE_STEP:
1862 target->debug_reason = DBG_REASON_SINGLESTEP;
1863 break;
1864 case DCSR_CAUSE_HALT:
1865 default:
1866 LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1867 cause, info->dcsr);
1868 }
1869
1870 if (info->never_halted) {
1871 info->never_halted = false;
1872
1873 int result = maybe_read_tselect(target);
1874 if (result != ERROR_OK)
1875 return result;
1876 riscv_enumerate_triggers(target);
1877 }
1878
1879 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1880 int retval;
1881 if (riscv_semihosting(target, &retval) != 0)
1882 return retval;
1883 }
1884
1885 if (announce)
1886 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1887
1888 const char *cause_string[] = {
1889 "none",
1890 "software breakpoint",
1891 "hardware trigger",
1892 "debug interrupt",
1893 "step",
1894 "halt"
1895 };
1896 /* This is logged to the user so that gdb will show it when a user types
1897 * 'monitor reset init'. At that time gdb appears to have the pc cached
1898 * still so if a user manually inspects the pc it will still have the old
1899 * value. */
1900 LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1901
1902 return ERROR_OK;
1903 }
1904
1905 static int poll_target(struct target *target, bool announce)
1906 {
1907 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1908
1909 /* Inhibit debug logging during poll(), which isn't usually interesting and
1910 * just fills up the screen/logs with clutter. */
1911 int old_debug_level = debug_level;
1912 if (debug_level >= LOG_LVL_DEBUG)
1913 debug_level = LOG_LVL_INFO;
1914 bits_t bits = read_bits(target);
1915 debug_level = old_debug_level;
1916
1917 if (bits.haltnot && bits.interrupt) {
1918 target->state = TARGET_DEBUG_RUNNING;
1919 LOG_DEBUG("debug running");
1920 } else if (bits.haltnot && !bits.interrupt) {
1921 if (target->state != TARGET_HALTED)
1922 return handle_halt(target, announce);
1923 } else if (!bits.haltnot && bits.interrupt) {
1924 /* Target is halting. There is no state for that, so don't change anything. */
1925 LOG_DEBUG("halting");
1926 } else if (!bits.haltnot && !bits.interrupt) {
1927 target->state = TARGET_RUNNING;
1928 }
1929
1930 return ERROR_OK;
1931 }
1932
1933 static int riscv011_poll(struct target *target)
1934 {
1935 return poll_target(target, true);
1936 }
1937
1938 static int riscv011_resume(struct target *target, int current,
1939 target_addr_t address, int handle_breakpoints, int debug_execution)
1940 {
1941 riscv011_info_t *info = get_info(target);
1942
1943 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1944
1945 if (!current) {
1946 if (riscv_xlen(target) > 32) {
1947 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1948 riscv_xlen(target));
1949 }
1950 int result = register_write(target, GDB_REGNO_PC, address);
1951 if (result != ERROR_OK)
1952 return result;
1953 }
1954
1955 if (info->need_strict_step || handle_breakpoints) {
1956 int result = strict_step(target, false);
1957 if (result != ERROR_OK)
1958 return result;
1959 }
1960
1961 return resume(target, debug_execution, false);
1962 }
1963
1964 static int assert_reset(struct target *target)
1965 {
1966 riscv011_info_t *info = get_info(target);
1967 /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1968
1969 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1970
1971 /* The only assumption we can make is that the TAP was reset. */
1972 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1973 LOG_ERROR("Debug interrupt didn't clear.");
1974 return ERROR_FAIL;
1975 }
1976
1977 /* Not sure what we should do when there are multiple cores.
1978 * Here just reset the single hart we're talking to. */
1979 info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
1980 DCSR_EBREAKU | DCSR_HALT;
1981 if (target->reset_halt)
1982 info->dcsr |= DCSR_NDRESET;
1983 else
1984 info->dcsr |= DCSR_FULLRESET;
1985 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1986 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1987 /* We shouldn't actually need the jump because a reset should happen. */
1988 dram_write_jump(target, 2, false);
1989 dram_write32(target, 4, info->dcsr, true);
1990 cache_invalidate(target);
1991
1992 target->state = TARGET_RESET;
1993
1994 return ERROR_OK;
1995 }
1996
1997 static int deassert_reset(struct target *target)
1998 {
1999 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2000 if (target->reset_halt)
2001 return wait_for_state(target, TARGET_HALTED);
2002 else
2003 return wait_for_state(target, TARGET_RUNNING);
2004 }
2005
2006 static int read_memory(struct target *target, target_addr_t address,
2007 uint32_t size, uint32_t count, uint8_t *buffer)
2008 {
2009 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2010
2011 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2012 switch (size) {
2013 case 1:
2014 cache_set32(target, 1, lb(S1, S0, 0));
2015 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2016 break;
2017 case 2:
2018 cache_set32(target, 1, lh(S1, S0, 0));
2019 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2020 break;
2021 case 4:
2022 cache_set32(target, 1, lw(S1, S0, 0));
2023 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2024 break;
2025 default:
2026 LOG_ERROR("Unsupported size: %d", size);
2027 return ERROR_FAIL;
2028 }
2029 cache_set_jump(target, 3);
2030 cache_write(target, CACHE_NO_READ, false);
2031
2032 riscv011_info_t *info = get_info(target);
2033 const unsigned max_batch_size = 256;
2034 scans_t *scans = scans_new(target, max_batch_size);
2035
2036 uint32_t result_value = 0x777;
2037 uint32_t i = 0;
2038 while (i < count + 3) {
2039 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2040 scans_reset(scans);
2041
2042 for (unsigned int j = 0; j < batch_size; j++) {
2043 if (i + j == count) {
2044 /* Just insert a read so we can scan out the last value. */
2045 scans_add_read32(scans, 4, false);
2046 } else if (i + j >= count + 1) {
2047 /* And check for errors. */
2048 scans_add_read32(scans, info->dramsize-1, false);
2049 } else {
2050 /* Write the next address and set interrupt. */
2051 uint32_t offset = size * (i + j);
2052 scans_add_write32(scans, 4, address + offset, true);
2053 }
2054 }
2055
2056 int retval = scans_execute(scans);
2057 if (retval != ERROR_OK) {
2058 LOG_ERROR("JTAG execute failed: %d", retval);
2059 goto error;
2060 }
2061
2062 int dbus_busy = 0;
2063 int execute_busy = 0;
2064 for (unsigned int j = 0; j < batch_size; j++) {
2065 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2066 DBUS_OP_SIZE);
2067 switch (status) {
2068 case DBUS_STATUS_SUCCESS:
2069 break;
2070 case DBUS_STATUS_FAILED:
2071 LOG_ERROR("Debug RAM write failed. Hardware error?");
2072 goto error;
2073 case DBUS_STATUS_BUSY:
2074 dbus_busy++;
2075 break;
2076 default:
2077 LOG_ERROR("Got invalid bus access status: %d", status);
2078 return ERROR_FAIL;
2079 }
2080 uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2081 DBUS_DATA_SIZE);
2082 if (data & DMCONTROL_INTERRUPT)
2083 execute_busy++;
2084 if (i + j == count + 2) {
2085 result_value = data;
2086 } else if (i + j > 1) {
2087 uint32_t offset = size * (i + j - 2);
2088 switch (size) {
2089 case 1:
2090 buffer[offset] = data;
2091 break;
2092 case 2:
2093 buffer[offset] = data;
2094 buffer[offset+1] = data >> 8;
2095 break;
2096 case 4:
2097 buffer[offset] = data;
2098 buffer[offset+1] = data >> 8;
2099 buffer[offset+2] = data >> 16;
2100 buffer[offset+3] = data >> 24;
2101 break;
2102 }
2103 }
2104 LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2105 }
2106 if (dbus_busy)
2107 increase_dbus_busy_delay(target);
2108 if (execute_busy)
2109 increase_interrupt_high_delay(target);
2110 if (dbus_busy || execute_busy) {
2111 wait_for_debugint_clear(target, false);
2112
2113 /* Retry. */
2114 LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2115 " with more delays", address + size * i);
2116 } else {
2117 i += batch_size;
2118 }
2119 }
2120
2121 if (result_value != 0) {
2122 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2123 TARGET_PRIxADDR, result_value, address + size * (count-1));
2124 if (count > 1) {
2125 LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2126 " and 0x%" TARGET_PRIxADDR " as well, but we "
2127 "didn't check then.)",
2128 address, address + size * (count-2) + size - 1);
2129 }
2130 goto error;
2131 }
2132
2133 scans_delete(scans);
2134 cache_clean(target);
2135 return ERROR_OK;
2136
2137 error:
2138 scans_delete(scans);
2139 cache_clean(target);
2140 return ERROR_FAIL;
2141 }
2142
2143 static int setup_write_memory(struct target *target, uint32_t size)
2144 {
2145 switch (size) {
2146 case 1:
2147 cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2148 cache_set32(target, 1, sb(S0, T0, 0));
2149 break;
2150 case 2:
2151 cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2152 cache_set32(target, 1, sh(S0, T0, 0));
2153 break;
2154 case 4:
2155 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2156 cache_set32(target, 1, sw(S0, T0, 0));
2157 break;
2158 default:
2159 LOG_ERROR("Unsupported size: %d", size);
2160 return ERROR_FAIL;
2161 }
2162 cache_set32(target, 2, addi(T0, T0, size));
2163 cache_set_jump(target, 3);
2164 cache_write(target, 4, false);
2165
2166 return ERROR_OK;
2167 }
2168
2169 static int write_memory(struct target *target, target_addr_t address,
2170 uint32_t size, uint32_t count, const uint8_t *buffer)
2171 {
2172 riscv011_info_t *info = get_info(target);
2173 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2174
2175 /* Set up the address. */
2176 cache_set_store(target, 0, T0, SLOT1);
2177 cache_set_load(target, 1, T0, SLOT0);
2178 cache_set_jump(target, 2);
2179 cache_set(target, SLOT0, address);
2180 if (cache_write(target, 5, true) != ERROR_OK)
2181 return ERROR_FAIL;
2182
2183 uint64_t t0 = cache_get(target, SLOT1);
2184 LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2185
2186 if (setup_write_memory(target, size) != ERROR_OK)
2187 return ERROR_FAIL;
2188
2189 const unsigned max_batch_size = 256;
2190 scans_t *scans = scans_new(target, max_batch_size);
2191
2192 uint32_t result_value = 0x777;
2193 uint32_t i = 0;
2194 while (i < count + 2) {
2195 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2196 scans_reset(scans);
2197
2198 for (unsigned int j = 0; j < batch_size; j++) {
2199 if (i + j >= count) {
2200 /* Check for an exception. */
2201 scans_add_read32(scans, info->dramsize-1, false);
2202 } else {
2203 /* Write the next value and set interrupt. */
2204 uint32_t value;
2205 uint32_t offset = size * (i + j);
2206 switch (size) {
2207 case 1:
2208 value = buffer[offset];
2209 break;
2210 case 2:
2211 value = buffer[offset] |
2212 (buffer[offset+1] << 8);
2213 break;
2214 case 4:
2215 value = buffer[offset] |
2216 ((uint32_t) buffer[offset+1] << 8) |
2217 ((uint32_t) buffer[offset+2] << 16) |
2218 ((uint32_t) buffer[offset+3] << 24);
2219 break;
2220 default:
2221 goto error;
2222 }
2223
2224 scans_add_write32(scans, 4, value, true);
2225 }
2226 }
2227
2228 int retval = scans_execute(scans);
2229 if (retval != ERROR_OK) {
2230 LOG_ERROR("JTAG execute failed: %d", retval);
2231 goto error;
2232 }
2233
2234 int dbus_busy = 0;
2235 int execute_busy = 0;
2236 for (unsigned int j = 0; j < batch_size; j++) {
2237 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2238 DBUS_OP_SIZE);
2239 switch (status) {
2240 case DBUS_STATUS_SUCCESS:
2241 break;
2242 case DBUS_STATUS_FAILED:
2243 LOG_ERROR("Debug RAM write failed. Hardware error?");
2244 goto error;
2245 case DBUS_STATUS_BUSY:
2246 dbus_busy++;
2247 break;
2248 default:
2249 LOG_ERROR("Got invalid bus access status: %d", status);
2250 return ERROR_FAIL;
2251 }
2252 int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2253 if (interrupt)
2254 execute_busy++;
2255 if (i + j == count + 1)
2256 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2257 }
2258 if (dbus_busy)
2259 increase_dbus_busy_delay(target);
2260 if (execute_busy)
2261 increase_interrupt_high_delay(target);
2262 if (dbus_busy || execute_busy) {
2263 wait_for_debugint_clear(target, false);
2264
2265 /* Retry.
2266 * Set t0 back to what it should have been at the beginning of this
2267 * batch. */
2268 LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2269 " with more delays", address + size * i);
2270
2271 cache_clean(target);
2272
2273 if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2274 goto error;
2275
2276 if (setup_write_memory(target, size) != ERROR_OK)
2277 goto error;
2278 } else {
2279 i += batch_size;
2280 }
2281 }
2282
2283 if (result_value != 0) {
2284 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2285 TARGET_PRIxADDR, result_value, address + size * (count-1));
2286 if (count > 1) {
2287 LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2288 " and 0x%" TARGET_PRIxADDR " as well, but we "
2289 "didn't check then.)",
2290 address, address + size * (count-2) + size - 1);
2291 }
2292 goto error;
2293 }
2294
2295 scans_delete(scans);
2296 cache_clean(target);
2297 return register_write(target, T0, t0);
2298
2299 error:
2300 scans_delete(scans);
2301 cache_clean(target);
2302 return ERROR_FAIL;
2303 }
2304
2305 static int arch_state(struct target *target)
2306 {
2307 return ERROR_OK;
2308 }
2309
2310 struct target_type riscv011_target = {
2311 .name = "riscv",
2312
2313 .init_target = init_target,
2314 .deinit_target = deinit_target,
2315 .examine = examine,
2316
2317 /* poll current target status */
2318 .poll = riscv011_poll,
2319
2320 .halt = halt,
2321 .resume = riscv011_resume,
2322 .step = step,
2323
2324 .assert_reset = assert_reset,
2325 .deassert_reset = deassert_reset,
2326
2327 .read_memory = read_memory,
2328 .write_memory = write_memory,
2329
2330 .arch_state = arch_state,
2331 };
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