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target|board: Add Intel (Altera) Arria 10 target and related board
[openocd.git] / src / target / riscv / riscv-011.c
1 /*
2 * Support for RISC-V, debug version 0.11. This was never an officially adopted
3 * spec, but SiFive made some silicon that uses it.
4 */
5
6 #include <assert.h>
7 #include <stdlib.h>
8 #include <time.h>
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "target/target.h"
15 #include "target/algorithm.h"
16 #include "target/target_type.h"
17 #include "log.h"
18 #include "jtag/jtag.h"
19 #include "target/register.h"
20 #include "target/breakpoints.h"
21 #include "helper/time_support.h"
22 #include "riscv.h"
23 #include "asm.h"
24 #include "gdb_regs.h"
25
26 /**
27 * Since almost everything can be accomplish by scanning the dbus register, all
28 * functions here assume dbus is already selected. The exception are functions
29 * called directly by OpenOCD, which can't assume anything about what's
30 * currently in IR. They should set IR to dbus explicitly.
31 */
32
33 /**
34 * Code structure
35 *
36 * At the bottom of the stack are the OpenOCD JTAG functions:
37 * jtag_add_[id]r_scan
38 * jtag_execute_query
39 * jtag_add_runtest
40 *
41 * There are a few functions to just instantly shift a register and get its
42 * value:
43 * dtmcontrol_scan
44 * idcode_scan
45 * dbus_scan
46 *
47 * Because doing one scan and waiting for the result is slow, most functions
48 * batch up a bunch of dbus writes and then execute them all at once. They use
49 * the scans "class" for this:
50 * scans_new
51 * scans_delete
52 * scans_execute
53 * scans_add_...
54 * Usually you new(), call a bunch of add functions, then execute() and look
55 * at the results by calling scans_get...()
56 *
57 * Optimized functions will directly use the scans class above, but slightly
58 * lazier code will use the cache functions that in turn use the scans
59 * functions:
60 * cache_get...
61 * cache_set...
62 * cache_write
63 * cache_set... update a local structure, which is then synced to the target
64 * with cache_write(). Only Debug RAM words that are actually changed are sent
65 * to the target. Afterwards use cache_get... to read results.
66 */
67
68 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
69 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
70
71 #define DIM(x) (sizeof(x)/sizeof(*x))
72
73 /* Constants for legacy SiFive hardware breakpoints. */
74 #define CSR_BPCONTROL_X (1<<0)
75 #define CSR_BPCONTROL_W (1<<1)
76 #define CSR_BPCONTROL_R (1<<2)
77 #define CSR_BPCONTROL_U (1<<3)
78 #define CSR_BPCONTROL_S (1<<4)
79 #define CSR_BPCONTROL_H (1<<5)
80 #define CSR_BPCONTROL_M (1<<6)
81 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
82 #define CSR_BPCONTROL_BPACTION (0xff<<11)
83
84 #define DEBUG_ROM_START 0x800
85 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
86 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
87 #define DEBUG_RAM_START 0x400
88
89 #define SETHALTNOT 0x10c
90
91 /*** JTAG registers. ***/
92
93 #define DTMCONTROL 0x10
94 #define DTMCONTROL_DBUS_RESET (1<<16)
95 #define DTMCONTROL_IDLE (7<<10)
96 #define DTMCONTROL_ADDRBITS (0xf<<4)
97 #define DTMCONTROL_VERSION (0xf)
98
99 #define DBUS 0x11
100 #define DBUS_OP_START 0
101 #define DBUS_OP_SIZE 2
102 typedef enum {
103 DBUS_OP_NOP = 0,
104 DBUS_OP_READ = 1,
105 DBUS_OP_WRITE = 2
106 } dbus_op_t;
107 typedef enum {
108 DBUS_STATUS_SUCCESS = 0,
109 DBUS_STATUS_FAILED = 2,
110 DBUS_STATUS_BUSY = 3
111 } dbus_status_t;
112 #define DBUS_DATA_START 2
113 #define DBUS_DATA_SIZE 34
114 #define DBUS_ADDRESS_START 36
115
116 typedef enum {
117 RE_OK,
118 RE_FAIL,
119 RE_AGAIN
120 } riscv_error_t;
121
122 typedef enum slot {
123 SLOT0,
124 SLOT1,
125 SLOT_LAST,
126 } slot_t;
127
128 /*** Debug Bus registers. ***/
129
130 #define DMCONTROL 0x10
131 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
132 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
133 #define DMCONTROL_BUSERROR (7<<19)
134 #define DMCONTROL_SERIAL (3<<16)
135 #define DMCONTROL_AUTOINCREMENT (1<<15)
136 #define DMCONTROL_ACCESS (7<<12)
137 #define DMCONTROL_HARTID (0x3ff<<2)
138 #define DMCONTROL_NDRESET (1<<1)
139 #define DMCONTROL_FULLRESET 1
140
141 #define DMINFO 0x11
142 #define DMINFO_ABUSSIZE (0x7fU<<25)
143 #define DMINFO_SERIALCOUNT (0xf<<21)
144 #define DMINFO_ACCESS128 (1<<20)
145 #define DMINFO_ACCESS64 (1<<19)
146 #define DMINFO_ACCESS32 (1<<18)
147 #define DMINFO_ACCESS16 (1<<17)
148 #define DMINFO_ACCESS8 (1<<16)
149 #define DMINFO_DRAMSIZE (0x3f<<10)
150 #define DMINFO_AUTHENTICATED (1<<5)
151 #define DMINFO_AUTHBUSY (1<<4)
152 #define DMINFO_AUTHTYPE (3<<2)
153 #define DMINFO_VERSION 3
154
155 /*** Info about the core being debugged. ***/
156
157 #define DBUS_ADDRESS_UNKNOWN 0xffff
158
159 #define DRAM_CACHE_SIZE 16
160
161 struct trigger {
162 uint64_t address;
163 uint32_t length;
164 uint64_t mask;
165 uint64_t value;
166 bool read, write, execute;
167 int unique_id;
168 };
169
170 struct memory_cache_line {
171 uint32_t data;
172 bool valid;
173 bool dirty;
174 };
175
176 typedef struct {
177 /* Number of address bits in the dbus register. */
178 uint8_t addrbits;
179 /* Number of words in Debug RAM. */
180 unsigned int dramsize;
181 uint64_t dcsr;
182 uint64_t dpc;
183 uint64_t tselect;
184 bool tselect_dirty;
185 /* The value that mstatus actually has on the target right now. This is not
186 * the value we present to the user. That one may be stored in the
187 * reg_cache. */
188 uint64_t mstatus_actual;
189
190 struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
191
192 /* Number of run-test/idle cycles the target requests we do after each dbus
193 * access. */
194 unsigned int dtmcontrol_idle;
195
196 /* This value is incremented every time a dbus access comes back as "busy".
197 * It's used to determine how many run-test/idle cycles to feed the target
198 * in between accesses. */
199 unsigned int dbus_busy_delay;
200
201 /* This value is incremented every time we read the debug interrupt as
202 * high. It's used to add extra run-test/idle cycles after setting debug
203 * interrupt high, so ideally we never have to perform a whole extra scan
204 * before the interrupt is cleared. */
205 unsigned int interrupt_high_delay;
206
207 bool need_strict_step;
208 bool never_halted;
209 } riscv011_info_t;
210
211 typedef struct {
212 bool haltnot;
213 bool interrupt;
214 } bits_t;
215
216 /*** Necessary prototypes. ***/
217
218 static int poll_target(struct target *target, bool announce);
219 static int riscv011_poll(struct target *target);
220 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
221 int regid);
222
223 /*** Utility functions. ***/
224
225 #define DEBUG_LENGTH 264
226
227 static riscv011_info_t *get_info(const struct target *target)
228 {
229 riscv_info_t *info = (riscv_info_t *) target->arch_info;
230 return (riscv011_info_t *) info->version_specific;
231 }
232
233 static unsigned int slot_offset(const struct target *target, slot_t slot)
234 {
235 riscv011_info_t *info = get_info(target);
236 switch (riscv_xlen(target)) {
237 case 32:
238 switch (slot) {
239 case SLOT0: return 4;
240 case SLOT1: return 5;
241 case SLOT_LAST: return info->dramsize-1;
242 }
243 case 64:
244 switch (slot) {
245 case SLOT0: return 4;
246 case SLOT1: return 6;
247 case SLOT_LAST: return info->dramsize-2;
248 }
249 }
250 LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
251 riscv_xlen(target), slot);
252 assert(0);
253 return 0; /* Silence -Werror=return-type */
254 }
255
256 static uint32_t load_slot(const struct target *target, unsigned int dest,
257 slot_t slot)
258 {
259 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
260 return load(target, dest, ZERO, offset);
261 }
262
263 static uint32_t store_slot(const struct target *target, unsigned int src,
264 slot_t slot)
265 {
266 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
267 return store(target, src, ZERO, offset);
268 }
269
270 static uint16_t dram_address(unsigned int index)
271 {
272 if (index < 0x10)
273 return index;
274 else
275 return 0x40 + index - 0x10;
276 }
277
278 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
279 {
280 struct scan_field field;
281 uint8_t in_value[4];
282 uint8_t out_value[4];
283
284 buf_set_u32(out_value, 0, 32, out);
285
286 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
287
288 field.num_bits = 32;
289 field.out_value = out_value;
290 field.in_value = in_value;
291 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
292
293 /* Always return to dbus. */
294 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
295
296 int retval = jtag_execute_queue();
297 if (retval != ERROR_OK) {
298 LOG_ERROR("failed jtag scan: %d", retval);
299 return retval;
300 }
301
302 uint32_t in = buf_get_u32(field.in_value, 0, 32);
303 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
304
305 return in;
306 }
307
308 static uint32_t idcode_scan(struct target *target)
309 {
310 struct scan_field field;
311 uint8_t in_value[4];
312
313 jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
314
315 field.num_bits = 32;
316 field.out_value = NULL;
317 field.in_value = in_value;
318 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
319
320 int retval = jtag_execute_queue();
321 if (retval != ERROR_OK) {
322 LOG_ERROR("failed jtag scan: %d", retval);
323 return retval;
324 }
325
326 /* Always return to dbus. */
327 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
328
329 uint32_t in = buf_get_u32(field.in_value, 0, 32);
330 LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
331
332 return in;
333 }
334
335 static void increase_dbus_busy_delay(struct target *target)
336 {
337 riscv011_info_t *info = get_info(target);
338 info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
339 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
340 info->dtmcontrol_idle, info->dbus_busy_delay,
341 info->interrupt_high_delay);
342
343 dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
344 }
345
346 static void increase_interrupt_high_delay(struct target *target)
347 {
348 riscv011_info_t *info = get_info(target);
349 info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
350 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
351 info->dtmcontrol_idle, info->dbus_busy_delay,
352 info->interrupt_high_delay);
353 }
354
355 static void add_dbus_scan(const struct target *target, struct scan_field *field,
356 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
357 uint16_t address, uint64_t data)
358 {
359 riscv011_info_t *info = get_info(target);
360
361 field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
362 field->in_value = in_value;
363 field->out_value = out_value;
364
365 buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
366 buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
367 buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
368
369 jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
370
371 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
372 if (data & DMCONTROL_INTERRUPT)
373 idle_count += info->interrupt_high_delay;
374
375 if (idle_count)
376 jtag_add_runtest(idle_count, TAP_IDLE);
377 }
378
379 static void dump_field(const struct scan_field *field)
380 {
381 static const char * const op_string[] = {"nop", "r", "w", "?"};
382 static const char * const status_string[] = {"+", "?", "F", "b"};
383
384 if (debug_level < LOG_LVL_DEBUG)
385 return;
386
387 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
388 unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
389 char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
390 char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
391 unsigned int out_data = out >> 2;
392 unsigned int out_address = out >> DBUS_ADDRESS_START;
393 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
394 unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
395 char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
396 char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
397 unsigned int in_data = in >> 2;
398 unsigned int in_address = in >> DBUS_ADDRESS_START;
399
400 log_printf_lf(LOG_LVL_DEBUG,
401 __FILE__, __LINE__, "scan",
402 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
403 field->num_bits,
404 op_string[out_op], out_interrupt, out_haltnot, out_data,
405 out_address,
406 status_string[in_op], in_interrupt, in_haltnot, in_data,
407 in_address);
408 }
409
410 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
411 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
412 {
413 riscv011_info_t *info = get_info(target);
414 uint8_t in[8] = {0};
415 uint8_t out[8];
416 struct scan_field field = {
417 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
418 .out_value = out,
419 .in_value = in
420 };
421
422 assert(info->addrbits != 0);
423
424 buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
425 buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
426 buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
427
428 /* Assume dbus is already selected. */
429 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
430
431 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
432
433 if (idle_count)
434 jtag_add_runtest(idle_count, TAP_IDLE);
435
436 int retval = jtag_execute_queue();
437 if (retval != ERROR_OK) {
438 LOG_ERROR("dbus_scan failed jtag scan");
439 return DBUS_STATUS_FAILED;
440 }
441
442 if (data_in)
443 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
444
445 if (address_in)
446 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
447
448 dump_field(&field);
449
450 return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
451 }
452
453 static uint64_t dbus_read(struct target *target, uint16_t address)
454 {
455 uint64_t value;
456 dbus_status_t status;
457 uint16_t address_in;
458
459 /* If the previous read/write was to the same address, we will get the read data
460 * from the previous access.
461 * While somewhat nonintuitive, this is an efficient way to get the data.
462 */
463
464 unsigned i = 0;
465 do {
466 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
467 if (status == DBUS_STATUS_BUSY)
468 increase_dbus_busy_delay(target);
469 if (status == DBUS_STATUS_FAILED) {
470 LOG_ERROR("dbus_read(0x%x) failed!", address);
471 return 0;
472 }
473 } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
474 i++ < 256);
475
476 if (status != DBUS_STATUS_SUCCESS)
477 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
478
479 return value;
480 }
481
482 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
483 {
484 dbus_status_t status = DBUS_STATUS_BUSY;
485 unsigned i = 0;
486 while (status == DBUS_STATUS_BUSY && i++ < 256) {
487 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
488 if (status == DBUS_STATUS_BUSY)
489 increase_dbus_busy_delay(target);
490 }
491 if (status != DBUS_STATUS_SUCCESS)
492 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
493 }
494
495 /*** scans "class" ***/
496
497 typedef struct {
498 /* Number of scans that space is reserved for. */
499 unsigned int scan_count;
500 /* Size reserved in memory for each scan, in bytes. */
501 unsigned int scan_size;
502 unsigned int next_scan;
503 uint8_t *in;
504 uint8_t *out;
505 struct scan_field *field;
506 const struct target *target;
507 } scans_t;
508
509 static scans_t *scans_new(struct target *target, unsigned int scan_count)
510 {
511 scans_t *scans = malloc(sizeof(scans_t));
512 scans->scan_count = scan_count;
513 /* This code also gets called before xlen is detected. */
514 if (riscv_xlen(target))
515 scans->scan_size = 2 + riscv_xlen(target) / 8;
516 else
517 scans->scan_size = 2 + 128 / 8;
518 scans->next_scan = 0;
519 scans->in = calloc(scans->scan_size, scans->scan_count);
520 scans->out = calloc(scans->scan_size, scans->scan_count);
521 scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
522 scans->target = target;
523 return scans;
524 }
525
526 static scans_t *scans_delete(scans_t *scans)
527 {
528 assert(scans);
529 free(scans->field);
530 free(scans->out);
531 free(scans->in);
532 free(scans);
533 return NULL;
534 }
535
536 static void scans_reset(scans_t *scans)
537 {
538 scans->next_scan = 0;
539 }
540
541 static void scans_dump(scans_t *scans)
542 {
543 for (unsigned int i = 0; i < scans->next_scan; i++)
544 dump_field(&scans->field[i]);
545 }
546
547 static int scans_execute(scans_t *scans)
548 {
549 int retval = jtag_execute_queue();
550 if (retval != ERROR_OK) {
551 LOG_ERROR("failed jtag scan: %d", retval);
552 return retval;
553 }
554
555 scans_dump(scans);
556
557 return ERROR_OK;
558 }
559
560 /** Add a 32-bit dbus write to the scans structure. */
561 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
562 bool set_interrupt)
563 {
564 const unsigned int i = scans->next_scan;
565 int data_offset = scans->scan_size * i;
566 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
567 scans->in + data_offset, DBUS_OP_WRITE, address,
568 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
569 scans->next_scan++;
570 assert(scans->next_scan <= scans->scan_count);
571 }
572
573 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
574 * debug RAM. */
575 static void scans_add_write_jump(scans_t *scans, uint16_t address,
576 bool set_interrupt)
577 {
578 scans_add_write32(scans, address,
579 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
580 set_interrupt);
581 }
582
583 /** Add a 32-bit dbus write for an instruction that loads from the indicated
584 * slot. */
585 static void scans_add_write_load(scans_t *scans, uint16_t address,
586 unsigned int reg, slot_t slot, bool set_interrupt)
587 {
588 scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
589 set_interrupt);
590 }
591
592 /** Add a 32-bit dbus write for an instruction that stores to the indicated
593 * slot. */
594 static void scans_add_write_store(scans_t *scans, uint16_t address,
595 unsigned int reg, slot_t slot, bool set_interrupt)
596 {
597 scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
598 set_interrupt);
599 }
600
601 /** Add a 32-bit dbus read. */
602 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
603 {
604 assert(scans->next_scan < scans->scan_count);
605 const unsigned int i = scans->next_scan;
606 int data_offset = scans->scan_size * i;
607 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
608 scans->in + data_offset, DBUS_OP_READ, address,
609 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
610 scans->next_scan++;
611 }
612
613 /** Add one or more scans to read the indicated slot. */
614 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
615 {
616 const struct target *target = scans->target;
617 switch (riscv_xlen(target)) {
618 case 32:
619 scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
620 break;
621 case 64:
622 scans_add_read32(scans, slot_offset(target, slot), false);
623 scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
624 break;
625 }
626 }
627
628 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
629 unsigned first, unsigned num)
630 {
631 return buf_get_u32(scans->in + scans->scan_size * index, first, num);
632 }
633
634 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
635 unsigned first, unsigned num)
636 {
637 return buf_get_u64(scans->in + scans->scan_size * index, first, num);
638 }
639
640 /*** end of scans class ***/
641
642 static uint32_t dram_read32(struct target *target, unsigned int index)
643 {
644 uint16_t address = dram_address(index);
645 uint32_t value = dbus_read(target, address);
646 return value;
647 }
648
649 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
650 bool set_interrupt)
651 {
652 uint64_t dbus_value = DMCONTROL_HALTNOT | value;
653 if (set_interrupt)
654 dbus_value |= DMCONTROL_INTERRUPT;
655 dbus_write(target, dram_address(index), dbus_value);
656 }
657
658 /** Read the haltnot and interrupt bits. */
659 static bits_t read_bits(struct target *target)
660 {
661 uint64_t value;
662 dbus_status_t status;
663 uint16_t address_in;
664 riscv011_info_t *info = get_info(target);
665
666 bits_t err_result = {
667 .haltnot = 0,
668 .interrupt = 0
669 };
670
671 do {
672 unsigned i = 0;
673 do {
674 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
675 if (status == DBUS_STATUS_BUSY) {
676 if (address_in == (1<<info->addrbits) - 1 &&
677 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
678 LOG_ERROR("TDO seems to be stuck high.");
679 return err_result;
680 }
681 increase_dbus_busy_delay(target);
682 } else if (status == DBUS_STATUS_FAILED) {
683 /* TODO: return an actual error */
684 return err_result;
685 }
686 } while (status == DBUS_STATUS_BUSY && i++ < 256);
687
688 if (i >= 256) {
689 LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
690 return err_result;
691 }
692 } while (address_in > 0x10 && address_in != DMCONTROL);
693
694 bits_t result = {
695 .haltnot = get_field(value, DMCONTROL_HALTNOT),
696 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
697 };
698 return result;
699 }
700
701 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
702 {
703 time_t start = time(NULL);
704 if (ignore_first) {
705 /* Throw away the results of the first read, since they'll contain the
706 * result of the read that happened just before debugint was set.
707 * (Assuming the last scan before calling this function was one that
708 * sets debugint.) */
709 read_bits(target);
710 }
711 while (1) {
712 bits_t bits = read_bits(target);
713 if (!bits.interrupt)
714 return ERROR_OK;
715 if (time(NULL) - start > riscv_command_timeout_sec) {
716 LOG_ERROR("Timed out waiting for debug int to clear."
717 "Increase timeout with riscv set_command_timeout_sec.");
718 return ERROR_FAIL;
719 }
720 }
721 }
722
723 static int dram_check32(struct target *target, unsigned int index,
724 uint32_t expected)
725 {
726 uint16_t address = dram_address(index);
727 uint32_t actual = dbus_read(target, address);
728 if (expected != actual) {
729 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
730 expected, index, actual);
731 return ERROR_FAIL;
732 }
733 return ERROR_OK;
734 }
735
736 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
737 {
738 riscv011_info_t *info = get_info(target);
739 if (info->dram_cache[index].valid &&
740 info->dram_cache[index].data == data) {
741 /* This is already preset on the target. */
742 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
743 return;
744 }
745 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
746 info->dram_cache[index].data = data;
747 info->dram_cache[index].valid = true;
748 info->dram_cache[index].dirty = true;
749 }
750
751 static void cache_set(struct target *target, slot_t slot, uint64_t data)
752 {
753 unsigned int offset = slot_offset(target, slot);
754 cache_set32(target, offset, data);
755 if (riscv_xlen(target) > 32)
756 cache_set32(target, offset + 1, data >> 32);
757 }
758
759 static void cache_set_jump(struct target *target, unsigned int index)
760 {
761 cache_set32(target, index,
762 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
763 }
764
765 static void cache_set_load(struct target *target, unsigned int index,
766 unsigned int reg, slot_t slot)
767 {
768 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
769 cache_set32(target, index, load(target, reg, ZERO, offset));
770 }
771
772 static void cache_set_store(struct target *target, unsigned int index,
773 unsigned int reg, slot_t slot)
774 {
775 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
776 cache_set32(target, index, store(target, reg, ZERO, offset));
777 }
778
779 static void dump_debug_ram(struct target *target)
780 {
781 for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
782 uint32_t value = dram_read32(target, i);
783 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
784 }
785 }
786
787 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
788 static void cache_invalidate(struct target *target)
789 {
790 riscv011_info_t *info = get_info(target);
791 for (unsigned int i = 0; i < info->dramsize; i++) {
792 info->dram_cache[i].valid = false;
793 info->dram_cache[i].dirty = false;
794 }
795 }
796
797 /* Called by cache_write() after the program has run. Also call this if you're
798 * running programs without calling cache_write(). */
799 static void cache_clean(struct target *target)
800 {
801 riscv011_info_t *info = get_info(target);
802 for (unsigned int i = 0; i < info->dramsize; i++) {
803 if (i >= 4)
804 info->dram_cache[i].valid = false;
805 info->dram_cache[i].dirty = false;
806 }
807 }
808
809 static int cache_check(struct target *target)
810 {
811 riscv011_info_t *info = get_info(target);
812 int error = 0;
813
814 for (unsigned int i = 0; i < info->dramsize; i++) {
815 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
816 if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
817 error++;
818 }
819 }
820
821 if (error) {
822 dump_debug_ram(target);
823 return ERROR_FAIL;
824 }
825
826 return ERROR_OK;
827 }
828
829 /** Write cache to the target, and optionally run the program.
830 * Then read the value at address into the cache, assuming address < 128. */
831 #define CACHE_NO_READ 128
832 static int cache_write(struct target *target, unsigned int address, bool run)
833 {
834 LOG_DEBUG("enter");
835 riscv011_info_t *info = get_info(target);
836 scans_t *scans = scans_new(target, info->dramsize + 2);
837
838 unsigned int last = info->dramsize;
839 for (unsigned int i = 0; i < info->dramsize; i++) {
840 if (info->dram_cache[i].dirty)
841 last = i;
842 }
843
844 if (last == info->dramsize) {
845 /* Nothing needs to be written to RAM. */
846 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
847
848 } else {
849 for (unsigned int i = 0; i < info->dramsize; i++) {
850 if (info->dram_cache[i].dirty) {
851 bool set_interrupt = (i == last && run);
852 scans_add_write32(scans, i, info->dram_cache[i].data,
853 set_interrupt);
854 }
855 }
856 }
857
858 if (run || address < CACHE_NO_READ) {
859 /* Throw away the results of the first read, since it'll contain the
860 * result of the read that happened just before debugint was set. */
861 scans_add_read32(scans, address, false);
862
863 /* This scan contains the results of the read the caller requested, as
864 * well as an interrupt bit worth looking at. */
865 scans_add_read32(scans, address, false);
866 }
867
868 int retval = scans_execute(scans);
869 if (retval != ERROR_OK) {
870 scans_delete(scans);
871 LOG_ERROR("JTAG execute failed.");
872 return retval;
873 }
874
875 int errors = 0;
876 for (unsigned int i = 0; i < scans->next_scan; i++) {
877 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
878 DBUS_OP_SIZE);
879 switch (status) {
880 case DBUS_STATUS_SUCCESS:
881 break;
882 case DBUS_STATUS_FAILED:
883 LOG_ERROR("Debug RAM write failed. Hardware error?");
884 scans_delete(scans);
885 return ERROR_FAIL;
886 case DBUS_STATUS_BUSY:
887 errors++;
888 break;
889 default:
890 LOG_ERROR("Got invalid bus access status: %d", status);
891 scans_delete(scans);
892 return ERROR_FAIL;
893 }
894 }
895
896 if (errors) {
897 increase_dbus_busy_delay(target);
898
899 /* Try again, using the slow careful code.
900 * Write all RAM, just to be extra cautious. */
901 for (unsigned int i = 0; i < info->dramsize; i++) {
902 if (i == last && run)
903 dram_write32(target, last, info->dram_cache[last].data, true);
904 else
905 dram_write32(target, i, info->dram_cache[i].data, false);
906 info->dram_cache[i].dirty = false;
907 }
908 if (run)
909 cache_clean(target);
910
911 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
912 LOG_ERROR("Debug interrupt didn't clear.");
913 dump_debug_ram(target);
914 scans_delete(scans);
915 return ERROR_FAIL;
916 }
917
918 } else {
919 if (run) {
920 cache_clean(target);
921 } else {
922 for (unsigned int i = 0; i < info->dramsize; i++)
923 info->dram_cache[i].dirty = false;
924 }
925
926 if (run || address < CACHE_NO_READ) {
927 int interrupt = scans_get_u32(scans, scans->next_scan-1,
928 DBUS_DATA_START + 33, 1);
929 if (interrupt) {
930 increase_interrupt_high_delay(target);
931 /* Slow path wait for it to clear. */
932 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
933 LOG_ERROR("Debug interrupt didn't clear.");
934 dump_debug_ram(target);
935 scans_delete(scans);
936 return ERROR_FAIL;
937 }
938 } else {
939 /* We read a useful value in that last scan. */
940 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
941 DBUS_ADDRESS_START, info->addrbits);
942 if (read_addr != address) {
943 LOG_INFO("Got data from 0x%x but expected it from 0x%x",
944 read_addr, address);
945 }
946 info->dram_cache[read_addr].data =
947 scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
948 info->dram_cache[read_addr].valid = true;
949 }
950 }
951 }
952
953 scans_delete(scans);
954 LOG_DEBUG("exit");
955
956 return ERROR_OK;
957 }
958
959 static uint32_t cache_get32(struct target *target, unsigned int address)
960 {
961 riscv011_info_t *info = get_info(target);
962 if (!info->dram_cache[address].valid) {
963 info->dram_cache[address].data = dram_read32(target, address);
964 info->dram_cache[address].valid = true;
965 }
966 return info->dram_cache[address].data;
967 }
968
969 static uint64_t cache_get(struct target *target, slot_t slot)
970 {
971 unsigned int offset = slot_offset(target, slot);
972 uint64_t value = cache_get32(target, offset);
973 if (riscv_xlen(target) > 32)
974 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
975 return value;
976 }
977
978 /* Write instruction that jumps from the specified word in Debug RAM to resume
979 * in Debug ROM. */
980 static void dram_write_jump(struct target *target, unsigned int index,
981 bool set_interrupt)
982 {
983 dram_write32(target, index,
984 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
985 set_interrupt);
986 }
987
988 static int wait_for_state(struct target *target, enum target_state state)
989 {
990 time_t start = time(NULL);
991 while (1) {
992 int result = riscv011_poll(target);
993 if (result != ERROR_OK)
994 return result;
995 if (target->state == state)
996 return ERROR_OK;
997 if (time(NULL) - start > riscv_command_timeout_sec) {
998 LOG_ERROR("Timed out waiting for state %d. "
999 "Increase timeout with riscv set_command_timeout_sec.", state);
1000 return ERROR_FAIL;
1001 }
1002 }
1003 }
1004
1005 static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
1006 {
1007 riscv011_info_t *info = get_info(target);
1008 cache_set32(target, 0, csrr(S0, csr));
1009 cache_set_store(target, 1, S0, SLOT0);
1010 cache_set_jump(target, 2);
1011 if (cache_write(target, 4, true) != ERROR_OK)
1012 return ERROR_FAIL;
1013 *value = cache_get(target, SLOT0);
1014 LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1015
1016 uint32_t exception = cache_get32(target, info->dramsize-1);
1017 if (exception) {
1018 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1019 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1020 *value = ~0;
1021 return ERROR_FAIL;
1022 }
1023
1024 return ERROR_OK;
1025 }
1026
1027 static int write_csr(struct target *target, uint32_t csr, uint64_t value)
1028 {
1029 LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1030 cache_set_load(target, 0, S0, SLOT0);
1031 cache_set32(target, 1, csrw(S0, csr));
1032 cache_set_jump(target, 2);
1033 cache_set(target, SLOT0, value);
1034 if (cache_write(target, 4, true) != ERROR_OK)
1035 return ERROR_FAIL;
1036
1037 return ERROR_OK;
1038 }
1039
1040 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1041 {
1042 cache_set_load(target, 0, gpr, SLOT0);
1043 cache_set_jump(target, 1);
1044 cache_set(target, SLOT0, value);
1045 if (cache_write(target, 4, true) != ERROR_OK)
1046 return ERROR_FAIL;
1047 return ERROR_OK;
1048 }
1049
1050 static int maybe_read_tselect(struct target *target)
1051 {
1052 riscv011_info_t *info = get_info(target);
1053
1054 if (info->tselect_dirty) {
1055 int result = read_csr(target, &info->tselect, CSR_TSELECT);
1056 if (result != ERROR_OK)
1057 return result;
1058 info->tselect_dirty = false;
1059 }
1060
1061 return ERROR_OK;
1062 }
1063
1064 static int maybe_write_tselect(struct target *target)
1065 {
1066 riscv011_info_t *info = get_info(target);
1067
1068 if (!info->tselect_dirty) {
1069 int result = write_csr(target, CSR_TSELECT, info->tselect);
1070 if (result != ERROR_OK)
1071 return result;
1072 info->tselect_dirty = true;
1073 }
1074
1075 return ERROR_OK;
1076 }
1077
1078 static int execute_resume(struct target *target, bool step)
1079 {
1080 riscv011_info_t *info = get_info(target);
1081
1082 LOG_DEBUG("step=%d", step);
1083
1084 maybe_write_tselect(target);
1085
1086 /* TODO: check if dpc is dirty (which also is true if an exception was hit
1087 * at any time) */
1088 cache_set_load(target, 0, S0, SLOT0);
1089 cache_set32(target, 1, csrw(S0, CSR_DPC));
1090 cache_set_jump(target, 2);
1091 cache_set(target, SLOT0, info->dpc);
1092 if (cache_write(target, 4, true) != ERROR_OK)
1093 return ERROR_FAIL;
1094
1095 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1096 if (mstatus_reg->valid) {
1097 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1098 if (mstatus_user != info->mstatus_actual) {
1099 cache_set_load(target, 0, S0, SLOT0);
1100 cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1101 cache_set_jump(target, 2);
1102 cache_set(target, SLOT0, mstatus_user);
1103 if (cache_write(target, 4, true) != ERROR_OK)
1104 return ERROR_FAIL;
1105 }
1106 }
1107
1108 info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
1109 info->dcsr &= ~DCSR_HALT;
1110
1111 if (step)
1112 info->dcsr |= DCSR_STEP;
1113 else
1114 info->dcsr &= ~DCSR_STEP;
1115
1116 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1117 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1118 dram_write32(target, 2, fence_i(), false);
1119 dram_write_jump(target, 3, false);
1120
1121 /* Write DCSR value, set interrupt and clear haltnot. */
1122 uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1123 dbus_write(target, dram_address(4), dbus_value);
1124
1125 cache_invalidate(target);
1126
1127 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1128 LOG_ERROR("Debug interrupt didn't clear.");
1129 return ERROR_FAIL;
1130 }
1131
1132 target->state = TARGET_RUNNING;
1133 register_cache_invalidate(target->reg_cache);
1134
1135 return ERROR_OK;
1136 }
1137
1138 /* Execute a step, and wait for reentry into Debug Mode. */
1139 static int full_step(struct target *target, bool announce)
1140 {
1141 int result = execute_resume(target, true);
1142 if (result != ERROR_OK)
1143 return result;
1144 time_t start = time(NULL);
1145 while (1) {
1146 result = poll_target(target, announce);
1147 if (result != ERROR_OK)
1148 return result;
1149 if (target->state != TARGET_DEBUG_RUNNING)
1150 break;
1151 if (time(NULL) - start > riscv_command_timeout_sec) {
1152 LOG_ERROR("Timed out waiting for step to complete."
1153 "Increase timeout with riscv set_command_timeout_sec");
1154 return ERROR_FAIL;
1155 }
1156 }
1157 return ERROR_OK;
1158 }
1159
1160 static int resume(struct target *target, int debug_execution, bool step)
1161 {
1162 if (debug_execution) {
1163 LOG_ERROR("TODO: debug_execution is true");
1164 return ERROR_FAIL;
1165 }
1166
1167 return execute_resume(target, step);
1168 }
1169
1170 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1171 {
1172 struct reg *r = &target->reg_cache->reg_list[number];
1173 if (!r->valid) {
1174 LOG_ERROR("Register cache entry for %d is invalid!", number);
1175 assert(r->valid);
1176 }
1177 uint64_t value = buf_get_u64(r->value, 0, r->size);
1178 LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1179 return value;
1180 }
1181
1182 static void reg_cache_set(struct target *target, unsigned int number,
1183 uint64_t value)
1184 {
1185 struct reg *r = &target->reg_cache->reg_list[number];
1186 LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1187 r->valid = true;
1188 buf_set_u64(r->value, 0, r->size, value);
1189 }
1190
1191 static int update_mstatus_actual(struct target *target)
1192 {
1193 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1194 if (mstatus_reg->valid) {
1195 /* We previously made it valid. */
1196 return ERROR_OK;
1197 }
1198
1199 /* Force reading the register. In that process mstatus_actual will be
1200 * updated. */
1201 riscv_reg_t mstatus;
1202 return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
1203 }
1204
1205 /*** OpenOCD target functions. ***/
1206
1207 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1208 {
1209 riscv011_info_t *info = get_info(target);
1210 if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1211 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1212 cache_set_store(target, 1, S0, SLOT0);
1213 cache_set_jump(target, 2);
1214 } else {
1215 LOG_ERROR("Don't know how to read register %d", regnum);
1216 return ERROR_FAIL;
1217 }
1218
1219 if (cache_write(target, 4, true) != ERROR_OK)
1220 return ERROR_FAIL;
1221
1222 uint32_t exception = cache_get32(target, info->dramsize-1);
1223 if (exception) {
1224 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1225 *value = ~0;
1226 return ERROR_FAIL;
1227 }
1228
1229 *value = cache_get(target, SLOT0);
1230 LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1231
1232 if (regnum == GDB_REGNO_MSTATUS)
1233 info->mstatus_actual = *value;
1234
1235 return ERROR_OK;
1236 }
1237
1238 /* Write the register. No caching or games. */
1239 static int register_write(struct target *target, unsigned int number,
1240 uint64_t value)
1241 {
1242 riscv011_info_t *info = get_info(target);
1243
1244 maybe_write_tselect(target);
1245
1246 if (number == S0) {
1247 cache_set_load(target, 0, S0, SLOT0);
1248 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
1249 cache_set_jump(target, 2);
1250 } else if (number == S1) {
1251 cache_set_load(target, 0, S0, SLOT0);
1252 cache_set_store(target, 1, S0, SLOT_LAST);
1253 cache_set_jump(target, 2);
1254 } else if (number <= GDB_REGNO_XPR31) {
1255 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1256 cache_set_jump(target, 1);
1257 } else if (number == GDB_REGNO_PC) {
1258 info->dpc = value;
1259 return ERROR_OK;
1260 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1261 int result = update_mstatus_actual(target);
1262 if (result != ERROR_OK)
1263 return result;
1264 unsigned i = 0;
1265 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1266 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1267 cache_set_load(target, i++, S0, SLOT1);
1268 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1269 cache_set(target, SLOT1, info->mstatus_actual);
1270 }
1271
1272 if (riscv_xlen(target) == 32)
1273 cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1274 else
1275 cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1276 cache_set_jump(target, i++);
1277 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1278 cache_set_load(target, 0, S0, SLOT0);
1279 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1280 cache_set_jump(target, 2);
1281
1282 if (number == GDB_REGNO_MSTATUS)
1283 info->mstatus_actual = value;
1284 } else if (number == GDB_REGNO_PRIV) {
1285 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1286 return ERROR_OK;
1287 } else {
1288 LOG_ERROR("Don't know how to write register %d", number);
1289 return ERROR_FAIL;
1290 }
1291
1292 cache_set(target, SLOT0, value);
1293 if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1294 return ERROR_FAIL;
1295
1296 uint32_t exception = cache_get32(target, info->dramsize-1);
1297 if (exception) {
1298 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1299 gdb_regno_name(number));
1300 return ERROR_FAIL;
1301 }
1302
1303 return ERROR_OK;
1304 }
1305
1306 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
1307 int regid)
1308 {
1309 assert(hartid == 0);
1310 riscv011_info_t *info = get_info(target);
1311
1312 maybe_write_tselect(target);
1313
1314 if (regid <= GDB_REGNO_XPR31) {
1315 *value = reg_cache_get(target, regid);
1316 } else if (regid == GDB_REGNO_PC) {
1317 *value = info->dpc;
1318 } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1319 int result = update_mstatus_actual(target);
1320 if (result != ERROR_OK)
1321 return result;
1322 unsigned i = 0;
1323 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1324 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1325 cache_set_load(target, i++, S0, SLOT1);
1326 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1327 cache_set(target, SLOT1, info->mstatus_actual);
1328 }
1329
1330 if (riscv_xlen(target) == 32)
1331 cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1332 else
1333 cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1334 cache_set_jump(target, i++);
1335
1336 if (cache_write(target, 4, true) != ERROR_OK)
1337 return ERROR_FAIL;
1338 } else if (regid == GDB_REGNO_PRIV) {
1339 *value = get_field(info->dcsr, DCSR_PRV);
1340 } else {
1341 int result = register_read(target, value, regid);
1342 if (result != ERROR_OK)
1343 return result;
1344 }
1345
1346 if (regid == GDB_REGNO_MSTATUS)
1347 target->reg_cache->reg_list[regid].valid = true;
1348
1349 return ERROR_OK;
1350 }
1351
1352 static int set_register(struct target *target, int hartid, int regid,
1353 uint64_t value)
1354 {
1355 assert(hartid == 0);
1356 return register_write(target, regid, value);
1357 }
1358
1359 static int halt(struct target *target)
1360 {
1361 LOG_DEBUG("riscv_halt()");
1362 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1363
1364 cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1365 cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1366 cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1367 cache_set_jump(target, 3);
1368
1369 if (cache_write(target, 4, true) != ERROR_OK) {
1370 LOG_ERROR("cache_write() failed.");
1371 return ERROR_FAIL;
1372 }
1373
1374 return ERROR_OK;
1375 }
1376
1377 static int init_target(struct command_context *cmd_ctx,
1378 struct target *target)
1379 {
1380 LOG_DEBUG("init");
1381 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1382 generic_info->get_register = get_register;
1383 generic_info->set_register = set_register;
1384
1385 generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
1386 if (!generic_info->version_specific)
1387 return ERROR_FAIL;
1388
1389 /* Assume 32-bit until we discover the real value in examine(). */
1390 generic_info->xlen[0] = 32;
1391 riscv_init_registers(target);
1392
1393 return ERROR_OK;
1394 }
1395
1396 static void deinit_target(struct target *target)
1397 {
1398 LOG_DEBUG("riscv_deinit_target()");
1399 riscv_info_t *info = (riscv_info_t *) target->arch_info;
1400 free(info->version_specific);
1401 info->version_specific = NULL;
1402 }
1403
1404 static int strict_step(struct target *target, bool announce)
1405 {
1406 riscv011_info_t *info = get_info(target);
1407
1408 LOG_DEBUG("enter");
1409
1410 struct breakpoint *breakpoint = target->breakpoints;
1411 while (breakpoint) {
1412 riscv_remove_breakpoint(target, breakpoint);
1413 breakpoint = breakpoint->next;
1414 }
1415
1416 struct watchpoint *watchpoint = target->watchpoints;
1417 while (watchpoint) {
1418 riscv_remove_watchpoint(target, watchpoint);
1419 watchpoint = watchpoint->next;
1420 }
1421
1422 int result = full_step(target, announce);
1423 if (result != ERROR_OK)
1424 return result;
1425
1426 breakpoint = target->breakpoints;
1427 while (breakpoint) {
1428 riscv_add_breakpoint(target, breakpoint);
1429 breakpoint = breakpoint->next;
1430 }
1431
1432 watchpoint = target->watchpoints;
1433 while (watchpoint) {
1434 riscv_add_watchpoint(target, watchpoint);
1435 watchpoint = watchpoint->next;
1436 }
1437
1438 info->need_strict_step = false;
1439
1440 return ERROR_OK;
1441 }
1442
1443 static int step(struct target *target, int current, target_addr_t address,
1444 int handle_breakpoints)
1445 {
1446 riscv011_info_t *info = get_info(target);
1447
1448 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1449
1450 if (!current) {
1451 if (riscv_xlen(target) > 32) {
1452 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1453 riscv_xlen(target));
1454 }
1455 int result = register_write(target, GDB_REGNO_PC, address);
1456 if (result != ERROR_OK)
1457 return result;
1458 }
1459
1460 if (info->need_strict_step || handle_breakpoints) {
1461 int result = strict_step(target, true);
1462 if (result != ERROR_OK)
1463 return result;
1464 } else {
1465 return resume(target, 0, true);
1466 }
1467
1468 return ERROR_OK;
1469 }
1470
1471 static int examine(struct target *target)
1472 {
1473 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1474
1475 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1476 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1477 LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1478 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1479 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1480 if (dtmcontrol == 0) {
1481 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1482 return ERROR_FAIL;
1483 }
1484 if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1485 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1486 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1487 return ERROR_FAIL;
1488 }
1489
1490 RISCV_INFO(r);
1491 r->hart_count = 1;
1492
1493 riscv011_info_t *info = get_info(target);
1494 info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1495 info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1496 if (info->dtmcontrol_idle == 0) {
1497 /* Some old SiFive cores don't set idle but need it to be 1. */
1498 uint32_t idcode = idcode_scan(target);
1499 if (idcode == 0x10e31913)
1500 info->dtmcontrol_idle = 1;
1501 }
1502
1503 uint32_t dminfo = dbus_read(target, DMINFO);
1504 LOG_DEBUG("dminfo: 0x%08x", dminfo);
1505 LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1506 LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1507 LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1508 LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1509 LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1510 LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1511 LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1512 LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1513 LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1514 LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1515 LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1516 LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
1517
1518 if (get_field(dminfo, DMINFO_VERSION) != 1) {
1519 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1520 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1521 return ERROR_FAIL;
1522 }
1523
1524 info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1525
1526 if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1527 LOG_ERROR("Authentication required by RISC-V core but not "
1528 "supported by OpenOCD. dminfo=0x%x", dminfo);
1529 return ERROR_FAIL;
1530 }
1531
1532 /* Pretend this is a 32-bit system until we have found out the true value. */
1533 r->xlen[0] = 32;
1534
1535 /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1536 cache_set32(target, 0, xori(S1, ZERO, -1));
1537 /* 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff */
1538 cache_set32(target, 1, srli(S1, S1, 31));
1539 /* 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff */
1540 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1541 cache_set32(target, 3, srli(S1, S1, 31));
1542 /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
1543 cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1544 cache_set_jump(target, 5);
1545 for (unsigned i = 6; i < info->dramsize; i++)
1546 cache_set32(target, i, i * 0x01020304);
1547
1548 cache_write(target, 0, false);
1549
1550 /* Check that we can actually read/write dram. */
1551 if (cache_check(target) != ERROR_OK)
1552 return ERROR_FAIL;
1553
1554 cache_write(target, 0, true);
1555 cache_invalidate(target);
1556
1557 uint32_t word0 = cache_get32(target, 0);
1558 uint32_t word1 = cache_get32(target, 1);
1559 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1560 if (word0 == 1 && word1 == 0) {
1561 generic_info->xlen[0] = 32;
1562 } else if (word0 == 0xffffffff && word1 == 3) {
1563 generic_info->xlen[0] = 64;
1564 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1565 generic_info->xlen[0] = 128;
1566 } else {
1567 uint32_t exception = cache_get32(target, info->dramsize-1);
1568 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1569 word0, word1, exception);
1570 dump_debug_ram(target);
1571 return ERROR_FAIL;
1572 }
1573 LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1574
1575 if (read_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) {
1576 const unsigned old_csr_misa = 0xf10;
1577 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1578 old_csr_misa);
1579 if (read_csr(target, &r->misa[0], old_csr_misa) != ERROR_OK) {
1580 /* Maybe this is an old core that still has $misa at the old
1581 * address. */
1582 LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1583 return ERROR_FAIL;
1584 }
1585 }
1586
1587 /* Update register list to match discovered XLEN/supported extensions. */
1588 riscv_init_registers(target);
1589
1590 info->never_halted = true;
1591
1592 int result = riscv011_poll(target);
1593 if (result != ERROR_OK)
1594 return result;
1595
1596 target_set_examined(target);
1597 riscv_set_current_hartid(target, 0);
1598 for (size_t i = 0; i < 32; ++i)
1599 reg_cache_set(target, i, -1);
1600 LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1601 riscv_xlen(target), r->misa[0]);
1602
1603 return ERROR_OK;
1604 }
1605
1606 static riscv_error_t handle_halt_routine(struct target *target)
1607 {
1608 riscv011_info_t *info = get_info(target);
1609
1610 scans_t *scans = scans_new(target, 256);
1611
1612 /* Read all GPRs as fast as we can, because gdb is going to ask for them
1613 * anyway. Reading them one at a time is much slower. */
1614
1615 /* Write the jump back to address 1. */
1616 scans_add_write_jump(scans, 1, false);
1617 for (int reg = 1; reg < 32; reg++) {
1618 if (reg == S0 || reg == S1)
1619 continue;
1620
1621 /* Write store instruction. */
1622 scans_add_write_store(scans, 0, reg, SLOT0, true);
1623
1624 /* Read value. */
1625 scans_add_read(scans, SLOT0, false);
1626 }
1627
1628 /* Write store of s0 at index 1. */
1629 scans_add_write_store(scans, 1, S0, SLOT0, false);
1630 /* Write jump at index 2. */
1631 scans_add_write_jump(scans, 2, false);
1632
1633 /* Read S1 from debug RAM */
1634 scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1635 /* Read value. */
1636 scans_add_read(scans, SLOT0, false);
1637
1638 /* Read S0 from dscratch */
1639 unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
1640 for (unsigned int i = 0; i < DIM(csr); i++) {
1641 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1642 scans_add_read(scans, SLOT0, false);
1643 }
1644
1645 /* Final read to get the last value out. */
1646 scans_add_read32(scans, 4, false);
1647
1648 int retval = scans_execute(scans);
1649 if (retval != ERROR_OK) {
1650 LOG_ERROR("JTAG execute failed: %d", retval);
1651 goto error;
1652 }
1653
1654 unsigned int dbus_busy = 0;
1655 unsigned int interrupt_set = 0;
1656 unsigned result = 0;
1657 uint64_t value = 0;
1658 reg_cache_set(target, 0, 0);
1659 /* The first scan result is the result from something old we don't care
1660 * about. */
1661 for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1662 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1663 DBUS_OP_SIZE);
1664 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1665 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1666 info->addrbits);
1667 switch (status) {
1668 case DBUS_STATUS_SUCCESS:
1669 break;
1670 case DBUS_STATUS_FAILED:
1671 LOG_ERROR("Debug access failed. Hardware error?");
1672 goto error;
1673 case DBUS_STATUS_BUSY:
1674 dbus_busy++;
1675 break;
1676 default:
1677 LOG_ERROR("Got invalid bus access status: %d", status);
1678 return ERROR_FAIL;
1679 }
1680 if (data & DMCONTROL_INTERRUPT) {
1681 interrupt_set++;
1682 break;
1683 }
1684 if (address == 4 || address == 5) {
1685 unsigned int reg;
1686 switch (result) {
1687 case 0:
1688 reg = 1;
1689 break;
1690 case 1:
1691 reg = 2;
1692 break;
1693 case 2:
1694 reg = 3;
1695 break;
1696 case 3:
1697 reg = 4;
1698 break;
1699 case 4:
1700 reg = 5;
1701 break;
1702 case 5:
1703 reg = 6;
1704 break;
1705 case 6:
1706 reg = 7;
1707 break;
1708 /* S0 */
1709 /* S1 */
1710 case 7:
1711 reg = 10;
1712 break;
1713 case 8:
1714 reg = 11;
1715 break;
1716 case 9:
1717 reg = 12;
1718 break;
1719 case 10:
1720 reg = 13;
1721 break;
1722 case 11:
1723 reg = 14;
1724 break;
1725 case 12:
1726 reg = 15;
1727 break;
1728 case 13:
1729 reg = 16;
1730 break;
1731 case 14:
1732 reg = 17;
1733 break;
1734 case 15:
1735 reg = 18;
1736 break;
1737 case 16:
1738 reg = 19;
1739 break;
1740 case 17:
1741 reg = 20;
1742 break;
1743 case 18:
1744 reg = 21;
1745 break;
1746 case 19:
1747 reg = 22;
1748 break;
1749 case 20:
1750 reg = 23;
1751 break;
1752 case 21:
1753 reg = 24;
1754 break;
1755 case 22:
1756 reg = 25;
1757 break;
1758 case 23:
1759 reg = 26;
1760 break;
1761 case 24:
1762 reg = 27;
1763 break;
1764 case 25:
1765 reg = 28;
1766 break;
1767 case 26:
1768 reg = 29;
1769 break;
1770 case 27:
1771 reg = 30;
1772 break;
1773 case 28:
1774 reg = 31;
1775 break;
1776 case 29:
1777 reg = S1;
1778 break;
1779 case 30:
1780 reg = S0;
1781 break;
1782 case 31:
1783 reg = CSR_DPC;
1784 break;
1785 case 32:
1786 reg = CSR_DCSR;
1787 break;
1788 default:
1789 assert(0);
1790 }
1791 if (riscv_xlen(target) == 32) {
1792 reg_cache_set(target, reg, data & 0xffffffff);
1793 result++;
1794 } else if (riscv_xlen(target) == 64) {
1795 if (address == 4) {
1796 value = data & 0xffffffff;
1797 } else if (address == 5) {
1798 reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1799 value = 0;
1800 result++;
1801 }
1802 }
1803 }
1804 }
1805
1806 if (dbus_busy) {
1807 increase_dbus_busy_delay(target);
1808 return RE_AGAIN;
1809 }
1810 if (interrupt_set) {
1811 increase_interrupt_high_delay(target);
1812 return RE_AGAIN;
1813 }
1814
1815 /* TODO: get rid of those 2 variables and talk to the cache directly. */
1816 info->dpc = reg_cache_get(target, CSR_DPC);
1817 info->dcsr = reg_cache_get(target, CSR_DCSR);
1818
1819 scans_delete(scans);
1820
1821 cache_invalidate(target);
1822
1823 return RE_OK;
1824
1825 error:
1826 scans_delete(scans);
1827 return RE_FAIL;
1828 }
1829
1830 static int handle_halt(struct target *target, bool announce)
1831 {
1832 riscv011_info_t *info = get_info(target);
1833 target->state = TARGET_HALTED;
1834
1835 riscv_error_t re;
1836 do {
1837 re = handle_halt_routine(target);
1838 } while (re == RE_AGAIN);
1839 if (re != RE_OK) {
1840 LOG_ERROR("handle_halt_routine failed");
1841 return ERROR_FAIL;
1842 }
1843
1844 int cause = get_field(info->dcsr, DCSR_CAUSE);
1845 switch (cause) {
1846 case DCSR_CAUSE_SWBP:
1847 target->debug_reason = DBG_REASON_BREAKPOINT;
1848 break;
1849 case DCSR_CAUSE_HWBP:
1850 target->debug_reason = DBG_REASON_WPTANDBKPT;
1851 /* If we halted because of a data trigger, gdb doesn't know to do
1852 * the disable-breakpoints-step-enable-breakpoints dance. */
1853 info->need_strict_step = true;
1854 break;
1855 case DCSR_CAUSE_DEBUGINT:
1856 target->debug_reason = DBG_REASON_DBGRQ;
1857 break;
1858 case DCSR_CAUSE_STEP:
1859 target->debug_reason = DBG_REASON_SINGLESTEP;
1860 break;
1861 case DCSR_CAUSE_HALT:
1862 default:
1863 LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1864 cause, info->dcsr);
1865 }
1866
1867 if (info->never_halted) {
1868 info->never_halted = false;
1869
1870 int result = maybe_read_tselect(target);
1871 if (result != ERROR_OK)
1872 return result;
1873 riscv_enumerate_triggers(target);
1874 }
1875
1876 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1877 int retval;
1878 if (riscv_semihosting(target, &retval) != 0)
1879 return retval;
1880 }
1881
1882 if (announce)
1883 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1884
1885 const char *cause_string[] = {
1886 "none",
1887 "software breakpoint",
1888 "hardware trigger",
1889 "debug interrupt",
1890 "step",
1891 "halt"
1892 };
1893 /* This is logged to the user so that gdb will show it when a user types
1894 * 'monitor reset init'. At that time gdb appears to have the pc cached
1895 * still so if a user manually inspects the pc it will still have the old
1896 * value. */
1897 LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1898
1899 return ERROR_OK;
1900 }
1901
1902 static int poll_target(struct target *target, bool announce)
1903 {
1904 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1905
1906 /* Inhibit debug logging during poll(), which isn't usually interesting and
1907 * just fills up the screen/logs with clutter. */
1908 int old_debug_level = debug_level;
1909 if (debug_level >= LOG_LVL_DEBUG)
1910 debug_level = LOG_LVL_INFO;
1911 bits_t bits = read_bits(target);
1912 debug_level = old_debug_level;
1913
1914 if (bits.haltnot && bits.interrupt) {
1915 target->state = TARGET_DEBUG_RUNNING;
1916 LOG_DEBUG("debug running");
1917 } else if (bits.haltnot && !bits.interrupt) {
1918 if (target->state != TARGET_HALTED)
1919 return handle_halt(target, announce);
1920 } else if (!bits.haltnot && bits.interrupt) {
1921 /* Target is halting. There is no state for that, so don't change anything. */
1922 LOG_DEBUG("halting");
1923 } else if (!bits.haltnot && !bits.interrupt) {
1924 target->state = TARGET_RUNNING;
1925 }
1926
1927 return ERROR_OK;
1928 }
1929
1930 static int riscv011_poll(struct target *target)
1931 {
1932 return poll_target(target, true);
1933 }
1934
1935 static int riscv011_resume(struct target *target, int current,
1936 target_addr_t address, int handle_breakpoints, int debug_execution)
1937 {
1938 riscv011_info_t *info = get_info(target);
1939
1940 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1941
1942 if (!current) {
1943 if (riscv_xlen(target) > 32) {
1944 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1945 riscv_xlen(target));
1946 }
1947 int result = register_write(target, GDB_REGNO_PC, address);
1948 if (result != ERROR_OK)
1949 return result;
1950 }
1951
1952 if (info->need_strict_step || handle_breakpoints) {
1953 int result = strict_step(target, false);
1954 if (result != ERROR_OK)
1955 return result;
1956 }
1957
1958 return resume(target, debug_execution, false);
1959 }
1960
1961 static int assert_reset(struct target *target)
1962 {
1963 riscv011_info_t *info = get_info(target);
1964 /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1965
1966 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1967
1968 /* The only assumption we can make is that the TAP was reset. */
1969 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1970 LOG_ERROR("Debug interrupt didn't clear.");
1971 return ERROR_FAIL;
1972 }
1973
1974 /* Not sure what we should do when there are multiple cores.
1975 * Here just reset the single hart we're talking to. */
1976 info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
1977 DCSR_EBREAKU | DCSR_HALT;
1978 if (target->reset_halt)
1979 info->dcsr |= DCSR_NDRESET;
1980 else
1981 info->dcsr |= DCSR_FULLRESET;
1982 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1983 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1984 /* We shouldn't actually need the jump because a reset should happen. */
1985 dram_write_jump(target, 2, false);
1986 dram_write32(target, 4, info->dcsr, true);
1987 cache_invalidate(target);
1988
1989 target->state = TARGET_RESET;
1990
1991 return ERROR_OK;
1992 }
1993
1994 static int deassert_reset(struct target *target)
1995 {
1996 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1997 if (target->reset_halt)
1998 return wait_for_state(target, TARGET_HALTED);
1999 else
2000 return wait_for_state(target, TARGET_RUNNING);
2001 }
2002
2003 static int read_memory(struct target *target, target_addr_t address,
2004 uint32_t size, uint32_t count, uint8_t *buffer)
2005 {
2006 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2007
2008 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2009 switch (size) {
2010 case 1:
2011 cache_set32(target, 1, lb(S1, S0, 0));
2012 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2013 break;
2014 case 2:
2015 cache_set32(target, 1, lh(S1, S0, 0));
2016 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2017 break;
2018 case 4:
2019 cache_set32(target, 1, lw(S1, S0, 0));
2020 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2021 break;
2022 default:
2023 LOG_ERROR("Unsupported size: %d", size);
2024 return ERROR_FAIL;
2025 }
2026 cache_set_jump(target, 3);
2027 cache_write(target, CACHE_NO_READ, false);
2028
2029 riscv011_info_t *info = get_info(target);
2030 const unsigned max_batch_size = 256;
2031 scans_t *scans = scans_new(target, max_batch_size);
2032
2033 uint32_t result_value = 0x777;
2034 uint32_t i = 0;
2035 while (i < count + 3) {
2036 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2037 scans_reset(scans);
2038
2039 for (unsigned int j = 0; j < batch_size; j++) {
2040 if (i + j == count) {
2041 /* Just insert a read so we can scan out the last value. */
2042 scans_add_read32(scans, 4, false);
2043 } else if (i + j >= count + 1) {
2044 /* And check for errors. */
2045 scans_add_read32(scans, info->dramsize-1, false);
2046 } else {
2047 /* Write the next address and set interrupt. */
2048 uint32_t offset = size * (i + j);
2049 scans_add_write32(scans, 4, address + offset, true);
2050 }
2051 }
2052
2053 int retval = scans_execute(scans);
2054 if (retval != ERROR_OK) {
2055 LOG_ERROR("JTAG execute failed: %d", retval);
2056 goto error;
2057 }
2058
2059 int dbus_busy = 0;
2060 int execute_busy = 0;
2061 for (unsigned int j = 0; j < batch_size; j++) {
2062 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2063 DBUS_OP_SIZE);
2064 switch (status) {
2065 case DBUS_STATUS_SUCCESS:
2066 break;
2067 case DBUS_STATUS_FAILED:
2068 LOG_ERROR("Debug RAM write failed. Hardware error?");
2069 goto error;
2070 case DBUS_STATUS_BUSY:
2071 dbus_busy++;
2072 break;
2073 default:
2074 LOG_ERROR("Got invalid bus access status: %d", status);
2075 return ERROR_FAIL;
2076 }
2077 uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2078 DBUS_DATA_SIZE);
2079 if (data & DMCONTROL_INTERRUPT)
2080 execute_busy++;
2081 if (i + j == count + 2) {
2082 result_value = data;
2083 } else if (i + j > 1) {
2084 uint32_t offset = size * (i + j - 2);
2085 switch (size) {
2086 case 1:
2087 buffer[offset] = data;
2088 break;
2089 case 2:
2090 buffer[offset] = data;
2091 buffer[offset+1] = data >> 8;
2092 break;
2093 case 4:
2094 buffer[offset] = data;
2095 buffer[offset+1] = data >> 8;
2096 buffer[offset+2] = data >> 16;
2097 buffer[offset+3] = data >> 24;
2098 break;
2099 }
2100 }
2101 LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2102 }
2103 if (dbus_busy)
2104 increase_dbus_busy_delay(target);
2105 if (execute_busy)
2106 increase_interrupt_high_delay(target);
2107 if (dbus_busy || execute_busy) {
2108 wait_for_debugint_clear(target, false);
2109
2110 /* Retry. */
2111 LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2112 " with more delays", address + size * i);
2113 } else {
2114 i += batch_size;
2115 }
2116 }
2117
2118 if (result_value != 0) {
2119 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2120 TARGET_PRIxADDR, result_value, address + size * (count-1));
2121 if (count > 1) {
2122 LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2123 " and 0x%" TARGET_PRIxADDR " as well, but we "
2124 "didn't check then.)",
2125 address, address + size * (count-2) + size - 1);
2126 }
2127 goto error;
2128 }
2129
2130 scans_delete(scans);
2131 cache_clean(target);
2132 return ERROR_OK;
2133
2134 error:
2135 scans_delete(scans);
2136 cache_clean(target);
2137 return ERROR_FAIL;
2138 }
2139
2140 static int setup_write_memory(struct target *target, uint32_t size)
2141 {
2142 switch (size) {
2143 case 1:
2144 cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2145 cache_set32(target, 1, sb(S0, T0, 0));
2146 break;
2147 case 2:
2148 cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2149 cache_set32(target, 1, sh(S0, T0, 0));
2150 break;
2151 case 4:
2152 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2153 cache_set32(target, 1, sw(S0, T0, 0));
2154 break;
2155 default:
2156 LOG_ERROR("Unsupported size: %d", size);
2157 return ERROR_FAIL;
2158 }
2159 cache_set32(target, 2, addi(T0, T0, size));
2160 cache_set_jump(target, 3);
2161 cache_write(target, 4, false);
2162
2163 return ERROR_OK;
2164 }
2165
2166 static int write_memory(struct target *target, target_addr_t address,
2167 uint32_t size, uint32_t count, const uint8_t *buffer)
2168 {
2169 riscv011_info_t *info = get_info(target);
2170 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2171
2172 /* Set up the address. */
2173 cache_set_store(target, 0, T0, SLOT1);
2174 cache_set_load(target, 1, T0, SLOT0);
2175 cache_set_jump(target, 2);
2176 cache_set(target, SLOT0, address);
2177 if (cache_write(target, 5, true) != ERROR_OK)
2178 return ERROR_FAIL;
2179
2180 uint64_t t0 = cache_get(target, SLOT1);
2181 LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2182
2183 if (setup_write_memory(target, size) != ERROR_OK)
2184 return ERROR_FAIL;
2185
2186 const unsigned max_batch_size = 256;
2187 scans_t *scans = scans_new(target, max_batch_size);
2188
2189 uint32_t result_value = 0x777;
2190 uint32_t i = 0;
2191 while (i < count + 2) {
2192 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2193 scans_reset(scans);
2194
2195 for (unsigned int j = 0; j < batch_size; j++) {
2196 if (i + j >= count) {
2197 /* Check for an exception. */
2198 scans_add_read32(scans, info->dramsize-1, false);
2199 } else {
2200 /* Write the next value and set interrupt. */
2201 uint32_t value;
2202 uint32_t offset = size * (i + j);
2203 switch (size) {
2204 case 1:
2205 value = buffer[offset];
2206 break;
2207 case 2:
2208 value = buffer[offset] |
2209 (buffer[offset+1] << 8);
2210 break;
2211 case 4:
2212 value = buffer[offset] |
2213 ((uint32_t) buffer[offset+1] << 8) |
2214 ((uint32_t) buffer[offset+2] << 16) |
2215 ((uint32_t) buffer[offset+3] << 24);
2216 break;
2217 default:
2218 goto error;
2219 }
2220
2221 scans_add_write32(scans, 4, value, true);
2222 }
2223 }
2224
2225 int retval = scans_execute(scans);
2226 if (retval != ERROR_OK) {
2227 LOG_ERROR("JTAG execute failed: %d", retval);
2228 goto error;
2229 }
2230
2231 int dbus_busy = 0;
2232 int execute_busy = 0;
2233 for (unsigned int j = 0; j < batch_size; j++) {
2234 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2235 DBUS_OP_SIZE);
2236 switch (status) {
2237 case DBUS_STATUS_SUCCESS:
2238 break;
2239 case DBUS_STATUS_FAILED:
2240 LOG_ERROR("Debug RAM write failed. Hardware error?");
2241 goto error;
2242 case DBUS_STATUS_BUSY:
2243 dbus_busy++;
2244 break;
2245 default:
2246 LOG_ERROR("Got invalid bus access status: %d", status);
2247 return ERROR_FAIL;
2248 }
2249 int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2250 if (interrupt)
2251 execute_busy++;
2252 if (i + j == count + 1)
2253 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2254 }
2255 if (dbus_busy)
2256 increase_dbus_busy_delay(target);
2257 if (execute_busy)
2258 increase_interrupt_high_delay(target);
2259 if (dbus_busy || execute_busy) {
2260 wait_for_debugint_clear(target, false);
2261
2262 /* Retry.
2263 * Set t0 back to what it should have been at the beginning of this
2264 * batch. */
2265 LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2266 " with more delays", address + size * i);
2267
2268 cache_clean(target);
2269
2270 if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2271 goto error;
2272
2273 if (setup_write_memory(target, size) != ERROR_OK)
2274 goto error;
2275 } else {
2276 i += batch_size;
2277 }
2278 }
2279
2280 if (result_value != 0) {
2281 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2282 TARGET_PRIxADDR, result_value, address + size * (count-1));
2283 if (count > 1) {
2284 LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2285 " and 0x%" TARGET_PRIxADDR " as well, but we "
2286 "didn't check then.)",
2287 address, address + size * (count-2) + size - 1);
2288 }
2289 goto error;
2290 }
2291
2292 scans_delete(scans);
2293 cache_clean(target);
2294 return register_write(target, T0, t0);
2295
2296 error:
2297 scans_delete(scans);
2298 cache_clean(target);
2299 return ERROR_FAIL;
2300 }
2301
2302 static int arch_state(struct target *target)
2303 {
2304 return ERROR_OK;
2305 }
2306
2307 struct target_type riscv011_target = {
2308 .name = "riscv",
2309
2310 .init_target = init_target,
2311 .deinit_target = deinit_target,
2312 .examine = examine,
2313
2314 /* poll current target status */
2315 .poll = riscv011_poll,
2316
2317 .halt = halt,
2318 .resume = riscv011_resume,
2319 .step = step,
2320
2321 .assert_reset = assert_reset,
2322 .deassert_reset = deassert_reset,
2323
2324 .read_memory = read_memory,
2325 .write_memory = write_memory,
2326
2327 .arch_state = arch_state,
2328 };
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