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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / riscv / riscv-011.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /*
4 * Support for RISC-V, debug version 0.11. This was never an officially adopted
5 * spec, but SiFive made some silicon that uses it.
6 */
7
8 #include <assert.h>
9 #include <stdlib.h>
10 #include <time.h>
11
12 #ifdef HAVE_CONFIG_H
13 #include "config.h"
14 #endif
15
16 #include "target/target.h"
17 #include "target/algorithm.h"
18 #include "target/target_type.h"
19 #include <helper/log.h>
20 #include "jtag/jtag.h"
21 #include "target/register.h"
22 #include "target/breakpoints.h"
23 #include "helper/time_support.h"
24 #include "riscv.h"
25 #include "asm.h"
26 #include "gdb_regs.h"
27
28 /**
29 * Since almost everything can be accomplish by scanning the dbus register, all
30 * functions here assume dbus is already selected. The exception are functions
31 * called directly by OpenOCD, which can't assume anything about what's
32 * currently in IR. They should set IR to dbus explicitly.
33 */
34
35 /**
36 * Code structure
37 *
38 * At the bottom of the stack are the OpenOCD JTAG functions:
39 * jtag_add_[id]r_scan
40 * jtag_execute_query
41 * jtag_add_runtest
42 *
43 * There are a few functions to just instantly shift a register and get its
44 * value:
45 * dtmcontrol_scan
46 * idcode_scan
47 * dbus_scan
48 *
49 * Because doing one scan and waiting for the result is slow, most functions
50 * batch up a bunch of dbus writes and then execute them all at once. They use
51 * the scans "class" for this:
52 * scans_new
53 * scans_delete
54 * scans_execute
55 * scans_add_...
56 * Usually you new(), call a bunch of add functions, then execute() and look
57 * at the results by calling scans_get...()
58 *
59 * Optimized functions will directly use the scans class above, but slightly
60 * lazier code will use the cache functions that in turn use the scans
61 * functions:
62 * cache_get...
63 * cache_set...
64 * cache_write
65 * cache_set... update a local structure, which is then synced to the target
66 * with cache_write(). Only Debug RAM words that are actually changed are sent
67 * to the target. Afterwards use cache_get... to read results.
68 */
69
70 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
71 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
72
73 /* Constants for legacy SiFive hardware breakpoints. */
74 #define CSR_BPCONTROL_X (1<<0)
75 #define CSR_BPCONTROL_W (1<<1)
76 #define CSR_BPCONTROL_R (1<<2)
77 #define CSR_BPCONTROL_U (1<<3)
78 #define CSR_BPCONTROL_S (1<<4)
79 #define CSR_BPCONTROL_H (1<<5)
80 #define CSR_BPCONTROL_M (1<<6)
81 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
82 #define CSR_BPCONTROL_BPACTION (0xff<<11)
83
84 #define DEBUG_ROM_START 0x800
85 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
86 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
87 #define DEBUG_RAM_START 0x400
88
89 #define SETHALTNOT 0x10c
90
91 /*** JTAG registers. ***/
92
93 #define DTMCONTROL 0x10
94 #define DTMCONTROL_DBUS_RESET (1<<16)
95 #define DTMCONTROL_IDLE (7<<10)
96 #define DTMCONTROL_ADDRBITS (0xf<<4)
97 #define DTMCONTROL_VERSION (0xf)
98
99 #define DBUS 0x11
100 #define DBUS_OP_START 0
101 #define DBUS_OP_SIZE 2
102 typedef enum {
103 DBUS_OP_NOP = 0,
104 DBUS_OP_READ = 1,
105 DBUS_OP_WRITE = 2
106 } dbus_op_t;
107 typedef enum {
108 DBUS_STATUS_SUCCESS = 0,
109 DBUS_STATUS_FAILED = 2,
110 DBUS_STATUS_BUSY = 3
111 } dbus_status_t;
112 #define DBUS_DATA_START 2
113 #define DBUS_DATA_SIZE 34
114 #define DBUS_ADDRESS_START 36
115
116 typedef enum {
117 RE_OK,
118 RE_FAIL,
119 RE_AGAIN
120 } riscv_error_t;
121
122 typedef enum slot {
123 SLOT0,
124 SLOT1,
125 SLOT_LAST,
126 } slot_t;
127
128 /*** Debug Bus registers. ***/
129
130 #define DMCONTROL 0x10
131 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
132 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
133 #define DMCONTROL_BUSERROR (7<<19)
134 #define DMCONTROL_SERIAL (3<<16)
135 #define DMCONTROL_AUTOINCREMENT (1<<15)
136 #define DMCONTROL_ACCESS (7<<12)
137 #define DMCONTROL_HARTID (0x3ff<<2)
138 #define DMCONTROL_NDRESET (1<<1)
139 #define DMCONTROL_FULLRESET 1
140
141 #define DMINFO 0x11
142 #define DMINFO_ABUSSIZE (0x7fU<<25)
143 #define DMINFO_SERIALCOUNT (0xf<<21)
144 #define DMINFO_ACCESS128 (1<<20)
145 #define DMINFO_ACCESS64 (1<<19)
146 #define DMINFO_ACCESS32 (1<<18)
147 #define DMINFO_ACCESS16 (1<<17)
148 #define DMINFO_ACCESS8 (1<<16)
149 #define DMINFO_DRAMSIZE (0x3f<<10)
150 #define DMINFO_AUTHENTICATED (1<<5)
151 #define DMINFO_AUTHBUSY (1<<4)
152 #define DMINFO_AUTHTYPE (3<<2)
153 #define DMINFO_VERSION 3
154
155 #define DMAUTHDATA0 0x12
156 #define DMAUTHDATA1 0x13
157
158 /*** Info about the core being debugged. ***/
159
160 #define DBUS_ADDRESS_UNKNOWN 0xffff
161
162 #define DRAM_CACHE_SIZE 16
163
164 struct trigger {
165 uint64_t address;
166 uint32_t length;
167 uint64_t mask;
168 uint64_t value;
169 bool read, write, execute;
170 int unique_id;
171 };
172
173 struct memory_cache_line {
174 uint32_t data;
175 bool valid;
176 bool dirty;
177 };
178
179 typedef struct {
180 /* Number of address bits in the dbus register. */
181 uint8_t addrbits;
182 /* Number of words in Debug RAM. */
183 unsigned int dramsize;
184 uint64_t dcsr;
185 uint64_t dpc;
186 uint64_t tselect;
187 bool tselect_dirty;
188 /* The value that mstatus actually has on the target right now. This is not
189 * the value we present to the user. That one may be stored in the
190 * reg_cache. */
191 uint64_t mstatus_actual;
192
193 struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
194
195 /* Number of run-test/idle cycles the target requests we do after each dbus
196 * access. */
197 unsigned int dtmcontrol_idle;
198
199 /* This value is incremented every time a dbus access comes back as "busy".
200 * It's used to determine how many run-test/idle cycles to feed the target
201 * in between accesses. */
202 unsigned int dbus_busy_delay;
203
204 /* This value is incremented every time we read the debug interrupt as
205 * high. It's used to add extra run-test/idle cycles after setting debug
206 * interrupt high, so ideally we never have to perform a whole extra scan
207 * before the interrupt is cleared. */
208 unsigned int interrupt_high_delay;
209
210 bool never_halted;
211 } riscv011_info_t;
212
213 typedef struct {
214 bool haltnot;
215 bool interrupt;
216 } bits_t;
217
218 /*** Necessary prototypes. ***/
219
220 static int poll_target(struct target *target, bool announce);
221 static int riscv011_poll(struct target *target);
222 static int get_register(struct target *target, riscv_reg_t *value, int regid);
223
224 /*** Utility functions. ***/
225
226 #define DEBUG_LENGTH 264
227
228 static riscv011_info_t *get_info(const struct target *target)
229 {
230 struct riscv_info *info = target->arch_info;
231 assert(info);
232 assert(info->version_specific);
233 return info->version_specific;
234 }
235
236 static unsigned int slot_offset(const struct target *target, slot_t slot)
237 {
238 riscv011_info_t *info = get_info(target);
239 switch (riscv_xlen(target)) {
240 case 32:
241 switch (slot) {
242 case SLOT0: return 4;
243 case SLOT1: return 5;
244 case SLOT_LAST: return info->dramsize-1;
245 }
246 break;
247 case 64:
248 switch (slot) {
249 case SLOT0: return 4;
250 case SLOT1: return 6;
251 case SLOT_LAST: return info->dramsize-2;
252 }
253 }
254 LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
255 riscv_xlen(target), slot);
256 assert(0);
257 return 0; /* Silence -Werror=return-type */
258 }
259
260 static uint32_t load_slot(const struct target *target, unsigned int dest,
261 slot_t slot)
262 {
263 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
264 return load(target, dest, ZERO, offset);
265 }
266
267 static uint32_t store_slot(const struct target *target, unsigned int src,
268 slot_t slot)
269 {
270 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
271 return store(target, src, ZERO, offset);
272 }
273
274 static uint16_t dram_address(unsigned int index)
275 {
276 if (index < 0x10)
277 return index;
278 else
279 return 0x40 + index - 0x10;
280 }
281
282 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
283 {
284 struct scan_field field;
285 uint8_t in_value[4];
286 uint8_t out_value[4] = { 0 };
287
288 buf_set_u32(out_value, 0, 32, out);
289
290 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
291
292 field.num_bits = 32;
293 field.out_value = out_value;
294 field.in_value = in_value;
295 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
296
297 /* Always return to dbus. */
298 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
299
300 int retval = jtag_execute_queue();
301 if (retval != ERROR_OK) {
302 LOG_ERROR("failed jtag scan: %d", retval);
303 return retval;
304 }
305
306 uint32_t in = buf_get_u32(field.in_value, 0, 32);
307 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
308
309 return in;
310 }
311
312 static uint32_t idcode_scan(struct target *target)
313 {
314 struct scan_field field;
315 uint8_t in_value[4];
316
317 jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
318
319 field.num_bits = 32;
320 field.out_value = NULL;
321 field.in_value = in_value;
322 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
323
324 int retval = jtag_execute_queue();
325 if (retval != ERROR_OK) {
326 LOG_ERROR("failed jtag scan: %d", retval);
327 return retval;
328 }
329
330 /* Always return to dbus. */
331 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
332
333 uint32_t in = buf_get_u32(field.in_value, 0, 32);
334 LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
335
336 return in;
337 }
338
339 static void increase_dbus_busy_delay(struct target *target)
340 {
341 riscv011_info_t *info = get_info(target);
342 info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
343 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
344 info->dtmcontrol_idle, info->dbus_busy_delay,
345 info->interrupt_high_delay);
346
347 dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
348 }
349
350 static void increase_interrupt_high_delay(struct target *target)
351 {
352 riscv011_info_t *info = get_info(target);
353 info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
354 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
355 info->dtmcontrol_idle, info->dbus_busy_delay,
356 info->interrupt_high_delay);
357 }
358
359 static void add_dbus_scan(const struct target *target, struct scan_field *field,
360 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
361 uint16_t address, uint64_t data)
362 {
363 riscv011_info_t *info = get_info(target);
364 RISCV_INFO(r);
365
366 if (r->reset_delays_wait >= 0) {
367 r->reset_delays_wait--;
368 if (r->reset_delays_wait < 0) {
369 info->dbus_busy_delay = 0;
370 info->interrupt_high_delay = 0;
371 }
372 }
373
374 field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
375 field->in_value = in_value;
376 field->out_value = out_value;
377
378 buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
379 buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
380 buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
381
382 jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
383
384 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
385 if (data & DMCONTROL_INTERRUPT)
386 idle_count += info->interrupt_high_delay;
387
388 if (idle_count)
389 jtag_add_runtest(idle_count, TAP_IDLE);
390 }
391
392 static void dump_field(const struct scan_field *field)
393 {
394 static const char * const op_string[] = {"nop", "r", "w", "?"};
395 static const char * const status_string[] = {"+", "?", "F", "b"};
396
397 if (debug_level < LOG_LVL_DEBUG)
398 return;
399
400 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
401 unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
402 char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
403 char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
404 unsigned int out_data = out >> 2;
405 unsigned int out_address = out >> DBUS_ADDRESS_START;
406 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
407 unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
408 char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
409 char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
410 unsigned int in_data = in >> 2;
411 unsigned int in_address = in >> DBUS_ADDRESS_START;
412
413 log_printf_lf(LOG_LVL_DEBUG,
414 __FILE__, __LINE__, "scan",
415 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
416 field->num_bits,
417 op_string[out_op], out_interrupt, out_haltnot, out_data,
418 out_address,
419 status_string[in_op], in_interrupt, in_haltnot, in_data,
420 in_address);
421 }
422
423 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
424 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
425 {
426 riscv011_info_t *info = get_info(target);
427 uint8_t in[8] = {0};
428 uint8_t out[8] = {0};
429 struct scan_field field = {
430 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
431 .out_value = out,
432 .in_value = in
433 };
434
435 assert(info->addrbits != 0);
436
437 buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
438 buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
439 buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
440
441 /* Assume dbus is already selected. */
442 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
443
444 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
445
446 if (idle_count)
447 jtag_add_runtest(idle_count, TAP_IDLE);
448
449 int retval = jtag_execute_queue();
450 if (retval != ERROR_OK) {
451 LOG_ERROR("dbus_scan failed jtag scan");
452 return DBUS_STATUS_FAILED;
453 }
454
455 if (data_in)
456 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
457
458 if (address_in)
459 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
460
461 dump_field(&field);
462
463 return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
464 }
465
466 static uint64_t dbus_read(struct target *target, uint16_t address)
467 {
468 uint64_t value;
469 dbus_status_t status;
470 uint16_t address_in;
471
472 /* If the previous read/write was to the same address, we will get the read data
473 * from the previous access.
474 * While somewhat nonintuitive, this is an efficient way to get the data.
475 */
476
477 unsigned i = 0;
478 do {
479 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
480 if (status == DBUS_STATUS_BUSY)
481 increase_dbus_busy_delay(target);
482 if (status == DBUS_STATUS_FAILED) {
483 LOG_ERROR("dbus_read(0x%x) failed!", address);
484 return 0;
485 }
486 } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
487 i++ < 256);
488
489 if (status != DBUS_STATUS_SUCCESS)
490 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
491
492 return value;
493 }
494
495 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
496 {
497 dbus_status_t status = DBUS_STATUS_BUSY;
498 unsigned i = 0;
499 while (status == DBUS_STATUS_BUSY && i++ < 256) {
500 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
501 if (status == DBUS_STATUS_BUSY)
502 increase_dbus_busy_delay(target);
503 }
504 if (status != DBUS_STATUS_SUCCESS)
505 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
506 }
507
508 /*** scans "class" ***/
509
510 typedef struct {
511 /* Number of scans that space is reserved for. */
512 unsigned int scan_count;
513 /* Size reserved in memory for each scan, in bytes. */
514 unsigned int scan_size;
515 unsigned int next_scan;
516 uint8_t *in;
517 uint8_t *out;
518 struct scan_field *field;
519 const struct target *target;
520 } scans_t;
521
522 static scans_t *scans_new(struct target *target, unsigned int scan_count)
523 {
524 scans_t *scans = malloc(sizeof(scans_t));
525 if (!scans)
526 goto error0;
527 scans->scan_count = scan_count;
528 /* This code also gets called before xlen is detected. */
529 if (riscv_xlen(target))
530 scans->scan_size = 2 + riscv_xlen(target) / 8;
531 else
532 scans->scan_size = 2 + 128 / 8;
533 scans->next_scan = 0;
534 scans->in = calloc(scans->scan_size, scans->scan_count);
535 if (!scans->in)
536 goto error1;
537 scans->out = calloc(scans->scan_size, scans->scan_count);
538 if (!scans->out)
539 goto error2;
540 scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
541 if (!scans->field)
542 goto error3;
543 scans->target = target;
544 return scans;
545
546 error3:
547 free(scans->out);
548 error2:
549 free(scans->in);
550 error1:
551 free(scans);
552 error0:
553 return NULL;
554 }
555
556 static scans_t *scans_delete(scans_t *scans)
557 {
558 assert(scans);
559 free(scans->field);
560 free(scans->out);
561 free(scans->in);
562 free(scans);
563 return NULL;
564 }
565
566 static void scans_reset(scans_t *scans)
567 {
568 scans->next_scan = 0;
569 }
570
571 static void scans_dump(scans_t *scans)
572 {
573 for (unsigned int i = 0; i < scans->next_scan; i++)
574 dump_field(&scans->field[i]);
575 }
576
577 static int scans_execute(scans_t *scans)
578 {
579 int retval = jtag_execute_queue();
580 if (retval != ERROR_OK) {
581 LOG_ERROR("failed jtag scan: %d", retval);
582 return retval;
583 }
584
585 scans_dump(scans);
586
587 return ERROR_OK;
588 }
589
590 /** Add a 32-bit dbus write to the scans structure. */
591 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
592 bool set_interrupt)
593 {
594 const unsigned int i = scans->next_scan;
595 int data_offset = scans->scan_size * i;
596 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
597 scans->in + data_offset, DBUS_OP_WRITE, address,
598 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
599 scans->next_scan++;
600 assert(scans->next_scan <= scans->scan_count);
601 }
602
603 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
604 * debug RAM. */
605 static void scans_add_write_jump(scans_t *scans, uint16_t address,
606 bool set_interrupt)
607 {
608 scans_add_write32(scans, address,
609 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
610 set_interrupt);
611 }
612
613 /** Add a 32-bit dbus write for an instruction that loads from the indicated
614 * slot. */
615 static void scans_add_write_load(scans_t *scans, uint16_t address,
616 unsigned int reg, slot_t slot, bool set_interrupt)
617 {
618 scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
619 set_interrupt);
620 }
621
622 /** Add a 32-bit dbus write for an instruction that stores to the indicated
623 * slot. */
624 static void scans_add_write_store(scans_t *scans, uint16_t address,
625 unsigned int reg, slot_t slot, bool set_interrupt)
626 {
627 scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
628 set_interrupt);
629 }
630
631 /** Add a 32-bit dbus read. */
632 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
633 {
634 assert(scans->next_scan < scans->scan_count);
635 const unsigned int i = scans->next_scan;
636 int data_offset = scans->scan_size * i;
637 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
638 scans->in + data_offset, DBUS_OP_READ, address,
639 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
640 scans->next_scan++;
641 }
642
643 /** Add one or more scans to read the indicated slot. */
644 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
645 {
646 const struct target *target = scans->target;
647 switch (riscv_xlen(target)) {
648 case 32:
649 scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
650 break;
651 case 64:
652 scans_add_read32(scans, slot_offset(target, slot), false);
653 scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
654 break;
655 }
656 }
657
658 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
659 unsigned first, unsigned num)
660 {
661 return buf_get_u32(scans->in + scans->scan_size * index, first, num);
662 }
663
664 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
665 unsigned first, unsigned num)
666 {
667 return buf_get_u64(scans->in + scans->scan_size * index, first, num);
668 }
669
670 /*** end of scans class ***/
671
672 static uint32_t dram_read32(struct target *target, unsigned int index)
673 {
674 uint16_t address = dram_address(index);
675 uint32_t value = dbus_read(target, address);
676 return value;
677 }
678
679 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
680 bool set_interrupt)
681 {
682 uint64_t dbus_value = DMCONTROL_HALTNOT | value;
683 if (set_interrupt)
684 dbus_value |= DMCONTROL_INTERRUPT;
685 dbus_write(target, dram_address(index), dbus_value);
686 }
687
688 /** Read the haltnot and interrupt bits. */
689 static bits_t read_bits(struct target *target)
690 {
691 uint64_t value;
692 dbus_status_t status;
693 uint16_t address_in;
694 riscv011_info_t *info = get_info(target);
695
696 bits_t err_result = {
697 .haltnot = 0,
698 .interrupt = 0
699 };
700
701 do {
702 unsigned i = 0;
703 do {
704 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
705 if (status == DBUS_STATUS_BUSY) {
706 if (address_in == (1<<info->addrbits) - 1 &&
707 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
708 LOG_ERROR("TDO seems to be stuck high.");
709 return err_result;
710 }
711 increase_dbus_busy_delay(target);
712 } else if (status == DBUS_STATUS_FAILED) {
713 /* TODO: return an actual error */
714 return err_result;
715 }
716 } while (status == DBUS_STATUS_BUSY && i++ < 256);
717
718 if (i >= 256) {
719 LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
720 return err_result;
721 }
722 } while (address_in > 0x10 && address_in != DMCONTROL);
723
724 bits_t result = {
725 .haltnot = get_field(value, DMCONTROL_HALTNOT),
726 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
727 };
728 return result;
729 }
730
731 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
732 {
733 time_t start = time(NULL);
734 if (ignore_first) {
735 /* Throw away the results of the first read, since they'll contain the
736 * result of the read that happened just before debugint was set.
737 * (Assuming the last scan before calling this function was one that
738 * sets debugint.) */
739 read_bits(target);
740 }
741 while (1) {
742 bits_t bits = read_bits(target);
743 if (!bits.interrupt)
744 return ERROR_OK;
745 if (time(NULL) - start > riscv_command_timeout_sec) {
746 LOG_ERROR("Timed out waiting for debug int to clear."
747 "Increase timeout with riscv set_command_timeout_sec.");
748 return ERROR_FAIL;
749 }
750 }
751 }
752
753 static int dram_check32(struct target *target, unsigned int index,
754 uint32_t expected)
755 {
756 uint16_t address = dram_address(index);
757 uint32_t actual = dbus_read(target, address);
758 if (expected != actual) {
759 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
760 expected, index, actual);
761 return ERROR_FAIL;
762 }
763 return ERROR_OK;
764 }
765
766 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
767 {
768 riscv011_info_t *info = get_info(target);
769 if (info->dram_cache[index].valid &&
770 info->dram_cache[index].data == data) {
771 /* This is already preset on the target. */
772 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
773 return;
774 }
775 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
776 info->dram_cache[index].data = data;
777 info->dram_cache[index].valid = true;
778 info->dram_cache[index].dirty = true;
779 }
780
781 static void cache_set(struct target *target, slot_t slot, uint64_t data)
782 {
783 unsigned int offset = slot_offset(target, slot);
784 cache_set32(target, offset, data);
785 if (riscv_xlen(target) > 32)
786 cache_set32(target, offset + 1, data >> 32);
787 }
788
789 static void cache_set_jump(struct target *target, unsigned int index)
790 {
791 cache_set32(target, index,
792 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
793 }
794
795 static void cache_set_load(struct target *target, unsigned int index,
796 unsigned int reg, slot_t slot)
797 {
798 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
799 cache_set32(target, index, load(target, reg, ZERO, offset));
800 }
801
802 static void cache_set_store(struct target *target, unsigned int index,
803 unsigned int reg, slot_t slot)
804 {
805 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
806 cache_set32(target, index, store(target, reg, ZERO, offset));
807 }
808
809 static void dump_debug_ram(struct target *target)
810 {
811 for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
812 uint32_t value = dram_read32(target, i);
813 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
814 }
815 }
816
817 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
818 static void cache_invalidate(struct target *target)
819 {
820 riscv011_info_t *info = get_info(target);
821 for (unsigned int i = 0; i < info->dramsize; i++) {
822 info->dram_cache[i].valid = false;
823 info->dram_cache[i].dirty = false;
824 }
825 }
826
827 /* Called by cache_write() after the program has run. Also call this if you're
828 * running programs without calling cache_write(). */
829 static void cache_clean(struct target *target)
830 {
831 riscv011_info_t *info = get_info(target);
832 for (unsigned int i = 0; i < info->dramsize; i++) {
833 if (i >= 4)
834 info->dram_cache[i].valid = false;
835 info->dram_cache[i].dirty = false;
836 }
837 }
838
839 static int cache_check(struct target *target)
840 {
841 riscv011_info_t *info = get_info(target);
842 int error = 0;
843
844 for (unsigned int i = 0; i < info->dramsize; i++) {
845 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
846 if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
847 error++;
848 }
849 }
850
851 if (error) {
852 dump_debug_ram(target);
853 return ERROR_FAIL;
854 }
855
856 return ERROR_OK;
857 }
858
859 /** Write cache to the target, and optionally run the program.
860 * Then read the value at address into the cache, assuming address < 128. */
861 #define CACHE_NO_READ 128
862 static int cache_write(struct target *target, unsigned int address, bool run)
863 {
864 LOG_DEBUG("enter");
865 riscv011_info_t *info = get_info(target);
866 scans_t *scans = scans_new(target, info->dramsize + 2);
867 if (!scans)
868 return ERROR_FAIL;
869
870 unsigned int last = info->dramsize;
871 for (unsigned int i = 0; i < info->dramsize; i++) {
872 if (info->dram_cache[i].dirty)
873 last = i;
874 }
875
876 if (last == info->dramsize) {
877 /* Nothing needs to be written to RAM. */
878 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
879
880 } else {
881 for (unsigned int i = 0; i < info->dramsize; i++) {
882 if (info->dram_cache[i].dirty) {
883 bool set_interrupt = (i == last && run);
884 scans_add_write32(scans, i, info->dram_cache[i].data,
885 set_interrupt);
886 }
887 }
888 }
889
890 if (run || address < CACHE_NO_READ) {
891 /* Throw away the results of the first read, since it'll contain the
892 * result of the read that happened just before debugint was set. */
893 scans_add_read32(scans, address, false);
894
895 /* This scan contains the results of the read the caller requested, as
896 * well as an interrupt bit worth looking at. */
897 scans_add_read32(scans, address, false);
898 }
899
900 int retval = scans_execute(scans);
901 if (retval != ERROR_OK) {
902 scans_delete(scans);
903 LOG_ERROR("JTAG execute failed.");
904 return retval;
905 }
906
907 int errors = 0;
908 for (unsigned int i = 0; i < scans->next_scan; i++) {
909 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
910 DBUS_OP_SIZE);
911 switch (status) {
912 case DBUS_STATUS_SUCCESS:
913 break;
914 case DBUS_STATUS_FAILED:
915 LOG_ERROR("Debug RAM write failed. Hardware error?");
916 scans_delete(scans);
917 return ERROR_FAIL;
918 case DBUS_STATUS_BUSY:
919 errors++;
920 break;
921 default:
922 LOG_ERROR("Got invalid bus access status: %d", status);
923 scans_delete(scans);
924 return ERROR_FAIL;
925 }
926 }
927
928 if (errors) {
929 increase_dbus_busy_delay(target);
930
931 /* Try again, using the slow careful code.
932 * Write all RAM, just to be extra cautious. */
933 for (unsigned int i = 0; i < info->dramsize; i++) {
934 if (i == last && run)
935 dram_write32(target, last, info->dram_cache[last].data, true);
936 else
937 dram_write32(target, i, info->dram_cache[i].data, false);
938 info->dram_cache[i].dirty = false;
939 }
940 if (run)
941 cache_clean(target);
942
943 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
944 LOG_ERROR("Debug interrupt didn't clear.");
945 dump_debug_ram(target);
946 scans_delete(scans);
947 return ERROR_FAIL;
948 }
949
950 } else {
951 if (run) {
952 cache_clean(target);
953 } else {
954 for (unsigned int i = 0; i < info->dramsize; i++)
955 info->dram_cache[i].dirty = false;
956 }
957
958 if (run || address < CACHE_NO_READ) {
959 int interrupt = scans_get_u32(scans, scans->next_scan-1,
960 DBUS_DATA_START + 33, 1);
961 if (interrupt) {
962 increase_interrupt_high_delay(target);
963 /* Slow path wait for it to clear. */
964 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
965 LOG_ERROR("Debug interrupt didn't clear.");
966 dump_debug_ram(target);
967 scans_delete(scans);
968 return ERROR_FAIL;
969 }
970 } else {
971 /* We read a useful value in that last scan. */
972 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
973 DBUS_ADDRESS_START, info->addrbits);
974 if (read_addr != address) {
975 LOG_INFO("Got data from 0x%x but expected it from 0x%x",
976 read_addr, address);
977 }
978 info->dram_cache[read_addr].data =
979 scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
980 info->dram_cache[read_addr].valid = true;
981 }
982 }
983 }
984
985 scans_delete(scans);
986 LOG_DEBUG("exit");
987
988 return ERROR_OK;
989 }
990
991 static uint32_t cache_get32(struct target *target, unsigned int address)
992 {
993 riscv011_info_t *info = get_info(target);
994 if (!info->dram_cache[address].valid) {
995 info->dram_cache[address].data = dram_read32(target, address);
996 info->dram_cache[address].valid = true;
997 }
998 return info->dram_cache[address].data;
999 }
1000
1001 static uint64_t cache_get(struct target *target, slot_t slot)
1002 {
1003 unsigned int offset = slot_offset(target, slot);
1004 uint64_t value = cache_get32(target, offset);
1005 if (riscv_xlen(target) > 32)
1006 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
1007 return value;
1008 }
1009
1010 /* Write instruction that jumps from the specified word in Debug RAM to resume
1011 * in Debug ROM. */
1012 static void dram_write_jump(struct target *target, unsigned int index,
1013 bool set_interrupt)
1014 {
1015 dram_write32(target, index,
1016 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
1017 set_interrupt);
1018 }
1019
1020 static int wait_for_state(struct target *target, enum target_state state)
1021 {
1022 time_t start = time(NULL);
1023 while (1) {
1024 int result = riscv011_poll(target);
1025 if (result != ERROR_OK)
1026 return result;
1027 if (target->state == state)
1028 return ERROR_OK;
1029 if (time(NULL) - start > riscv_command_timeout_sec) {
1030 LOG_ERROR("Timed out waiting for state %d. "
1031 "Increase timeout with riscv set_command_timeout_sec.", state);
1032 return ERROR_FAIL;
1033 }
1034 }
1035 }
1036
1037 static int read_remote_csr(struct target *target, uint64_t *value, uint32_t csr)
1038 {
1039 riscv011_info_t *info = get_info(target);
1040 cache_set32(target, 0, csrr(S0, csr));
1041 cache_set_store(target, 1, S0, SLOT0);
1042 cache_set_jump(target, 2);
1043 if (cache_write(target, 4, true) != ERROR_OK)
1044 return ERROR_FAIL;
1045 *value = cache_get(target, SLOT0);
1046 LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1047
1048 uint32_t exception = cache_get32(target, info->dramsize-1);
1049 if (exception) {
1050 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1051 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1052 *value = ~0;
1053 return ERROR_FAIL;
1054 }
1055
1056 return ERROR_OK;
1057 }
1058
1059 static int write_remote_csr(struct target *target, uint32_t csr, uint64_t value)
1060 {
1061 LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1062 cache_set_load(target, 0, S0, SLOT0);
1063 cache_set32(target, 1, csrw(S0, csr));
1064 cache_set_jump(target, 2);
1065 cache_set(target, SLOT0, value);
1066 if (cache_write(target, 4, true) != ERROR_OK)
1067 return ERROR_FAIL;
1068
1069 return ERROR_OK;
1070 }
1071
1072 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1073 {
1074 cache_set_load(target, 0, gpr, SLOT0);
1075 cache_set_jump(target, 1);
1076 cache_set(target, SLOT0, value);
1077 if (cache_write(target, 4, true) != ERROR_OK)
1078 return ERROR_FAIL;
1079 return ERROR_OK;
1080 }
1081
1082 static int maybe_read_tselect(struct target *target)
1083 {
1084 riscv011_info_t *info = get_info(target);
1085
1086 if (info->tselect_dirty) {
1087 int result = read_remote_csr(target, &info->tselect, CSR_TSELECT);
1088 if (result != ERROR_OK)
1089 return result;
1090 info->tselect_dirty = false;
1091 }
1092
1093 return ERROR_OK;
1094 }
1095
1096 static int maybe_write_tselect(struct target *target)
1097 {
1098 riscv011_info_t *info = get_info(target);
1099
1100 if (!info->tselect_dirty) {
1101 int result = write_remote_csr(target, CSR_TSELECT, info->tselect);
1102 if (result != ERROR_OK)
1103 return result;
1104 info->tselect_dirty = true;
1105 }
1106
1107 return ERROR_OK;
1108 }
1109
1110 static int execute_resume(struct target *target, bool step)
1111 {
1112 riscv011_info_t *info = get_info(target);
1113
1114 LOG_DEBUG("step=%d", step);
1115
1116 maybe_write_tselect(target);
1117
1118 /* TODO: check if dpc is dirty (which also is true if an exception was hit
1119 * at any time) */
1120 cache_set_load(target, 0, S0, SLOT0);
1121 cache_set32(target, 1, csrw(S0, CSR_DPC));
1122 cache_set_jump(target, 2);
1123 cache_set(target, SLOT0, info->dpc);
1124 if (cache_write(target, 4, true) != ERROR_OK)
1125 return ERROR_FAIL;
1126
1127 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1128 if (mstatus_reg->valid) {
1129 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1130 if (mstatus_user != info->mstatus_actual) {
1131 cache_set_load(target, 0, S0, SLOT0);
1132 cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1133 cache_set_jump(target, 2);
1134 cache_set(target, SLOT0, mstatus_user);
1135 if (cache_write(target, 4, true) != ERROR_OK)
1136 return ERROR_FAIL;
1137 }
1138 }
1139
1140 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1141 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1142 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1143 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1144 info->dcsr &= ~DCSR_HALT;
1145
1146 if (step)
1147 info->dcsr |= DCSR_STEP;
1148 else
1149 info->dcsr &= ~DCSR_STEP;
1150
1151 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1152 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1153 dram_write32(target, 2, fence_i(), false);
1154 dram_write_jump(target, 3, false);
1155
1156 /* Write DCSR value, set interrupt and clear haltnot. */
1157 uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1158 dbus_write(target, dram_address(4), dbus_value);
1159
1160 cache_invalidate(target);
1161
1162 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1163 LOG_ERROR("Debug interrupt didn't clear.");
1164 return ERROR_FAIL;
1165 }
1166
1167 target->state = TARGET_RUNNING;
1168 register_cache_invalidate(target->reg_cache);
1169
1170 return ERROR_OK;
1171 }
1172
1173 /* Execute a step, and wait for reentry into Debug Mode. */
1174 static int full_step(struct target *target, bool announce)
1175 {
1176 int result = execute_resume(target, true);
1177 if (result != ERROR_OK)
1178 return result;
1179 time_t start = time(NULL);
1180 while (1) {
1181 result = poll_target(target, announce);
1182 if (result != ERROR_OK)
1183 return result;
1184 if (target->state != TARGET_DEBUG_RUNNING)
1185 break;
1186 if (time(NULL) - start > riscv_command_timeout_sec) {
1187 LOG_ERROR("Timed out waiting for step to complete."
1188 "Increase timeout with riscv set_command_timeout_sec");
1189 return ERROR_FAIL;
1190 }
1191 }
1192 return ERROR_OK;
1193 }
1194
1195 static int resume(struct target *target, int debug_execution, bool step)
1196 {
1197 if (debug_execution) {
1198 LOG_ERROR("TODO: debug_execution is true");
1199 return ERROR_FAIL;
1200 }
1201
1202 return execute_resume(target, step);
1203 }
1204
1205 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1206 {
1207 struct reg *r = &target->reg_cache->reg_list[number];
1208 if (!r->valid) {
1209 LOG_ERROR("Register cache entry for %d is invalid!", number);
1210 assert(r->valid);
1211 }
1212 uint64_t value = buf_get_u64(r->value, 0, r->size);
1213 LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1214 return value;
1215 }
1216
1217 static void reg_cache_set(struct target *target, unsigned int number,
1218 uint64_t value)
1219 {
1220 struct reg *r = &target->reg_cache->reg_list[number];
1221 LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1222 r->valid = true;
1223 buf_set_u64(r->value, 0, r->size, value);
1224 }
1225
1226 static int update_mstatus_actual(struct target *target)
1227 {
1228 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1229 if (mstatus_reg->valid) {
1230 /* We previously made it valid. */
1231 return ERROR_OK;
1232 }
1233
1234 /* Force reading the register. In that process mstatus_actual will be
1235 * updated. */
1236 riscv_reg_t mstatus;
1237 return get_register(target, &mstatus, GDB_REGNO_MSTATUS);
1238 }
1239
1240 /*** OpenOCD target functions. ***/
1241
1242 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1243 {
1244 riscv011_info_t *info = get_info(target);
1245 if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1246 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1247 cache_set_store(target, 1, S0, SLOT0);
1248 cache_set_jump(target, 2);
1249 } else {
1250 LOG_ERROR("Don't know how to read register %d", regnum);
1251 return ERROR_FAIL;
1252 }
1253
1254 if (cache_write(target, 4, true) != ERROR_OK)
1255 return ERROR_FAIL;
1256
1257 uint32_t exception = cache_get32(target, info->dramsize-1);
1258 if (exception) {
1259 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1260 *value = ~0;
1261 return ERROR_FAIL;
1262 }
1263
1264 *value = cache_get(target, SLOT0);
1265 LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1266
1267 if (regnum == GDB_REGNO_MSTATUS)
1268 info->mstatus_actual = *value;
1269
1270 return ERROR_OK;
1271 }
1272
1273 /* Write the register. No caching or games. */
1274 static int register_write(struct target *target, unsigned int number,
1275 uint64_t value)
1276 {
1277 riscv011_info_t *info = get_info(target);
1278
1279 maybe_write_tselect(target);
1280
1281 if (number == S0) {
1282 cache_set_load(target, 0, S0, SLOT0);
1283 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH0));
1284 cache_set_jump(target, 2);
1285 } else if (number == S1) {
1286 cache_set_load(target, 0, S0, SLOT0);
1287 cache_set_store(target, 1, S0, SLOT_LAST);
1288 cache_set_jump(target, 2);
1289 } else if (number <= GDB_REGNO_XPR31) {
1290 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1291 cache_set_jump(target, 1);
1292 } else if (number == GDB_REGNO_PC) {
1293 info->dpc = value;
1294 return ERROR_OK;
1295 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1296 int result = update_mstatus_actual(target);
1297 if (result != ERROR_OK)
1298 return result;
1299 unsigned i = 0;
1300 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1301 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1302 cache_set_load(target, i++, S0, SLOT1);
1303 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1304 cache_set(target, SLOT1, info->mstatus_actual);
1305 }
1306
1307 if (riscv_xlen(target) == 32)
1308 cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1309 else
1310 cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1311 cache_set_jump(target, i++);
1312 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1313 cache_set_load(target, 0, S0, SLOT0);
1314 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1315 cache_set_jump(target, 2);
1316
1317 if (number == GDB_REGNO_MSTATUS)
1318 info->mstatus_actual = value;
1319 } else if (number == GDB_REGNO_PRIV) {
1320 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1321 return ERROR_OK;
1322 } else {
1323 LOG_ERROR("Don't know how to write register %d", number);
1324 return ERROR_FAIL;
1325 }
1326
1327 cache_set(target, SLOT0, value);
1328 if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1329 return ERROR_FAIL;
1330
1331 uint32_t exception = cache_get32(target, info->dramsize-1);
1332 if (exception) {
1333 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1334 gdb_regno_name(number));
1335 return ERROR_FAIL;
1336 }
1337
1338 return ERROR_OK;
1339 }
1340
1341 static int get_register(struct target *target, riscv_reg_t *value, int regid)
1342 {
1343 riscv011_info_t *info = get_info(target);
1344
1345 maybe_write_tselect(target);
1346
1347 if (regid <= GDB_REGNO_XPR31) {
1348 *value = reg_cache_get(target, regid);
1349 } else if (regid == GDB_REGNO_PC) {
1350 *value = info->dpc;
1351 } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1352 int result = update_mstatus_actual(target);
1353 if (result != ERROR_OK)
1354 return result;
1355 unsigned i = 0;
1356 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1357 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1358 cache_set_load(target, i++, S0, SLOT1);
1359 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1360 cache_set(target, SLOT1, info->mstatus_actual);
1361 }
1362
1363 if (riscv_xlen(target) == 32)
1364 cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1365 else
1366 cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1367 cache_set_jump(target, i++);
1368
1369 if (cache_write(target, 4, true) != ERROR_OK)
1370 return ERROR_FAIL;
1371 } else if (regid == GDB_REGNO_PRIV) {
1372 *value = get_field(info->dcsr, DCSR_PRV);
1373 } else {
1374 int result = register_read(target, value, regid);
1375 if (result != ERROR_OK)
1376 return result;
1377 }
1378
1379 if (regid == GDB_REGNO_MSTATUS)
1380 target->reg_cache->reg_list[regid].valid = true;
1381
1382 return ERROR_OK;
1383 }
1384
1385 static int set_register(struct target *target, int regid, uint64_t value)
1386 {
1387 return register_write(target, regid, value);
1388 }
1389
1390 static int halt(struct target *target)
1391 {
1392 LOG_DEBUG("riscv_halt()");
1393 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1394
1395 cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1396 cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1397 cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1398 cache_set_jump(target, 3);
1399
1400 if (cache_write(target, 4, true) != ERROR_OK) {
1401 LOG_ERROR("cache_write() failed.");
1402 return ERROR_FAIL;
1403 }
1404
1405 return ERROR_OK;
1406 }
1407
1408 static void deinit_target(struct target *target)
1409 {
1410 LOG_DEBUG("riscv_deinit_target()");
1411 struct riscv_info *info = target->arch_info;
1412 if (!info)
1413 return;
1414
1415 free(info->version_specific);
1416 info->version_specific = NULL;
1417 }
1418
1419 static int strict_step(struct target *target, bool announce)
1420 {
1421 LOG_DEBUG("enter");
1422
1423 struct watchpoint *watchpoint = target->watchpoints;
1424 while (watchpoint) {
1425 riscv_remove_watchpoint(target, watchpoint);
1426 watchpoint = watchpoint->next;
1427 }
1428
1429 int result = full_step(target, announce);
1430 if (result != ERROR_OK)
1431 return result;
1432
1433 watchpoint = target->watchpoints;
1434 while (watchpoint) {
1435 riscv_add_watchpoint(target, watchpoint);
1436 watchpoint = watchpoint->next;
1437 }
1438
1439 return ERROR_OK;
1440 }
1441
1442 static int step(struct target *target, int current, target_addr_t address,
1443 int handle_breakpoints)
1444 {
1445 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1446
1447 if (!current) {
1448 if (riscv_xlen(target) > 32) {
1449 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1450 riscv_xlen(target));
1451 }
1452 int result = register_write(target, GDB_REGNO_PC, address);
1453 if (result != ERROR_OK)
1454 return result;
1455 }
1456
1457 if (handle_breakpoints) {
1458 int result = strict_step(target, true);
1459 if (result != ERROR_OK)
1460 return result;
1461 } else {
1462 return full_step(target, false);
1463 }
1464
1465 return ERROR_OK;
1466 }
1467
1468 static int examine(struct target *target)
1469 {
1470 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1471
1472 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1473 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1474 LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1475 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1476 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1477 if (dtmcontrol == 0) {
1478 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1479 return ERROR_FAIL;
1480 }
1481 if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1482 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1483 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1484 return ERROR_FAIL;
1485 }
1486
1487 RISCV_INFO(r);
1488
1489 riscv011_info_t *info = get_info(target);
1490 info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1491 info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1492 if (info->dtmcontrol_idle == 0) {
1493 /* Some old SiFive cores don't set idle but need it to be 1. */
1494 uint32_t idcode = idcode_scan(target);
1495 if (idcode == 0x10e31913)
1496 info->dtmcontrol_idle = 1;
1497 }
1498
1499 uint32_t dminfo = dbus_read(target, DMINFO);
1500 LOG_DEBUG("dminfo: 0x%08x", dminfo);
1501 LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1502 LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1503 LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1504 LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1505 LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1506 LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1507 LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1508 LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1509 LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1510 LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1511 LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1512 LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
1513
1514 if (get_field(dminfo, DMINFO_VERSION) != 1) {
1515 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1516 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1517 return ERROR_FAIL;
1518 }
1519
1520 info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1521
1522 if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1523 LOG_ERROR("Authentication required by RISC-V core but not "
1524 "supported by OpenOCD. dminfo=0x%x", dminfo);
1525 return ERROR_FAIL;
1526 }
1527
1528 /* Pretend this is a 32-bit system until we have found out the true value. */
1529 r->xlen = 32;
1530
1531 /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1532 cache_set32(target, 0, xori(S1, ZERO, -1));
1533 /* 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff */
1534 cache_set32(target, 1, srli(S1, S1, 31));
1535 /* 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff */
1536 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1537 cache_set32(target, 3, srli(S1, S1, 31));
1538 /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
1539 cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1540 cache_set_jump(target, 5);
1541 for (unsigned i = 6; i < info->dramsize; i++)
1542 cache_set32(target, i, i * 0x01020304);
1543
1544 cache_write(target, 0, false);
1545
1546 /* Check that we can actually read/write dram. */
1547 if (cache_check(target) != ERROR_OK)
1548 return ERROR_FAIL;
1549
1550 cache_write(target, 0, true);
1551 cache_invalidate(target);
1552
1553 uint32_t word0 = cache_get32(target, 0);
1554 uint32_t word1 = cache_get32(target, 1);
1555 struct riscv_info *generic_info = riscv_info(target);
1556 if (word0 == 1 && word1 == 0) {
1557 generic_info->xlen = 32;
1558 } else if (word0 == 0xffffffff && word1 == 3) {
1559 generic_info->xlen = 64;
1560 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1561 generic_info->xlen = 128;
1562 } else {
1563 uint32_t exception = cache_get32(target, info->dramsize-1);
1564 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1565 word0, word1, exception);
1566 dump_debug_ram(target);
1567 return ERROR_FAIL;
1568 }
1569 LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1570
1571 if (read_remote_csr(target, &r->misa, CSR_MISA) != ERROR_OK) {
1572 const unsigned old_csr_misa = 0xf10;
1573 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1574 old_csr_misa);
1575 if (read_remote_csr(target, &r->misa, old_csr_misa) != ERROR_OK) {
1576 /* Maybe this is an old core that still has $misa at the old
1577 * address. */
1578 LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1579 return ERROR_FAIL;
1580 }
1581 }
1582
1583 /* Update register list to match discovered XLEN/supported extensions. */
1584 riscv_init_registers(target);
1585
1586 info->never_halted = true;
1587
1588 int result = riscv011_poll(target);
1589 if (result != ERROR_OK)
1590 return result;
1591
1592 target_set_examined(target);
1593 riscv_set_current_hartid(target, 0);
1594 for (size_t i = 0; i < 32; ++i)
1595 reg_cache_set(target, i, -1);
1596 LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1597 riscv_xlen(target), r->misa);
1598
1599 return ERROR_OK;
1600 }
1601
1602 static riscv_error_t handle_halt_routine(struct target *target)
1603 {
1604 riscv011_info_t *info = get_info(target);
1605
1606 scans_t *scans = scans_new(target, 256);
1607 if (!scans)
1608 return RE_FAIL;
1609
1610 /* Read all GPRs as fast as we can, because gdb is going to ask for them
1611 * anyway. Reading them one at a time is much slower. */
1612
1613 /* Write the jump back to address 1. */
1614 scans_add_write_jump(scans, 1, false);
1615 for (int reg = 1; reg < 32; reg++) {
1616 if (reg == S0 || reg == S1)
1617 continue;
1618
1619 /* Write store instruction. */
1620 scans_add_write_store(scans, 0, reg, SLOT0, true);
1621
1622 /* Read value. */
1623 scans_add_read(scans, SLOT0, false);
1624 }
1625
1626 /* Write store of s0 at index 1. */
1627 scans_add_write_store(scans, 1, S0, SLOT0, false);
1628 /* Write jump at index 2. */
1629 scans_add_write_jump(scans, 2, false);
1630
1631 /* Read S1 from debug RAM */
1632 scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1633 /* Read value. */
1634 scans_add_read(scans, SLOT0, false);
1635
1636 /* Read S0 from dscratch */
1637 unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR};
1638 for (unsigned int i = 0; i < ARRAY_SIZE(csr); i++) {
1639 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1640 scans_add_read(scans, SLOT0, false);
1641 }
1642
1643 /* Final read to get the last value out. */
1644 scans_add_read32(scans, 4, false);
1645
1646 int retval = scans_execute(scans);
1647 if (retval != ERROR_OK) {
1648 LOG_ERROR("JTAG execute failed: %d", retval);
1649 goto error;
1650 }
1651
1652 unsigned int dbus_busy = 0;
1653 unsigned int interrupt_set = 0;
1654 unsigned result = 0;
1655 uint64_t value = 0;
1656 reg_cache_set(target, 0, 0);
1657 /* The first scan result is the result from something old we don't care
1658 * about. */
1659 for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1660 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1661 DBUS_OP_SIZE);
1662 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1663 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1664 info->addrbits);
1665 switch (status) {
1666 case DBUS_STATUS_SUCCESS:
1667 break;
1668 case DBUS_STATUS_FAILED:
1669 LOG_ERROR("Debug access failed. Hardware error?");
1670 goto error;
1671 case DBUS_STATUS_BUSY:
1672 dbus_busy++;
1673 break;
1674 default:
1675 LOG_ERROR("Got invalid bus access status: %d", status);
1676 goto error;
1677 }
1678 if (data & DMCONTROL_INTERRUPT) {
1679 interrupt_set++;
1680 break;
1681 }
1682 if (address == 4 || address == 5) {
1683 unsigned int reg;
1684 switch (result) {
1685 case 0:
1686 reg = 1;
1687 break;
1688 case 1:
1689 reg = 2;
1690 break;
1691 case 2:
1692 reg = 3;
1693 break;
1694 case 3:
1695 reg = 4;
1696 break;
1697 case 4:
1698 reg = 5;
1699 break;
1700 case 5:
1701 reg = 6;
1702 break;
1703 case 6:
1704 reg = 7;
1705 break;
1706 /* S0 */
1707 /* S1 */
1708 case 7:
1709 reg = 10;
1710 break;
1711 case 8:
1712 reg = 11;
1713 break;
1714 case 9:
1715 reg = 12;
1716 break;
1717 case 10:
1718 reg = 13;
1719 break;
1720 case 11:
1721 reg = 14;
1722 break;
1723 case 12:
1724 reg = 15;
1725 break;
1726 case 13:
1727 reg = 16;
1728 break;
1729 case 14:
1730 reg = 17;
1731 break;
1732 case 15:
1733 reg = 18;
1734 break;
1735 case 16:
1736 reg = 19;
1737 break;
1738 case 17:
1739 reg = 20;
1740 break;
1741 case 18:
1742 reg = 21;
1743 break;
1744 case 19:
1745 reg = 22;
1746 break;
1747 case 20:
1748 reg = 23;
1749 break;
1750 case 21:
1751 reg = 24;
1752 break;
1753 case 22:
1754 reg = 25;
1755 break;
1756 case 23:
1757 reg = 26;
1758 break;
1759 case 24:
1760 reg = 27;
1761 break;
1762 case 25:
1763 reg = 28;
1764 break;
1765 case 26:
1766 reg = 29;
1767 break;
1768 case 27:
1769 reg = 30;
1770 break;
1771 case 28:
1772 reg = 31;
1773 break;
1774 case 29:
1775 reg = S1;
1776 break;
1777 case 30:
1778 reg = S0;
1779 break;
1780 case 31:
1781 reg = CSR_DPC;
1782 break;
1783 case 32:
1784 reg = CSR_DCSR;
1785 break;
1786 default:
1787 assert(0);
1788 LOG_ERROR("Got invalid register result %d", result);
1789 goto error;
1790 }
1791 if (riscv_xlen(target) == 32) {
1792 reg_cache_set(target, reg, data & 0xffffffff);
1793 result++;
1794 } else if (riscv_xlen(target) == 64) {
1795 if (address == 4) {
1796 value = data & 0xffffffff;
1797 } else if (address == 5) {
1798 reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1799 value = 0;
1800 result++;
1801 }
1802 }
1803 }
1804 }
1805
1806 scans_delete(scans);
1807
1808 if (dbus_busy) {
1809 increase_dbus_busy_delay(target);
1810 return RE_AGAIN;
1811 }
1812 if (interrupt_set) {
1813 increase_interrupt_high_delay(target);
1814 return RE_AGAIN;
1815 }
1816
1817 /* TODO: get rid of those 2 variables and talk to the cache directly. */
1818 info->dpc = reg_cache_get(target, CSR_DPC);
1819 info->dcsr = reg_cache_get(target, CSR_DCSR);
1820
1821 cache_invalidate(target);
1822
1823 return RE_OK;
1824
1825 error:
1826 scans_delete(scans);
1827 return RE_FAIL;
1828 }
1829
1830 static int handle_halt(struct target *target, bool announce)
1831 {
1832 riscv011_info_t *info = get_info(target);
1833 target->state = TARGET_HALTED;
1834
1835 riscv_error_t re;
1836 do {
1837 re = handle_halt_routine(target);
1838 } while (re == RE_AGAIN);
1839 if (re != RE_OK) {
1840 LOG_ERROR("handle_halt_routine failed");
1841 return ERROR_FAIL;
1842 }
1843
1844 int cause = get_field(info->dcsr, DCSR_CAUSE);
1845 switch (cause) {
1846 case DCSR_CAUSE_SWBP:
1847 target->debug_reason = DBG_REASON_BREAKPOINT;
1848 break;
1849 case DCSR_CAUSE_HWBP:
1850 target->debug_reason = DBG_REASON_WATCHPOINT;
1851 break;
1852 case DCSR_CAUSE_DEBUGINT:
1853 target->debug_reason = DBG_REASON_DBGRQ;
1854 break;
1855 case DCSR_CAUSE_STEP:
1856 target->debug_reason = DBG_REASON_SINGLESTEP;
1857 break;
1858 case DCSR_CAUSE_HALT:
1859 default:
1860 LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1861 cause, info->dcsr);
1862 }
1863
1864 if (info->never_halted) {
1865 info->never_halted = false;
1866
1867 int result = maybe_read_tselect(target);
1868 if (result != ERROR_OK)
1869 return result;
1870 riscv_enumerate_triggers(target);
1871 }
1872
1873 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1874 int retval;
1875 if (riscv_semihosting(target, &retval) != 0)
1876 return retval;
1877 }
1878
1879 if (announce)
1880 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1881
1882 const char *cause_string[] = {
1883 "none",
1884 "software breakpoint",
1885 "hardware trigger",
1886 "debug interrupt",
1887 "step",
1888 "halt"
1889 };
1890 /* This is logged to the user so that gdb will show it when a user types
1891 * 'monitor reset init'. At that time gdb appears to have the pc cached
1892 * still so if a user manually inspects the pc it will still have the old
1893 * value. */
1894 LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1895
1896 return ERROR_OK;
1897 }
1898
1899 static int poll_target(struct target *target, bool announce)
1900 {
1901 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1902
1903 /* Inhibit debug logging during poll(), which isn't usually interesting and
1904 * just fills up the screen/logs with clutter. */
1905 int old_debug_level = debug_level;
1906 if (debug_level >= LOG_LVL_DEBUG)
1907 debug_level = LOG_LVL_INFO;
1908 bits_t bits = read_bits(target);
1909 debug_level = old_debug_level;
1910
1911 if (bits.haltnot && bits.interrupt) {
1912 target->state = TARGET_DEBUG_RUNNING;
1913 LOG_DEBUG("debug running");
1914 } else if (bits.haltnot && !bits.interrupt) {
1915 if (target->state != TARGET_HALTED)
1916 return handle_halt(target, announce);
1917 } else if (!bits.haltnot && bits.interrupt) {
1918 /* Target is halting. There is no state for that, so don't change anything. */
1919 LOG_DEBUG("halting");
1920 } else if (!bits.haltnot && !bits.interrupt) {
1921 target->state = TARGET_RUNNING;
1922 }
1923
1924 return ERROR_OK;
1925 }
1926
1927 static int riscv011_poll(struct target *target)
1928 {
1929 return poll_target(target, true);
1930 }
1931
1932 static int riscv011_resume(struct target *target, int current,
1933 target_addr_t address, int handle_breakpoints, int debug_execution)
1934 {
1935 RISCV_INFO(r);
1936 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1937
1938 r->prepped = false;
1939 return resume(target, debug_execution, false);
1940 }
1941
1942 static int assert_reset(struct target *target)
1943 {
1944 riscv011_info_t *info = get_info(target);
1945 /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1946
1947 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1948
1949 /* The only assumption we can make is that the TAP was reset. */
1950 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1951 LOG_ERROR("Debug interrupt didn't clear.");
1952 return ERROR_FAIL;
1953 }
1954
1955 /* Not sure what we should do when there are multiple cores.
1956 * Here just reset the single hart we're talking to. */
1957 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1958 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1959 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1960 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1961 info->dcsr |= DCSR_HALT;
1962 if (target->reset_halt)
1963 info->dcsr |= DCSR_NDRESET;
1964 else
1965 info->dcsr |= DCSR_FULLRESET;
1966 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1967 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1968 /* We shouldn't actually need the jump because a reset should happen. */
1969 dram_write_jump(target, 2, false);
1970 dram_write32(target, 4, info->dcsr, true);
1971 cache_invalidate(target);
1972
1973 target->state = TARGET_RESET;
1974
1975 return ERROR_OK;
1976 }
1977
1978 static int deassert_reset(struct target *target)
1979 {
1980 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1981 if (target->reset_halt)
1982 return wait_for_state(target, TARGET_HALTED);
1983 else
1984 return wait_for_state(target, TARGET_RUNNING);
1985 }
1986
1987 static int read_memory(struct target *target, target_addr_t address,
1988 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
1989 {
1990 if (increment != size) {
1991 LOG_ERROR("read_memory with custom increment not implemented");
1992 return ERROR_NOT_IMPLEMENTED;
1993 }
1994
1995 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1996
1997 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
1998 switch (size) {
1999 case 1:
2000 cache_set32(target, 1, lb(S1, S0, 0));
2001 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2002 break;
2003 case 2:
2004 cache_set32(target, 1, lh(S1, S0, 0));
2005 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2006 break;
2007 case 4:
2008 cache_set32(target, 1, lw(S1, S0, 0));
2009 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2010 break;
2011 default:
2012 LOG_ERROR("Unsupported size: %d", size);
2013 return ERROR_FAIL;
2014 }
2015 cache_set_jump(target, 3);
2016 cache_write(target, CACHE_NO_READ, false);
2017
2018 riscv011_info_t *info = get_info(target);
2019 const unsigned max_batch_size = 256;
2020 scans_t *scans = scans_new(target, max_batch_size);
2021 if (!scans)
2022 return ERROR_FAIL;
2023
2024 uint32_t result_value = 0x777;
2025 uint32_t i = 0;
2026 while (i < count + 3) {
2027 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2028 scans_reset(scans);
2029
2030 for (unsigned int j = 0; j < batch_size; j++) {
2031 if (i + j == count) {
2032 /* Just insert a read so we can scan out the last value. */
2033 scans_add_read32(scans, 4, false);
2034 } else if (i + j >= count + 1) {
2035 /* And check for errors. */
2036 scans_add_read32(scans, info->dramsize-1, false);
2037 } else {
2038 /* Write the next address and set interrupt. */
2039 uint32_t offset = size * (i + j);
2040 scans_add_write32(scans, 4, address + offset, true);
2041 }
2042 }
2043
2044 int retval = scans_execute(scans);
2045 if (retval != ERROR_OK) {
2046 LOG_ERROR("JTAG execute failed: %d", retval);
2047 goto error;
2048 }
2049
2050 int dbus_busy = 0;
2051 int execute_busy = 0;
2052 for (unsigned int j = 0; j < batch_size; j++) {
2053 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2054 DBUS_OP_SIZE);
2055 switch (status) {
2056 case DBUS_STATUS_SUCCESS:
2057 break;
2058 case DBUS_STATUS_FAILED:
2059 LOG_ERROR("Debug RAM write failed. Hardware error?");
2060 goto error;
2061 case DBUS_STATUS_BUSY:
2062 dbus_busy++;
2063 break;
2064 default:
2065 LOG_ERROR("Got invalid bus access status: %d", status);
2066 return ERROR_FAIL;
2067 }
2068 uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2069 DBUS_DATA_SIZE);
2070 if (data & DMCONTROL_INTERRUPT)
2071 execute_busy++;
2072 if (i + j == count + 2) {
2073 result_value = data;
2074 } else if (i + j > 1) {
2075 uint32_t offset = size * (i + j - 2);
2076 switch (size) {
2077 case 1:
2078 buffer[offset] = data;
2079 break;
2080 case 2:
2081 buffer[offset] = data;
2082 buffer[offset+1] = data >> 8;
2083 break;
2084 case 4:
2085 buffer[offset] = data;
2086 buffer[offset+1] = data >> 8;
2087 buffer[offset+2] = data >> 16;
2088 buffer[offset+3] = data >> 24;
2089 break;
2090 }
2091 }
2092 LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2093 }
2094 if (dbus_busy)
2095 increase_dbus_busy_delay(target);
2096 if (execute_busy)
2097 increase_interrupt_high_delay(target);
2098 if (dbus_busy || execute_busy) {
2099 wait_for_debugint_clear(target, false);
2100
2101 /* Retry. */
2102 LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2103 " with more delays", address + size * i);
2104 } else {
2105 i += batch_size;
2106 }
2107 }
2108
2109 if (result_value != 0) {
2110 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2111 TARGET_PRIxADDR, result_value, address + size * (count-1));
2112 if (count > 1) {
2113 LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2114 " and 0x%" TARGET_PRIxADDR " as well, but we "
2115 "didn't check then.)",
2116 address, address + size * (count-2) + size - 1);
2117 }
2118 goto error;
2119 }
2120
2121 scans_delete(scans);
2122 cache_clean(target);
2123 return ERROR_OK;
2124
2125 error:
2126 scans_delete(scans);
2127 cache_clean(target);
2128 return ERROR_FAIL;
2129 }
2130
2131 static int setup_write_memory(struct target *target, uint32_t size)
2132 {
2133 switch (size) {
2134 case 1:
2135 cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2136 cache_set32(target, 1, sb(S0, T0, 0));
2137 break;
2138 case 2:
2139 cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2140 cache_set32(target, 1, sh(S0, T0, 0));
2141 break;
2142 case 4:
2143 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2144 cache_set32(target, 1, sw(S0, T0, 0));
2145 break;
2146 default:
2147 LOG_ERROR("Unsupported size: %d", size);
2148 return ERROR_FAIL;
2149 }
2150 cache_set32(target, 2, addi(T0, T0, size));
2151 cache_set_jump(target, 3);
2152 cache_write(target, 4, false);
2153
2154 return ERROR_OK;
2155 }
2156
2157 static int write_memory(struct target *target, target_addr_t address,
2158 uint32_t size, uint32_t count, const uint8_t *buffer)
2159 {
2160 riscv011_info_t *info = get_info(target);
2161 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2162
2163 /* Set up the address. */
2164 cache_set_store(target, 0, T0, SLOT1);
2165 cache_set_load(target, 1, T0, SLOT0);
2166 cache_set_jump(target, 2);
2167 cache_set(target, SLOT0, address);
2168 if (cache_write(target, 5, true) != ERROR_OK)
2169 return ERROR_FAIL;
2170
2171 uint64_t t0 = cache_get(target, SLOT1);
2172 LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2173
2174 if (setup_write_memory(target, size) != ERROR_OK)
2175 return ERROR_FAIL;
2176
2177 const unsigned max_batch_size = 256;
2178 scans_t *scans = scans_new(target, max_batch_size);
2179 if (!scans)
2180 return ERROR_FAIL;
2181
2182 uint32_t result_value = 0x777;
2183 uint32_t i = 0;
2184 while (i < count + 2) {
2185 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2186 scans_reset(scans);
2187
2188 for (unsigned int j = 0; j < batch_size; j++) {
2189 if (i + j >= count) {
2190 /* Check for an exception. */
2191 scans_add_read32(scans, info->dramsize-1, false);
2192 } else {
2193 /* Write the next value and set interrupt. */
2194 uint32_t value;
2195 uint32_t offset = size * (i + j);
2196 switch (size) {
2197 case 1:
2198 value = buffer[offset];
2199 break;
2200 case 2:
2201 value = buffer[offset] |
2202 (buffer[offset+1] << 8);
2203 break;
2204 case 4:
2205 value = buffer[offset] |
2206 ((uint32_t) buffer[offset+1] << 8) |
2207 ((uint32_t) buffer[offset+2] << 16) |
2208 ((uint32_t) buffer[offset+3] << 24);
2209 break;
2210 default:
2211 goto error;
2212 }
2213
2214 scans_add_write32(scans, 4, value, true);
2215 }
2216 }
2217
2218 int retval = scans_execute(scans);
2219 if (retval != ERROR_OK) {
2220 LOG_ERROR("JTAG execute failed: %d", retval);
2221 goto error;
2222 }
2223
2224 int dbus_busy = 0;
2225 int execute_busy = 0;
2226 for (unsigned int j = 0; j < batch_size; j++) {
2227 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2228 DBUS_OP_SIZE);
2229 switch (status) {
2230 case DBUS_STATUS_SUCCESS:
2231 break;
2232 case DBUS_STATUS_FAILED:
2233 LOG_ERROR("Debug RAM write failed. Hardware error?");
2234 goto error;
2235 case DBUS_STATUS_BUSY:
2236 dbus_busy++;
2237 break;
2238 default:
2239 LOG_ERROR("Got invalid bus access status: %d", status);
2240 return ERROR_FAIL;
2241 }
2242 int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2243 if (interrupt)
2244 execute_busy++;
2245 if (i + j == count + 1)
2246 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2247 }
2248 if (dbus_busy)
2249 increase_dbus_busy_delay(target);
2250 if (execute_busy)
2251 increase_interrupt_high_delay(target);
2252 if (dbus_busy || execute_busy) {
2253 wait_for_debugint_clear(target, false);
2254
2255 /* Retry.
2256 * Set t0 back to what it should have been at the beginning of this
2257 * batch. */
2258 LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2259 " with more delays", address + size * i);
2260
2261 cache_clean(target);
2262
2263 if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2264 goto error;
2265
2266 if (setup_write_memory(target, size) != ERROR_OK)
2267 goto error;
2268 } else {
2269 i += batch_size;
2270 }
2271 }
2272
2273 if (result_value != 0) {
2274 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2275 TARGET_PRIxADDR, result_value, address + size * (count-1));
2276 if (count > 1) {
2277 LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2278 " and 0x%" TARGET_PRIxADDR " as well, but we "
2279 "didn't check then.)",
2280 address, address + size * (count-2) + size - 1);
2281 }
2282 goto error;
2283 }
2284
2285 scans_delete(scans);
2286 cache_clean(target);
2287 return register_write(target, T0, t0);
2288
2289 error:
2290 scans_delete(scans);
2291 cache_clean(target);
2292 return ERROR_FAIL;
2293 }
2294
2295 static int arch_state(struct target *target)
2296 {
2297 return ERROR_OK;
2298 }
2299
2300 static COMMAND_HELPER(riscv011_print_info, struct target *target)
2301 {
2302 /* Abstract description. */
2303 riscv_print_info_line(CMD, "target", "memory.read_while_running8", 0);
2304 riscv_print_info_line(CMD, "target", "memory.write_while_running8", 0);
2305 riscv_print_info_line(CMD, "target", "memory.read_while_running16", 0);
2306 riscv_print_info_line(CMD, "target", "memory.write_while_running16", 0);
2307 riscv_print_info_line(CMD, "target", "memory.read_while_running32", 0);
2308 riscv_print_info_line(CMD, "target", "memory.write_while_running32", 0);
2309 riscv_print_info_line(CMD, "target", "memory.read_while_running64", 0);
2310 riscv_print_info_line(CMD, "target", "memory.write_while_running64", 0);
2311 riscv_print_info_line(CMD, "target", "memory.read_while_running128", 0);
2312 riscv_print_info_line(CMD, "target", "memory.write_while_running128", 0);
2313
2314 uint32_t dminfo = dbus_read(target, DMINFO);
2315 riscv_print_info_line(CMD, "dm", "authenticated", get_field(dminfo, DMINFO_AUTHENTICATED));
2316
2317 return 0;
2318 }
2319
2320 static int wait_for_authbusy(struct target *target)
2321 {
2322 time_t start = time(NULL);
2323 while (1) {
2324 uint32_t dminfo = dbus_read(target, DMINFO);
2325 if (!get_field(dminfo, DMINFO_AUTHBUSY))
2326 break;
2327 if (time(NULL) - start > riscv_command_timeout_sec) {
2328 LOG_ERROR("Timed out after %ds waiting for authbusy to go low (dminfo=0x%x). "
2329 "Increase the timeout with riscv set_command_timeout_sec.",
2330 riscv_command_timeout_sec,
2331 dminfo);
2332 return ERROR_FAIL;
2333 }
2334 }
2335
2336 return ERROR_OK;
2337 }
2338
2339 static int riscv011_authdata_read(struct target *target, uint32_t *value, unsigned int index)
2340 {
2341 if (index > 1) {
2342 LOG_ERROR("Spec 0.11 only has a two authdata registers.");
2343 return ERROR_FAIL;
2344 }
2345
2346 if (wait_for_authbusy(target) != ERROR_OK)
2347 return ERROR_FAIL;
2348
2349 uint16_t authdata_address = index ? DMAUTHDATA1 : DMAUTHDATA0;
2350 *value = dbus_read(target, authdata_address);
2351
2352 return ERROR_OK;
2353 }
2354
2355 static int riscv011_authdata_write(struct target *target, uint32_t value, unsigned int index)
2356 {
2357 if (index > 1) {
2358 LOG_ERROR("Spec 0.11 only has a two authdata registers.");
2359 return ERROR_FAIL;
2360 }
2361
2362 if (wait_for_authbusy(target) != ERROR_OK)
2363 return ERROR_FAIL;
2364
2365 uint16_t authdata_address = index ? DMAUTHDATA1 : DMAUTHDATA0;
2366 dbus_write(target, authdata_address, value);
2367
2368 return ERROR_OK;
2369 }
2370
2371 static int init_target(struct command_context *cmd_ctx,
2372 struct target *target)
2373 {
2374 LOG_DEBUG("init");
2375 RISCV_INFO(generic_info);
2376 generic_info->get_register = get_register;
2377 generic_info->set_register = set_register;
2378 generic_info->read_memory = read_memory;
2379 generic_info->authdata_read = &riscv011_authdata_read;
2380 generic_info->authdata_write = &riscv011_authdata_write;
2381 generic_info->print_info = &riscv011_print_info;
2382
2383 generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
2384 if (!generic_info->version_specific)
2385 return ERROR_FAIL;
2386
2387 /* Assume 32-bit until we discover the real value in examine(). */
2388 generic_info->xlen = 32;
2389 riscv_init_registers(target);
2390
2391 return ERROR_OK;
2392 }
2393
2394 struct target_type riscv011_target = {
2395 .name = "riscv",
2396
2397 .init_target = init_target,
2398 .deinit_target = deinit_target,
2399 .examine = examine,
2400
2401 /* poll current target status */
2402 .poll = riscv011_poll,
2403
2404 .halt = halt,
2405 .resume = riscv011_resume,
2406 .step = step,
2407
2408 .assert_reset = assert_reset,
2409 .deassert_reset = deassert_reset,
2410
2411 .write_memory = write_memory,
2412
2413 .arch_state = arch_state,
2414 };
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