9 #include "target/target.h"
10 #include "target/algorithm.h"
11 #include "target/target_type.h"
13 #include "jtag/jtag.h"
14 #include "target/register.h"
15 #include "target/breakpoints.h"
16 #include "helper/time_support.h"
19 #include "rtos/rtos.h"
22 * Since almost everything can be accomplish by scanning the dbus register, all
23 * functions here assume dbus is already selected. The exception are functions
24 * called directly by OpenOCD, which can't assume anything about what's
25 * currently in IR. They should set IR to dbus explicitly.
31 * At the bottom of the stack are the OpenOCD JTAG functions:
36 * There are a few functions to just instantly shift a register and get its
42 * Because doing one scan and waiting for the result is slow, most functions
43 * batch up a bunch of dbus writes and then execute them all at once. They use
44 * the scans "class" for this:
49 * Usually you new(), call a bunch of add functions, then execute() and look
50 * at the results by calling scans_get...()
52 * Optimized functions will directly use the scans class above, but slightly
53 * lazier code will use the cache functions that in turn use the scans
58 * cache_set... update a local structure, which is then synced to the target
59 * with cache_write(). Only Debug RAM words that are actually changed are sent
60 * to the target. Afterwards use cache_get... to read results.
63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
66 #define DIM(x) (sizeof(x)/sizeof(*x))
68 /* Constants for legacy SiFive hardware breakpoints. */
69 #define CSR_BPCONTROL_X (1<<0)
70 #define CSR_BPCONTROL_W (1<<1)
71 #define CSR_BPCONTROL_R (1<<2)
72 #define CSR_BPCONTROL_U (1<<3)
73 #define CSR_BPCONTROL_S (1<<4)
74 #define CSR_BPCONTROL_H (1<<5)
75 #define CSR_BPCONTROL_M (1<<6)
76 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
77 #define CSR_BPCONTROL_BPACTION (0xff<<11)
79 #define DEBUG_ROM_START 0x800
80 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
81 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
82 #define DEBUG_RAM_START 0x400
84 #define SETHALTNOT 0x10c
86 /*** JTAG registers. ***/
88 #define DTMCONTROL 0x10
89 #define DTMCONTROL_DBUS_RESET (1<<16)
90 #define DTMCONTROL_IDLE (7<<10)
91 #define DTMCONTROL_ADDRBITS (0xf<<4)
92 #define DTMCONTROL_VERSION (0xf)
95 #define DBUS_OP_START 0
96 #define DBUS_OP_SIZE 2
103 DBUS_STATUS_SUCCESS
= 0,
104 DBUS_STATUS_FAILED
= 2,
107 #define DBUS_DATA_START 2
108 #define DBUS_DATA_SIZE 34
109 #define DBUS_ADDRESS_START 36
123 /*** Debug Bus registers. ***/
125 #define DMCONTROL 0x10
126 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
127 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
128 #define DMCONTROL_BUSERROR (7<<19)
129 #define DMCONTROL_SERIAL (3<<16)
130 #define DMCONTROL_AUTOINCREMENT (1<<15)
131 #define DMCONTROL_ACCESS (7<<12)
132 #define DMCONTROL_HARTID (0x3ff<<2)
133 #define DMCONTROL_NDRESET (1<<1)
134 #define DMCONTROL_FULLRESET 1
137 #define DMINFO_ABUSSIZE (0x7fU<<25)
138 #define DMINFO_SERIALCOUNT (0xf<<21)
139 #define DMINFO_ACCESS128 (1<<20)
140 #define DMINFO_ACCESS64 (1<<19)
141 #define DMINFO_ACCESS32 (1<<18)
142 #define DMINFO_ACCESS16 (1<<17)
143 #define DMINFO_ACCESS8 (1<<16)
144 #define DMINFO_DRAMSIZE (0x3f<<10)
145 #define DMINFO_AUTHENTICATED (1<<5)
146 #define DMINFO_AUTHBUSY (1<<4)
147 #define DMINFO_AUTHTYPE (3<<2)
148 #define DMINFO_VERSION 3
150 /*** Info about the core being debugged. ***/
152 #define DBUS_ADDRESS_UNKNOWN 0xffff
155 #define DRAM_CACHE_SIZE 16
157 uint8_t ir_dtmcontrol
[1] = {DTMCONTROL
};
158 struct scan_field select_dtmcontrol
= {
160 .out_value
= ir_dtmcontrol
162 uint8_t ir_dbus
[1] = {DBUS
};
163 struct scan_field select_dbus
= {
167 uint8_t ir_idcode
[1] = {0x1};
168 struct scan_field select_idcode
= {
170 .out_value
= ir_idcode
178 bool read
, write
, execute
;
182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
183 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
186 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
188 bool riscv_prefer_sba
;
190 /* In addition to the ones in the standard spec, we'll also expose additional
192 * The list is either NULL, or a series of ranges (inclusive), terminated with
198 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
200 struct scan_field field
;
202 uint8_t out_value
[4];
204 buf_set_u32(out_value
, 0, 32, out
);
206 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
209 field
.out_value
= out_value
;
210 field
.in_value
= in_value
;
211 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
213 /* Always return to dbus. */
214 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
216 int retval
= jtag_execute_queue();
217 if (retval
!= ERROR_OK
) {
218 LOG_ERROR("failed jtag scan: %d", retval
);
222 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
223 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
228 static struct target_type
*get_target_type(struct target
*target
)
230 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
233 LOG_ERROR("Target has not been initialized");
237 switch (info
->dtm_version
) {
239 return &riscv011_target
;
241 return &riscv013_target
;
243 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
248 static int riscv_init_target(struct command_context
*cmd_ctx
,
249 struct target
*target
)
251 LOG_DEBUG("riscv_init_target()");
252 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
253 if (!target
->arch_info
)
255 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
256 riscv_info_init(target
, info
);
257 info
->cmd_ctx
= cmd_ctx
;
259 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
260 select_dbus
.num_bits
= target
->tap
->ir_length
;
261 select_idcode
.num_bits
= target
->tap
->ir_length
;
263 riscv_semihosting_init(target
);
268 static void riscv_deinit_target(struct target
*target
)
270 LOG_DEBUG("riscv_deinit_target()");
271 struct target_type
*tt
= get_target_type(target
);
273 tt
->deinit_target(target
);
274 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
277 target
->arch_info
= NULL
;
280 static int oldriscv_halt(struct target
*target
)
282 struct target_type
*tt
= get_target_type(target
);
283 return tt
->halt(target
);
286 static void trigger_from_breakpoint(struct trigger
*trigger
,
287 const struct breakpoint
*breakpoint
)
289 trigger
->address
= breakpoint
->address
;
290 trigger
->length
= breakpoint
->length
;
291 trigger
->mask
= ~0LL;
292 trigger
->read
= false;
293 trigger
->write
= false;
294 trigger
->execute
= true;
295 /* unique_id is unique across both breakpoints and watchpoints. */
296 trigger
->unique_id
= breakpoint
->unique_id
;
299 static int maybe_add_trigger_t1(struct target
*target
, unsigned hartid
,
300 struct trigger
*trigger
, uint64_t tdata1
)
304 const uint32_t bpcontrol_x
= 1<<0;
305 const uint32_t bpcontrol_w
= 1<<1;
306 const uint32_t bpcontrol_r
= 1<<2;
307 const uint32_t bpcontrol_u
= 1<<3;
308 const uint32_t bpcontrol_s
= 1<<4;
309 const uint32_t bpcontrol_h
= 1<<5;
310 const uint32_t bpcontrol_m
= 1<<6;
311 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
312 const uint32_t bpcontrol_bpaction
= 0xff << 11;
314 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
315 /* Trigger is already in use, presumably by user code. */
316 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
319 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
320 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
321 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
322 tdata1
= set_field(tdata1
, bpcontrol_u
,
323 !!(r
->misa
[hartid
] & (1 << ('U' - 'A'))));
324 tdata1
= set_field(tdata1
, bpcontrol_s
,
325 !!(r
->misa
[hartid
] & (1 << ('S' - 'A'))));
326 tdata1
= set_field(tdata1
, bpcontrol_h
,
327 !!(r
->misa
[hartid
] & (1 << ('H' - 'A'))));
328 tdata1
|= bpcontrol_m
;
329 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
330 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
332 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
334 riscv_reg_t tdata1_rb
;
335 if (riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
,
336 GDB_REGNO_TDATA1
) != ERROR_OK
)
338 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
340 if (tdata1
!= tdata1_rb
) {
341 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
342 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
344 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
345 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
348 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
353 static int maybe_add_trigger_t2(struct target
*target
, unsigned hartid
,
354 struct trigger
*trigger
, uint64_t tdata1
)
358 /* tselect is already set */
359 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
360 /* Trigger is already in use, presumably by user code. */
361 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
364 /* address/data match trigger */
365 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
366 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
367 MCONTROL_ACTION_DEBUG_MODE
);
368 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
369 tdata1
|= MCONTROL_M
;
370 if (r
->misa
[hartid
] & (1 << ('H' - 'A')))
371 tdata1
|= MCONTROL_H
;
372 if (r
->misa
[hartid
] & (1 << ('S' - 'A')))
373 tdata1
|= MCONTROL_S
;
374 if (r
->misa
[hartid
] & (1 << ('U' - 'A')))
375 tdata1
|= MCONTROL_U
;
377 if (trigger
->execute
)
378 tdata1
|= MCONTROL_EXECUTE
;
380 tdata1
|= MCONTROL_LOAD
;
382 tdata1
|= MCONTROL_STORE
;
384 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
387 int result
= riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
, GDB_REGNO_TDATA1
);
388 if (result
!= ERROR_OK
)
390 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
392 if (tdata1
!= tdata1_rb
) {
393 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
394 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
396 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
400 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
405 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
409 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
412 /* In RTOS mode, we need to set the same trigger in the same slot on every
413 * hart, to keep up the illusion that each hart is a thread running on the
416 /* Otherwise, we just set the trigger on the one hart this target deals
419 riscv_reg_t tselect
[RISCV_MAX_HARTS
];
422 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
423 if (!riscv_hart_enabled(target
, hartid
))
427 int result
= riscv_get_register_on_hart(target
, &tselect
[hartid
],
428 hartid
, GDB_REGNO_TSELECT
);
429 if (result
!= ERROR_OK
)
432 assert(first_hart
>= 0);
435 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
436 if (r
->trigger_unique_id
[i
] != -1)
439 riscv_set_register_on_hart(target
, first_hart
, GDB_REGNO_TSELECT
, i
);
442 int result
= riscv_get_register_on_hart(target
, &tdata1
, first_hart
,
444 if (result
!= ERROR_OK
)
446 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
449 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
450 if (!riscv_hart_enabled(target
, hartid
))
452 if (hartid
> first_hart
)
453 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
456 result
= maybe_add_trigger_t1(target
, hartid
, trigger
, tdata1
);
459 result
= maybe_add_trigger_t2(target
, hartid
, trigger
, tdata1
);
462 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
466 if (result
!= ERROR_OK
)
470 if (result
!= ERROR_OK
)
473 LOG_DEBUG("Using trigger %d (type %d) for bp %d", i
, type
,
475 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
479 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
480 if (!riscv_hart_enabled(target
, hartid
))
482 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
,
486 if (i
>= r
->trigger_count
[first_hart
]) {
487 LOG_ERROR("Couldn't find an available hardware trigger.");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
494 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
496 if (breakpoint
->type
== BKPT_SOFT
) {
497 if (target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
498 breakpoint
->orig_instr
) != ERROR_OK
) {
499 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
500 breakpoint
->address
);
505 if (breakpoint
->length
== 4)
506 retval
= target_write_u32(target
, breakpoint
->address
, ebreak());
508 retval
= target_write_u16(target
, breakpoint
->address
, ebreak_c());
509 if (retval
!= ERROR_OK
) {
510 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
511 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
515 } else if (breakpoint
->type
== BKPT_HARD
) {
516 struct trigger trigger
;
517 trigger_from_breakpoint(&trigger
, breakpoint
);
518 int result
= add_trigger(target
, &trigger
);
519 if (result
!= ERROR_OK
)
523 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
524 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
527 breakpoint
->set
= true;
532 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
536 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
540 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
541 if (!riscv_hart_enabled(target
, hartid
))
543 if (first_hart
< 0) {
548 assert(first_hart
>= 0);
551 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
552 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
555 if (i
>= r
->trigger_count
[first_hart
]) {
556 LOG_ERROR("Couldn't find the hardware resources used by hardware "
560 LOG_DEBUG("Stop using resource %d for bp %d", i
, trigger
->unique_id
);
561 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
562 if (!riscv_hart_enabled(target
, hartid
))
565 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
, GDB_REGNO_TSELECT
);
566 if (result
!= ERROR_OK
)
568 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
569 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
570 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
572 r
->trigger_unique_id
[i
] = -1;
577 int riscv_remove_breakpoint(struct target
*target
,
578 struct breakpoint
*breakpoint
)
580 if (breakpoint
->type
== BKPT_SOFT
) {
581 if (target_write_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
582 breakpoint
->orig_instr
) != ERROR_OK
) {
583 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
584 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
588 } else if (breakpoint
->type
== BKPT_HARD
) {
589 struct trigger trigger
;
590 trigger_from_breakpoint(&trigger
, breakpoint
);
591 int result
= remove_trigger(target
, &trigger
);
592 if (result
!= ERROR_OK
)
596 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
597 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
600 breakpoint
->set
= false;
605 static void trigger_from_watchpoint(struct trigger
*trigger
,
606 const struct watchpoint
*watchpoint
)
608 trigger
->address
= watchpoint
->address
;
609 trigger
->length
= watchpoint
->length
;
610 trigger
->mask
= watchpoint
->mask
;
611 trigger
->value
= watchpoint
->value
;
612 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
613 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
614 trigger
->execute
= false;
615 /* unique_id is unique across both breakpoints and watchpoints. */
616 trigger
->unique_id
= watchpoint
->unique_id
;
619 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
621 struct trigger trigger
;
622 trigger_from_watchpoint(&trigger
, watchpoint
);
624 int result
= add_trigger(target
, &trigger
);
625 if (result
!= ERROR_OK
)
627 watchpoint
->set
= true;
632 int riscv_remove_watchpoint(struct target
*target
,
633 struct watchpoint
*watchpoint
)
635 struct trigger trigger
;
636 trigger_from_watchpoint(&trigger
, watchpoint
);
638 int result
= remove_trigger(target
, &trigger
);
639 if (result
!= ERROR_OK
)
641 watchpoint
->set
= false;
646 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
647 int handle_breakpoints
)
649 struct target_type
*tt
= get_target_type(target
);
650 return tt
->step(target
, current
, address
, handle_breakpoints
);
653 static int old_or_new_riscv_step(
654 struct target
*target
,
656 target_addr_t address
,
657 int handle_breakpoints
660 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
661 if (r
->is_halted
== NULL
)
662 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
664 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
668 static int riscv_examine(struct target
*target
)
670 LOG_DEBUG("riscv_examine()");
671 if (target_was_examined(target
)) {
672 LOG_DEBUG("Target was already examined.");
676 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
678 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
679 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
680 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
681 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
682 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
684 struct target_type
*tt
= get_target_type(target
);
688 int result
= tt
->init_target(info
->cmd_ctx
, target
);
689 if (result
!= ERROR_OK
)
692 return tt
->examine(target
);
695 static int oldriscv_poll(struct target
*target
)
697 struct target_type
*tt
= get_target_type(target
);
698 return tt
->poll(target
);
701 static int old_or_new_riscv_poll(struct target
*target
)
704 if (r
->is_halted
== NULL
)
705 return oldriscv_poll(target
);
707 return riscv_openocd_poll(target
);
710 static int old_or_new_riscv_halt(struct target
*target
)
713 if (r
->is_halted
== NULL
)
714 return oldriscv_halt(target
);
716 return riscv_openocd_halt(target
);
719 static int riscv_assert_reset(struct target
*target
)
721 struct target_type
*tt
= get_target_type(target
);
722 return tt
->assert_reset(target
);
725 static int riscv_deassert_reset(struct target
*target
)
727 LOG_DEBUG("RISCV DEASSERT RESET");
728 struct target_type
*tt
= get_target_type(target
);
729 return tt
->deassert_reset(target
);
733 static int oldriscv_resume(struct target
*target
, int current
, uint32_t address
,
734 int handle_breakpoints
, int debug_execution
)
736 struct target_type
*tt
= get_target_type(target
);
737 return tt
->resume(target
, current
, address
, handle_breakpoints
,
741 static int old_or_new_riscv_resume(
742 struct target
*target
,
744 target_addr_t address
,
745 int handle_breakpoints
,
749 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
750 if (r
->is_halted
== NULL
)
751 return oldriscv_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
753 return riscv_openocd_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
756 static int riscv_select_current_hart(struct target
*target
)
759 if (r
->rtos_hartid
!= -1 && riscv_rtos_enabled(target
))
760 return riscv_set_current_hartid(target
, r
->rtos_hartid
);
762 return riscv_set_current_hartid(target
, target
->coreid
);
765 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
766 uint32_t size
, uint32_t count
, uint8_t *buffer
)
768 if (riscv_select_current_hart(target
) != ERROR_OK
)
770 struct target_type
*tt
= get_target_type(target
);
771 return tt
->read_memory(target
, address
, size
, count
, buffer
);
774 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
775 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
777 if (riscv_select_current_hart(target
) != ERROR_OK
)
779 struct target_type
*tt
= get_target_type(target
);
780 return tt
->write_memory(target
, address
, size
, count
, buffer
);
783 static int riscv_get_gdb_reg_list(struct target
*target
,
784 struct reg
**reg_list
[], int *reg_list_size
,
785 enum target_register_class reg_class
)
788 LOG_DEBUG("reg_class=%d", reg_class
);
789 LOG_DEBUG("rtos_hartid=%d current_hartid=%d", r
->rtos_hartid
, r
->current_hartid
);
791 if (!target
->reg_cache
) {
792 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
796 if (riscv_select_current_hart(target
) != ERROR_OK
)
800 case REG_CLASS_GENERAL
:
804 *reg_list_size
= GDB_REGNO_COUNT
;
807 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
811 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
815 for (int i
= 0; i
< *reg_list_size
; i
++) {
816 assert(!target
->reg_cache
->reg_list
[i
].valid
||
817 target
->reg_cache
->reg_list
[i
].size
> 0);
818 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
824 static int riscv_arch_state(struct target
*target
)
826 struct target_type
*tt
= get_target_type(target
);
827 return tt
->arch_state(target
);
830 /* Algorithm must end with a software breakpoint instruction. */
831 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
832 struct mem_param
*mem_params
, int num_reg_params
,
833 struct reg_param
*reg_params
, target_addr_t entry_point
,
834 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
836 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
838 if (num_mem_params
> 0) {
839 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
843 if (target
->state
!= TARGET_HALTED
) {
844 LOG_WARNING("target not halted");
845 return ERROR_TARGET_NOT_HALTED
;
849 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", 1);
850 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
852 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
854 uint64_t saved_regs
[32];
855 for (int i
= 0; i
< num_reg_params
; i
++) {
856 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
857 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
859 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
863 if (r
->size
!= reg_params
[i
].size
) {
864 LOG_ERROR("Register %s is %d bits instead of %d bits.",
865 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
869 if (r
->number
> GDB_REGNO_XPR31
) {
870 LOG_ERROR("Only GPRs can be use as argument registers.");
874 if (r
->type
->get(r
) != ERROR_OK
)
876 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
877 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
882 /* Disable Interrupts before attempting to run the algorithm. */
883 uint64_t current_mstatus
;
884 uint8_t mstatus_bytes
[8];
886 LOG_DEBUG("Disabling Interrupts");
887 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
890 LOG_ERROR("Couldn't find mstatus!");
894 reg_mstatus
->type
->get(reg_mstatus
);
895 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
896 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
897 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], set_field(current_mstatus
,
900 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
903 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
904 if (oldriscv_resume(target
, 0, entry_point
, 0, 0) != ERROR_OK
)
907 int64_t start
= timeval_ms();
908 while (target
->state
!= TARGET_HALTED
) {
910 int64_t now
= timeval_ms();
911 if (now
- start
> timeout_ms
) {
912 LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms
);
913 LOG_ERROR(" now = 0x%08x", (uint32_t) now
);
914 LOG_ERROR(" start = 0x%08x", (uint32_t) start
);
915 oldriscv_halt(target
);
916 old_or_new_riscv_poll(target
);
917 return ERROR_TARGET_TIMEOUT
;
920 int result
= old_or_new_riscv_poll(target
);
921 if (result
!= ERROR_OK
)
925 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
927 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
928 if (final_pc
!= exit_point
) {
929 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
930 TARGET_PRIxADDR
, final_pc
, exit_point
);
934 /* Restore Interrupts */
935 LOG_DEBUG("Restoring Interrupts");
936 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], current_mstatus
);
937 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
939 /* Restore registers */
941 buf_set_u64(buf
, 0, info
->xlen
[0], saved_pc
);
942 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
945 for (int i
= 0; i
< num_reg_params
; i
++) {
946 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
947 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
948 buf_set_u64(buf
, 0, info
->xlen
[0], saved_regs
[r
->number
]);
949 if (r
->type
->set(r
, buf
) != ERROR_OK
)
956 /* Should run code on the target to perform CRC of
957 memory. Not yet implemented.
960 static int riscv_checksum_memory(struct target
*target
,
961 target_addr_t address
, uint32_t count
,
964 *checksum
= 0xFFFFFFFF;
965 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
968 /*** OpenOCD Helper Functions ***/
970 enum riscv_poll_hart
{
972 RPH_DISCOVERED_HALTED
,
973 RPH_DISCOVERED_RUNNING
,
976 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
979 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
982 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
984 /* If OpenOCD thinks we're running but this hart is halted then it's time
985 * to raise an event. */
986 bool halted
= riscv_is_halted(target
);
987 if (target
->state
!= TARGET_HALTED
&& halted
) {
988 LOG_DEBUG(" triggered a halt");
990 return RPH_DISCOVERED_HALTED
;
991 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
992 LOG_DEBUG(" triggered running");
993 target
->state
= TARGET_RUNNING
;
994 return RPH_DISCOVERED_RUNNING
;
997 return RPH_NO_CHANGE
;
1000 /*** OpenOCD Interface ***/
1001 int riscv_openocd_poll(struct target
*target
)
1003 LOG_DEBUG("polling all harts");
1004 int halted_hart
= -1;
1005 if (riscv_rtos_enabled(target
)) {
1006 /* Check every hart for an event. */
1007 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1008 enum riscv_poll_hart out
= riscv_poll_hart(target
, i
);
1011 case RPH_DISCOVERED_RUNNING
:
1013 case RPH_DISCOVERED_HALTED
:
1020 if (halted_hart
== -1) {
1021 LOG_DEBUG(" no harts just halted, target->state=%d", target
->state
);
1024 LOG_DEBUG(" hart %d halted", halted_hart
);
1026 /* If we're here then at least one hart triggered. That means
1027 * we want to go and halt _every_ hart in the system, as that's
1028 * the invariant we hold here. Some harts might have already
1029 * halted (as we're either in single-step mode or they also
1030 * triggered a breakpoint), so don't attempt to halt those
1032 for (int i
= 0; i
< riscv_count_harts(target
); ++i
)
1033 riscv_halt_one_hart(target
, i
);
1035 enum riscv_poll_hart out
= riscv_poll_hart(target
,
1036 riscv_current_hartid(target
));
1037 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
)
1039 else if (out
== RPH_ERROR
)
1042 halted_hart
= riscv_current_hartid(target
);
1043 LOG_DEBUG(" hart %d halted", halted_hart
);
1046 target
->state
= TARGET_HALTED
;
1047 switch (riscv_halt_reason(target
, halted_hart
)) {
1048 case RISCV_HALT_BREAKPOINT
:
1049 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1051 case RISCV_HALT_TRIGGER
:
1052 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1054 case RISCV_HALT_INTERRUPT
:
1055 target
->debug_reason
= DBG_REASON_DBGRQ
;
1057 case RISCV_HALT_SINGLESTEP
:
1058 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1060 case RISCV_HALT_UNKNOWN
:
1061 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1063 case RISCV_HALT_ERROR
:
1067 if (riscv_rtos_enabled(target
)) {
1068 target
->rtos
->current_threadid
= halted_hart
+ 1;
1069 target
->rtos
->current_thread
= halted_hart
+ 1;
1072 target
->state
= TARGET_HALTED
;
1074 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
1076 if (riscv_semihosting(target
, &retval
) != 0)
1080 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1084 int riscv_openocd_halt(struct target
*target
)
1088 LOG_DEBUG("halting all harts");
1090 int out
= riscv_halt_all_harts(target
);
1091 if (out
!= ERROR_OK
) {
1092 LOG_ERROR("Unable to halt all harts");
1096 register_cache_invalidate(target
->reg_cache
);
1097 if (riscv_rtos_enabled(target
)) {
1098 target
->rtos
->current_threadid
= r
->rtos_hartid
+ 1;
1099 target
->rtos
->current_thread
= r
->rtos_hartid
+ 1;
1102 target
->state
= TARGET_HALTED
;
1103 target
->debug_reason
= DBG_REASON_DBGRQ
;
1104 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1108 int riscv_openocd_resume(
1109 struct target
*target
,
1111 target_addr_t address
,
1112 int handle_breakpoints
,
1113 int debug_execution
)
1115 LOG_DEBUG("debug_reason=%d", target
->debug_reason
);
1118 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1120 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1121 /* To be able to run off a trigger, disable all the triggers, step, and
1122 * then resume as usual. */
1123 struct watchpoint
*watchpoint
= target
->watchpoints
;
1124 bool trigger_temporarily_cleared
[RISCV_MAX_HWBPS
] = {0};
1127 int result
= ERROR_OK
;
1128 while (watchpoint
&& result
== ERROR_OK
) {
1129 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1130 trigger_temporarily_cleared
[i
] = watchpoint
->set
;
1131 if (watchpoint
->set
)
1132 result
= riscv_remove_watchpoint(target
, watchpoint
);
1133 watchpoint
= watchpoint
->next
;
1137 if (result
== ERROR_OK
)
1138 result
= riscv_step_rtos_hart(target
);
1140 watchpoint
= target
->watchpoints
;
1142 while (watchpoint
) {
1143 LOG_DEBUG("watchpoint %d: cleared=%d", i
, trigger_temporarily_cleared
[i
]);
1144 if (trigger_temporarily_cleared
[i
]) {
1145 if (result
== ERROR_OK
)
1146 result
= riscv_add_watchpoint(target
, watchpoint
);
1148 riscv_add_watchpoint(target
, watchpoint
);
1150 watchpoint
= watchpoint
->next
;
1154 if (result
!= ERROR_OK
)
1158 int out
= riscv_resume_all_harts(target
);
1159 if (out
!= ERROR_OK
) {
1160 LOG_ERROR("unable to resume all harts");
1164 register_cache_invalidate(target
->reg_cache
);
1165 target
->state
= TARGET_RUNNING
;
1166 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1170 int riscv_openocd_step(
1171 struct target
*target
,
1173 target_addr_t address
,
1174 int handle_breakpoints
1176 LOG_DEBUG("stepping rtos hart");
1179 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1181 int out
= riscv_step_rtos_hart(target
);
1182 if (out
!= ERROR_OK
) {
1183 LOG_ERROR("unable to step rtos hart");
1187 register_cache_invalidate(target
->reg_cache
);
1188 target
->state
= TARGET_RUNNING
;
1189 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1190 target
->state
= TARGET_HALTED
;
1191 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1192 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1196 /* Command Handlers */
1197 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
1199 if (CMD_ARGC
!= 1) {
1200 LOG_ERROR("Command takes exactly 1 parameter");
1201 return ERROR_COMMAND_SYNTAX_ERROR
;
1203 int timeout
= atoi(CMD_ARGV
[0]);
1205 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1209 riscv_command_timeout_sec
= timeout
;
1214 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
1216 if (CMD_ARGC
!= 1) {
1217 LOG_ERROR("Command takes exactly 1 parameter");
1218 return ERROR_COMMAND_SYNTAX_ERROR
;
1220 int timeout
= atoi(CMD_ARGV
[0]);
1222 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
1226 riscv_reset_timeout_sec
= timeout
;
1230 COMMAND_HANDLER(riscv_set_prefer_sba
)
1232 if (CMD_ARGC
!= 1) {
1233 LOG_ERROR("Command takes exactly 1 parameter");
1234 return ERROR_COMMAND_SYNTAX_ERROR
;
1236 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_prefer_sba
);
1240 void parse_error(const char *string
, char c
, unsigned position
)
1242 char buf
[position
+2];
1243 for (unsigned i
= 0; i
< position
; i
++)
1245 buf
[position
] = '^';
1246 buf
[position
+ 1] = 0;
1248 LOG_ERROR("Parse error at character %c in:", c
);
1249 LOG_ERROR("%s", string
);
1250 LOG_ERROR("%s", buf
);
1253 COMMAND_HANDLER(riscv_set_expose_csrs
)
1255 if (CMD_ARGC
!= 1) {
1256 LOG_ERROR("Command takes exactly 1 parameter");
1257 return ERROR_COMMAND_SYNTAX_ERROR
;
1260 for (unsigned pass
= 0; pass
< 2; pass
++) {
1263 bool parse_low
= true;
1265 for (unsigned i
= 0; i
== 0 || CMD_ARGV
[0][i
-1]; i
++) {
1266 char c
= CMD_ARGV
[0][i
];
1268 /* Ignore whitespace. */
1276 } else if (c
== '-') {
1278 } else if (c
== ',' || c
== 0) {
1280 expose_csr
[range
].low
= low
;
1281 expose_csr
[range
].high
= low
;
1286 parse_error(CMD_ARGV
[0], c
, i
);
1287 return ERROR_COMMAND_SYNTAX_ERROR
;
1294 } else if (c
== ',' || c
== 0) {
1297 expose_csr
[range
].low
= low
;
1298 expose_csr
[range
].high
= high
;
1304 parse_error(CMD_ARGV
[0], c
, i
);
1305 return ERROR_COMMAND_SYNTAX_ERROR
;
1313 expose_csr
= calloc(range
+ 2, sizeof(*expose_csr
));
1315 expose_csr
[range
].low
= 1;
1316 expose_csr
[range
].high
= 0;
1322 COMMAND_HANDLER(riscv_authdata_read
)
1324 if (CMD_ARGC
!= 0) {
1325 LOG_ERROR("Command takes no parameters");
1326 return ERROR_COMMAND_SYNTAX_ERROR
;
1329 struct target
*target
= get_current_target(CMD_CTX
);
1331 LOG_ERROR("target is NULL!");
1337 LOG_ERROR("riscv_info is NULL!");
1341 if (r
->authdata_read
) {
1343 if (r
->authdata_read(target
, &value
) != ERROR_OK
)
1345 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1348 LOG_ERROR("authdata_read is not implemented for this target.");
1353 COMMAND_HANDLER(riscv_authdata_write
)
1355 if (CMD_ARGC
!= 1) {
1356 LOG_ERROR("Command takes exactly 1 argument");
1357 return ERROR_COMMAND_SYNTAX_ERROR
;
1360 struct target
*target
= get_current_target(CMD_CTX
);
1364 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
1366 if (r
->authdata_write
) {
1367 return r
->authdata_write(target
, value
);
1369 LOG_ERROR("authdata_write is not implemented for this target.");
1374 COMMAND_HANDLER(riscv_dmi_read
)
1376 if (CMD_ARGC
!= 1) {
1377 LOG_ERROR("Command takes 1 parameter");
1378 return ERROR_COMMAND_SYNTAX_ERROR
;
1381 struct target
*target
= get_current_target(CMD_CTX
);
1383 LOG_ERROR("target is NULL!");
1389 LOG_ERROR("riscv_info is NULL!");
1394 uint32_t address
, value
;
1395 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1396 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
1398 command_print(CMD_CTX
, "0x%" PRIx32
, value
);
1401 LOG_ERROR("dmi_read is not implemented for this target.");
1407 COMMAND_HANDLER(riscv_dmi_write
)
1409 if (CMD_ARGC
!= 2) {
1410 LOG_ERROR("Command takes exactly 2 arguments");
1411 return ERROR_COMMAND_SYNTAX_ERROR
;
1414 struct target
*target
= get_current_target(CMD_CTX
);
1417 uint32_t address
, value
;
1418 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
1419 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
1422 return r
->dmi_write(target
, address
, value
);
1424 LOG_ERROR("dmi_write is not implemented for this target.");
1429 static const struct command_registration riscv_exec_command_handlers
[] = {
1431 .name
= "set_command_timeout_sec",
1432 .handler
= riscv_set_command_timeout_sec
,
1433 .mode
= COMMAND_ANY
,
1434 .usage
= "riscv set_command_timeout_sec [sec]",
1435 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
1438 .name
= "set_reset_timeout_sec",
1439 .handler
= riscv_set_reset_timeout_sec
,
1440 .mode
= COMMAND_ANY
,
1441 .usage
= "riscv set_reset_timeout_sec [sec]",
1442 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
1445 .name
= "set_prefer_sba",
1446 .handler
= riscv_set_prefer_sba
,
1447 .mode
= COMMAND_ANY
,
1448 .usage
= "riscv set_prefer_sba on|off",
1449 .help
= "When on, prefer to use System Bus Access to access memory. "
1450 "When off, prefer to use the Program Buffer to access memory."
1453 .name
= "expose_csrs",
1454 .handler
= riscv_set_expose_csrs
,
1455 .mode
= COMMAND_ANY
,
1456 .usage
= "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1457 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
1458 "addition to the standard ones. This must be executed before "
1462 .name
= "authdata_read",
1463 .handler
= riscv_authdata_read
,
1464 .mode
= COMMAND_ANY
,
1465 .usage
= "riscv authdata_read",
1466 .help
= "Return the 32-bit value read from authdata."
1469 .name
= "authdata_write",
1470 .handler
= riscv_authdata_write
,
1471 .mode
= COMMAND_ANY
,
1472 .usage
= "riscv authdata_write value",
1473 .help
= "Write the 32-bit value to authdata."
1477 .handler
= riscv_dmi_read
,
1478 .mode
= COMMAND_ANY
,
1479 .usage
= "riscv dmi_read address",
1480 .help
= "Perform a 32-bit DMI read at address, returning the value."
1483 .name
= "dmi_write",
1484 .handler
= riscv_dmi_write
,
1485 .mode
= COMMAND_ANY
,
1486 .usage
= "riscv dmi_write address value",
1487 .help
= "Perform a 32-bit DMI write of value at address."
1489 COMMAND_REGISTRATION_DONE
1492 extern __COMMAND_HANDLER(handle_common_semihosting_command
);
1493 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command
);
1494 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command
);
1495 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline
);
1498 * To be noted that RISC-V targets use the same semihosting commands as
1501 * The main reason is compatibility with existing tools. For example the
1502 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1503 * configure semihosting, which generate commands like `arm semihosting
1505 * A secondary reason is the fact that the protocol used is exactly the
1506 * one specified by ARM. If RISC-V will ever define its own semihosting
1507 * protocol, then a command like `riscv semihosting enable` will make
1508 * sense, but for now all semihosting commands are prefixed with `arm`.
1510 static const struct command_registration arm_exec_command_handlers
[] = {
1513 .handler
= handle_common_semihosting_command
,
1514 .mode
= COMMAND_EXEC
,
1515 .usage
= "['enable'|'disable']",
1516 .help
= "activate support for semihosting operations",
1519 "semihosting_cmdline",
1520 .handler
= handle_common_semihosting_cmdline
,
1521 .mode
= COMMAND_EXEC
,
1522 .usage
= "arguments",
1523 .help
= "command line arguments to be passed to program",
1526 "semihosting_fileio",
1527 .handler
= handle_common_semihosting_fileio_command
,
1528 .mode
= COMMAND_EXEC
,
1529 .usage
= "['enable'|'disable']",
1530 .help
= "activate support for semihosting fileio operations",
1533 "semihosting_resexit",
1534 .handler
= handle_common_semihosting_resumable_exit_command
,
1535 .mode
= COMMAND_EXEC
,
1536 .usage
= "['enable'|'disable']",
1537 .help
= "activate support for semihosting resumable exit",
1539 COMMAND_REGISTRATION_DONE
1542 const struct command_registration riscv_command_handlers
[] = {
1545 .mode
= COMMAND_ANY
,
1546 .help
= "RISC-V Command Group",
1548 .chain
= riscv_exec_command_handlers
1552 .mode
= COMMAND_ANY
,
1553 .help
= "ARM Command Group",
1555 .chain
= arm_exec_command_handlers
1557 COMMAND_REGISTRATION_DONE
1560 struct target_type riscv_target
= {
1563 .init_target
= riscv_init_target
,
1564 .deinit_target
= riscv_deinit_target
,
1565 .examine
= riscv_examine
,
1567 /* poll current target status */
1568 .poll
= old_or_new_riscv_poll
,
1570 .halt
= old_or_new_riscv_halt
,
1571 .resume
= old_or_new_riscv_resume
,
1572 .step
= old_or_new_riscv_step
,
1574 .assert_reset
= riscv_assert_reset
,
1575 .deassert_reset
= riscv_deassert_reset
,
1577 .read_memory
= riscv_read_memory
,
1578 .write_memory
= riscv_write_memory
,
1580 .checksum_memory
= riscv_checksum_memory
,
1582 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
1584 .add_breakpoint
= riscv_add_breakpoint
,
1585 .remove_breakpoint
= riscv_remove_breakpoint
,
1587 .add_watchpoint
= riscv_add_watchpoint
,
1588 .remove_watchpoint
= riscv_remove_watchpoint
,
1590 .arch_state
= riscv_arch_state
,
1592 .run_algorithm
= riscv_run_algorithm
,
1594 .commands
= riscv_command_handlers
1597 /*** RISC-V Interface ***/
1599 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
1601 memset(r
, 0, sizeof(*r
));
1603 r
->registers_initialized
= false;
1604 r
->current_hartid
= target
->coreid
;
1606 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
1608 for (size_t h
= 0; h
< RISCV_MAX_HARTS
; ++h
) {
1611 for (size_t e
= 0; e
< RISCV_MAX_REGISTERS
; ++e
)
1612 r
->valid_saved_registers
[h
][e
] = false;
1616 int riscv_halt_all_harts(struct target
*target
)
1618 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1619 if (!riscv_hart_enabled(target
, i
))
1622 riscv_halt_one_hart(target
, i
);
1628 int riscv_halt_one_hart(struct target
*target
, int hartid
)
1631 LOG_DEBUG("halting hart %d", hartid
);
1632 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1634 if (riscv_is_halted(target
)) {
1635 LOG_DEBUG(" hart %d requested halt, but was already halted", hartid
);
1639 return r
->halt_current_hart(target
);
1642 int riscv_resume_all_harts(struct target
*target
)
1644 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1645 if (!riscv_hart_enabled(target
, i
))
1648 riscv_resume_one_hart(target
, i
);
1651 riscv_invalidate_register_cache(target
);
1655 int riscv_resume_one_hart(struct target
*target
, int hartid
)
1658 LOG_DEBUG("resuming hart %d", hartid
);
1659 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1661 if (!riscv_is_halted(target
)) {
1662 LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid
);
1666 r
->on_resume(target
);
1667 return r
->resume_current_hart(target
);
1670 int riscv_step_rtos_hart(struct target
*target
)
1673 int hartid
= r
->current_hartid
;
1674 if (riscv_rtos_enabled(target
)) {
1675 hartid
= r
->rtos_hartid
;
1677 LOG_USER("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
1681 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1683 LOG_DEBUG("stepping hart %d", hartid
);
1685 if (!riscv_is_halted(target
)) {
1686 LOG_ERROR("Hart isn't halted before single step!");
1689 riscv_invalidate_register_cache(target
);
1691 if (r
->step_current_hart(target
) != ERROR_OK
)
1693 riscv_invalidate_register_cache(target
);
1695 if (!riscv_is_halted(target
)) {
1696 LOG_ERROR("Hart was not halted after single step!");
1702 bool riscv_supports_extension(struct target
*target
, int hartid
, char letter
)
1706 if (letter
>= 'a' && letter
<= 'z')
1708 else if (letter
>= 'A' && letter
<= 'Z')
1712 return r
->misa
[hartid
] & (1 << num
);
1715 int riscv_xlen(const struct target
*target
)
1717 return riscv_xlen_of_hart(target
, riscv_current_hartid(target
));
1720 int riscv_xlen_of_hart(const struct target
*target
, int hartid
)
1723 assert(r
->xlen
[hartid
] != -1);
1724 return r
->xlen
[hartid
];
1727 bool riscv_rtos_enabled(const struct target
*target
)
1729 return target
->rtos
!= NULL
;
1732 int riscv_set_current_hartid(struct target
*target
, int hartid
)
1735 if (!r
->select_current_hart
)
1738 int previous_hartid
= riscv_current_hartid(target
);
1739 r
->current_hartid
= hartid
;
1740 assert(riscv_hart_enabled(target
, hartid
));
1741 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
1742 if (r
->select_current_hart(target
) != ERROR_OK
)
1745 /* This might get called during init, in which case we shouldn't be
1746 * setting up the register cache. */
1747 if (!target_was_examined(target
))
1750 /* Avoid invalidating the register cache all the time. */
1751 if (r
->registers_initialized
1752 && (!riscv_rtos_enabled(target
) || (previous_hartid
== hartid
))
1753 && target
->reg_cache
->reg_list
[GDB_REGNO_ZERO
].size
== (unsigned)riscv_xlen(target
)
1754 && (!riscv_rtos_enabled(target
) || (r
->rtos_hartid
!= -1))) {
1757 LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target
));
1759 riscv_invalidate_register_cache(target
);
1763 void riscv_invalidate_register_cache(struct target
*target
)
1767 register_cache_invalidate(target
->reg_cache
);
1768 for (size_t i
= 0; i
< GDB_REGNO_COUNT
; ++i
) {
1769 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
1773 r
->registers_initialized
= true;
1776 int riscv_current_hartid(const struct target
*target
)
1779 return r
->current_hartid
;
1782 void riscv_set_all_rtos_harts(struct target
*target
)
1785 r
->rtos_hartid
= -1;
1788 void riscv_set_rtos_hartid(struct target
*target
, int hartid
)
1790 LOG_DEBUG("setting RTOS hartid %d", hartid
);
1792 r
->rtos_hartid
= hartid
;
1795 int riscv_count_harts(struct target
*target
)
1802 return r
->hart_count
;
1805 bool riscv_has_register(struct target
*target
, int hartid
, int regid
)
1811 * This function is called when the debug user wants to change the value of a
1812 * register. The new value may be cached, and may not be written until the hart
1814 int riscv_set_register(struct target
*target
, enum gdb_regno r
, riscv_reg_t v
)
1816 return riscv_set_register_on_hart(target
, riscv_current_hartid(target
), r
, v
);
1819 int riscv_set_register_on_hart(struct target
*target
, int hartid
,
1820 enum gdb_regno regid
, uint64_t value
)
1823 LOG_DEBUG("[%d] %s <- %" PRIx64
, hartid
, gdb_regno_name(regid
), value
);
1824 assert(r
->set_register
);
1825 return r
->set_register(target
, hartid
, regid
, value
);
1828 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
1831 return riscv_get_register_on_hart(target
, value
,
1832 riscv_current_hartid(target
), r
);
1835 int riscv_get_register_on_hart(struct target
*target
, riscv_reg_t
*value
,
1836 int hartid
, enum gdb_regno regid
)
1839 int result
= r
->get_register(target
, value
, hartid
, regid
);
1840 LOG_DEBUG("[%d] %s: %" PRIx64
, hartid
, gdb_regno_name(regid
), *value
);
1844 bool riscv_is_halted(struct target
*target
)
1847 assert(r
->is_halted
);
1848 return r
->is_halted(target
);
1851 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
1854 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1855 return RISCV_HALT_ERROR
;
1856 if (!riscv_is_halted(target
)) {
1857 LOG_ERROR("Hart is not halted!");
1858 return RISCV_HALT_UNKNOWN
;
1860 return r
->halt_reason(target
);
1863 size_t riscv_debug_buffer_size(struct target
*target
)
1866 return r
->debug_buffer_size
[riscv_current_hartid(target
)];
1869 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
1872 r
->write_debug_buffer(target
, index
, insn
);
1876 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
1879 return r
->read_debug_buffer(target
, index
);
1882 int riscv_execute_debug_buffer(struct target
*target
)
1885 return r
->execute_debug_buffer(target
);
1888 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
1891 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
1894 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
1897 r
->fill_dmi_read_u64(target
, buf
, a
);
1900 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
1903 r
->fill_dmi_nop_u64(target
, buf
);
1906 int riscv_dmi_write_u64_bits(struct target
*target
)
1909 return r
->dmi_write_u64_bits(target
);
1912 bool riscv_hart_enabled(struct target
*target
, int hartid
)
1914 /* FIXME: Add a hart mask to the RTOS. */
1915 if (riscv_rtos_enabled(target
))
1916 return hartid
< riscv_count_harts(target
);
1918 return hartid
== target
->coreid
;
1922 * Count triggers, and initialize trigger_count for each hart.
1923 * trigger_count is initialized even if this function fails to discover
1925 * Disable any hardware triggers that have dmode set. We can't have set them
1926 * ourselves. Maybe they're left over from some killed debug session.
1928 int riscv_enumerate_triggers(struct target
*target
)
1932 if (r
->triggers_enumerated
)
1935 r
->triggers_enumerated
= true; /* At the very least we tried. */
1937 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
1938 if (!riscv_hart_enabled(target
, hartid
))
1941 riscv_reg_t tselect
;
1942 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
,
1944 if (result
!= ERROR_OK
)
1947 for (unsigned t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
1948 r
->trigger_count
[hartid
] = t
;
1950 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, t
);
1951 uint64_t tselect_rb
;
1952 result
= riscv_get_register_on_hart(target
, &tselect_rb
, hartid
,
1954 if (result
!= ERROR_OK
)
1956 /* Mask off the top bit, which is used as tdrmode in old
1957 * implementations. */
1958 tselect_rb
&= ~(1ULL << (riscv_xlen(target
)-1));
1959 if (tselect_rb
!= t
)
1962 result
= riscv_get_register_on_hart(target
, &tdata1
, hartid
,
1964 if (result
!= ERROR_OK
)
1967 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
1970 /* On these older cores we don't support software using
1972 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
1975 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
1976 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
1981 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
1983 LOG_INFO("[%d] Found %d triggers", hartid
, r
->trigger_count
[hartid
]);
1989 const char *gdb_regno_name(enum gdb_regno regno
)
1991 static char buf
[32];
1994 case GDB_REGNO_ZERO
:
2002 case GDB_REGNO_FPR0
:
2004 case GDB_REGNO_FPR31
:
2006 case GDB_REGNO_CSR0
:
2008 case GDB_REGNO_TSELECT
:
2010 case GDB_REGNO_TDATA1
:
2012 case GDB_REGNO_TDATA2
:
2014 case GDB_REGNO_MISA
:
2018 case GDB_REGNO_DCSR
:
2020 case GDB_REGNO_DSCRATCH
:
2022 case GDB_REGNO_MSTATUS
:
2024 case GDB_REGNO_PRIV
:
2027 if (regno
<= GDB_REGNO_XPR31
)
2028 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
2029 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
2030 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
2031 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
2032 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
2034 sprintf(buf
, "gdb_regno_%d", regno
);
2039 static int register_get(struct reg
*reg
)
2041 struct target
*target
= (struct target
*) reg
->arch_info
;
2043 int result
= riscv_get_register(target
, &value
, reg
->number
);
2044 if (result
!= ERROR_OK
)
2046 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
2050 static int register_set(struct reg
*reg
, uint8_t *buf
)
2052 struct target
*target
= (struct target
*) reg
->arch_info
;
2054 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
2056 LOG_DEBUG("write 0x%" PRIx64
" to %s", value
, reg
->name
);
2057 struct reg
*r
= &target
->reg_cache
->reg_list
[reg
->number
];
2059 memcpy(r
->value
, buf
, (r
->size
+ 7) / 8);
2061 riscv_set_register(target
, reg
->number
, value
);
2065 static struct reg_arch_type riscv_reg_arch_type
= {
2066 .get
= register_get
,
2075 static int cmp_csr_info(const void *p1
, const void *p2
)
2077 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
2080 int riscv_init_registers(struct target
*target
)
2084 if (target
->reg_cache
) {
2085 if (target
->reg_cache
->reg_list
)
2086 free(target
->reg_cache
->reg_list
);
2087 free(target
->reg_cache
);
2090 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
2091 target
->reg_cache
->name
= "RISC-V Registers";
2092 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
2094 target
->reg_cache
->reg_list
= calloc(GDB_REGNO_COUNT
, sizeof(struct reg
));
2096 const unsigned int max_reg_name_len
= 12;
2097 if (info
->reg_names
)
2098 free(info
->reg_names
);
2099 info
->reg_names
= calloc(1, GDB_REGNO_COUNT
* max_reg_name_len
);
2100 char *reg_name
= info
->reg_names
;
2102 static struct reg_feature feature_cpu
= {
2103 .name
= "org.gnu.gdb.riscv.cpu"
2105 static struct reg_feature feature_fpu
= {
2106 .name
= "org.gnu.gdb.riscv.fpu"
2108 static struct reg_feature feature_csr
= {
2109 .name
= "org.gnu.gdb.riscv.csr"
2111 static struct reg_feature feature_virtual
= {
2112 .name
= "org.gnu.gdb.riscv.virtual"
2115 static struct reg_data_type type_ieee_single
= {
2116 .type
= REG_TYPE_IEEE_SINGLE
,
2119 static struct reg_data_type type_ieee_double
= {
2120 .type
= REG_TYPE_IEEE_DOUBLE
,
2123 struct csr_info csr_info
[] = {
2124 #define DECLARE_CSR(name, number) { number, #name },
2125 #include "encoding.h"
2128 /* encoding.h does not contain the registers in sorted order. */
2129 qsort(csr_info
, DIM(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
2130 unsigned csr_info_index
= 0;
2132 /* When gdb request register N, gdb_get_register_packet() assumes that this
2133 * is register at index N in reg_list. So if there are certain registers
2134 * that don't exist, we need to leave holes in the list (or renumber, but
2135 * it would be nice not to have yet another set of numbers to translate
2137 for (uint32_t number
= 0; number
< GDB_REGNO_COUNT
; number
++) {
2138 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
2142 r
->type
= &riscv_reg_arch_type
;
2143 r
->arch_info
= target
;
2145 r
->size
= riscv_xlen(target
);
2146 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2147 * target is in theory allowed to change XLEN on us. But I expect a lot
2148 * of other things to break in that case as well. */
2149 if (number
<= GDB_REGNO_XPR31
) {
2150 r
->caller_save
= true;
2152 case GDB_REGNO_ZERO
:
2249 r
->group
= "general";
2250 r
->feature
= &feature_cpu
;
2251 } else if (number
== GDB_REGNO_PC
) {
2252 r
->caller_save
= true;
2253 sprintf(reg_name
, "pc");
2254 r
->group
= "general";
2255 r
->feature
= &feature_cpu
;
2256 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
2257 r
->caller_save
= true;
2258 if (riscv_supports_extension(target
, riscv_current_hartid(target
),
2260 r
->reg_data_type
= &type_ieee_double
;
2262 } else if (riscv_supports_extension(target
,
2263 riscv_current_hartid(target
), 'F')) {
2264 r
->reg_data_type
= &type_ieee_single
;
2348 case GDB_REGNO_FS10
:
2351 case GDB_REGNO_FS11
:
2360 case GDB_REGNO_FT10
:
2363 case GDB_REGNO_FT11
:
2368 r
->feature
= &feature_fpu
;
2369 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
2371 r
->feature
= &feature_csr
;
2372 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
2374 while (csr_info
[csr_info_index
].number
< csr_number
&&
2375 csr_info_index
< DIM(csr_info
) - 1) {
2378 if (csr_info
[csr_info_index
].number
== csr_number
) {
2379 r
->name
= csr_info
[csr_info_index
].name
;
2381 sprintf(reg_name
, "csr%d", csr_number
);
2382 /* Assume unnamed registers don't exist, unless we have some
2383 * configuration that tells us otherwise. That's important
2384 * because eg. Eclipse crashes if a target has too many
2385 * registers, and apparently has no way of only showing a
2386 * subset of registers in any case. */
2390 switch (csr_number
) {
2394 r
->exist
= riscv_supports_extension(target
,
2395 riscv_current_hartid(target
), 'F');
2397 r
->feature
= &feature_fpu
;
2403 case CSR_SCOUNTEREN
:
2409 r
->exist
= riscv_supports_extension(target
,
2410 riscv_current_hartid(target
), 'S');
2414 /* "In systems with only M-mode, or with both M-mode and
2415 * U-mode but without U-mode trap support, the medeleg and
2416 * mideleg registers should not exist." */
2417 r
->exist
= riscv_supports_extension(target
, riscv_current_hartid(target
), 'S') ||
2418 riscv_supports_extension(target
, riscv_current_hartid(target
), 'N');
2424 case CSR_HPMCOUNTER3H
:
2425 case CSR_HPMCOUNTER4H
:
2426 case CSR_HPMCOUNTER5H
:
2427 case CSR_HPMCOUNTER6H
:
2428 case CSR_HPMCOUNTER7H
:
2429 case CSR_HPMCOUNTER8H
:
2430 case CSR_HPMCOUNTER9H
:
2431 case CSR_HPMCOUNTER10H
:
2432 case CSR_HPMCOUNTER11H
:
2433 case CSR_HPMCOUNTER12H
:
2434 case CSR_HPMCOUNTER13H
:
2435 case CSR_HPMCOUNTER14H
:
2436 case CSR_HPMCOUNTER15H
:
2437 case CSR_HPMCOUNTER16H
:
2438 case CSR_HPMCOUNTER17H
:
2439 case CSR_HPMCOUNTER18H
:
2440 case CSR_HPMCOUNTER19H
:
2441 case CSR_HPMCOUNTER20H
:
2442 case CSR_HPMCOUNTER21H
:
2443 case CSR_HPMCOUNTER22H
:
2444 case CSR_HPMCOUNTER23H
:
2445 case CSR_HPMCOUNTER24H
:
2446 case CSR_HPMCOUNTER25H
:
2447 case CSR_HPMCOUNTER26H
:
2448 case CSR_HPMCOUNTER27H
:
2449 case CSR_HPMCOUNTER28H
:
2450 case CSR_HPMCOUNTER29H
:
2451 case CSR_HPMCOUNTER30H
:
2452 case CSR_HPMCOUNTER31H
:
2455 case CSR_MHPMCOUNTER3H
:
2456 case CSR_MHPMCOUNTER4H
:
2457 case CSR_MHPMCOUNTER5H
:
2458 case CSR_MHPMCOUNTER6H
:
2459 case CSR_MHPMCOUNTER7H
:
2460 case CSR_MHPMCOUNTER8H
:
2461 case CSR_MHPMCOUNTER9H
:
2462 case CSR_MHPMCOUNTER10H
:
2463 case CSR_MHPMCOUNTER11H
:
2464 case CSR_MHPMCOUNTER12H
:
2465 case CSR_MHPMCOUNTER13H
:
2466 case CSR_MHPMCOUNTER14H
:
2467 case CSR_MHPMCOUNTER15H
:
2468 case CSR_MHPMCOUNTER16H
:
2469 case CSR_MHPMCOUNTER17H
:
2470 case CSR_MHPMCOUNTER18H
:
2471 case CSR_MHPMCOUNTER19H
:
2472 case CSR_MHPMCOUNTER20H
:
2473 case CSR_MHPMCOUNTER21H
:
2474 case CSR_MHPMCOUNTER22H
:
2475 case CSR_MHPMCOUNTER23H
:
2476 case CSR_MHPMCOUNTER24H
:
2477 case CSR_MHPMCOUNTER25H
:
2478 case CSR_MHPMCOUNTER26H
:
2479 case CSR_MHPMCOUNTER27H
:
2480 case CSR_MHPMCOUNTER28H
:
2481 case CSR_MHPMCOUNTER29H
:
2482 case CSR_MHPMCOUNTER30H
:
2483 case CSR_MHPMCOUNTER31H
:
2484 r
->exist
= riscv_xlen(target
) == 32;
2488 if (!r
->exist
&& expose_csr
) {
2489 for (unsigned i
= 0; expose_csr
[i
].low
<= expose_csr
[i
].high
; i
++) {
2490 if (csr_number
>= expose_csr
[i
].low
&& csr_number
<= expose_csr
[i
].high
) {
2491 LOG_INFO("Exposing additional CSR %d", csr_number
);
2498 } else if (number
== GDB_REGNO_PRIV
) {
2499 sprintf(reg_name
, "priv");
2500 r
->group
= "general";
2501 r
->feature
= &feature_virtual
;
2506 reg_name
+= strlen(reg_name
) + 1;
2507 assert(reg_name
< info
->reg_names
+ GDB_REGNO_COUNT
* max_reg_name_len
);
2508 r
->value
= &info
->reg_cache_values
[number
];
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