1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include "target/target.h"
12 #include "target/algorithm.h"
13 #include "target/target_type.h"
15 #include "jtag/jtag.h"
16 #include "target/register.h"
17 #include "target/breakpoints.h"
18 #include "helper/time_support.h"
21 #include "rtos/rtos.h"
23 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
24 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
26 /* Constants for legacy SiFive hardware breakpoints. */
27 #define CSR_BPCONTROL_X (1<<0)
28 #define CSR_BPCONTROL_W (1<<1)
29 #define CSR_BPCONTROL_R (1<<2)
30 #define CSR_BPCONTROL_U (1<<3)
31 #define CSR_BPCONTROL_S (1<<4)
32 #define CSR_BPCONTROL_H (1<<5)
33 #define CSR_BPCONTROL_M (1<<6)
34 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
35 #define CSR_BPCONTROL_BPACTION (0xff<<11)
37 #define DEBUG_ROM_START 0x800
38 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
39 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
40 #define DEBUG_RAM_START 0x400
42 #define SETHALTNOT 0x10c
44 /*** JTAG registers. ***/
46 #define DTMCONTROL 0x10
47 #define DTMCONTROL_DBUS_RESET (1<<16)
48 #define DTMCONTROL_IDLE (7<<10)
49 #define DTMCONTROL_ADDRBITS (0xf<<4)
50 #define DTMCONTROL_VERSION (0xf)
53 #define DBUS_OP_START 0
54 #define DBUS_OP_SIZE 2
61 DBUS_STATUS_SUCCESS
= 0,
62 DBUS_STATUS_FAILED
= 2,
65 #define DBUS_DATA_START 2
66 #define DBUS_DATA_SIZE 34
67 #define DBUS_ADDRESS_START 36
75 /*** Debug Bus registers. ***/
77 #define DMCONTROL 0x10
78 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
79 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
80 #define DMCONTROL_BUSERROR (7<<19)
81 #define DMCONTROL_SERIAL (3<<16)
82 #define DMCONTROL_AUTOINCREMENT (1<<15)
83 #define DMCONTROL_ACCESS (7<<12)
84 #define DMCONTROL_HARTID (0x3ff<<2)
85 #define DMCONTROL_NDRESET (1<<1)
86 #define DMCONTROL_FULLRESET 1
89 #define DMINFO_ABUSSIZE (0x7fU<<25)
90 #define DMINFO_SERIALCOUNT (0xf<<21)
91 #define DMINFO_ACCESS128 (1<<20)
92 #define DMINFO_ACCESS64 (1<<19)
93 #define DMINFO_ACCESS32 (1<<18)
94 #define DMINFO_ACCESS16 (1<<17)
95 #define DMINFO_ACCESS8 (1<<16)
96 #define DMINFO_DRAMSIZE (0x3f<<10)
97 #define DMINFO_AUTHENTICATED (1<<5)
98 #define DMINFO_AUTHBUSY (1<<4)
99 #define DMINFO_AUTHTYPE (3<<2)
100 #define DMINFO_VERSION 3
102 /*** Info about the core being debugged. ***/
104 #define DBUS_ADDRESS_UNKNOWN 0xffff
107 #define DRAM_CACHE_SIZE 16
109 uint8_t ir_dtmcontrol
[4] = {DTMCONTROL
};
110 struct scan_field select_dtmcontrol
= {
112 .out_value
= ir_dtmcontrol
114 uint8_t ir_dbus
[4] = {DBUS
};
115 struct scan_field select_dbus
= {
119 uint8_t ir_idcode
[4] = {0x1};
120 struct scan_field select_idcode
= {
122 .out_value
= ir_idcode
125 bscan_tunnel_type_t bscan_tunnel_type
;
126 int bscan_tunnel_ir_width
; /* if zero, then tunneling is not present/active */
128 static uint8_t bscan_zero
[4] = {0};
129 static uint8_t bscan_one
[4] = {1};
131 uint8_t ir_user4
[4] = {0x23};
132 struct scan_field select_user4
= {
134 .out_value
= ir_user4
138 uint8_t bscan_tunneled_ir_width
[4] = {5}; /* overridden by assignment in riscv_init_target */
139 struct scan_field _bscan_tunnel_data_register_select_dmi
[] = {
142 .out_value
= bscan_zero
,
146 .num_bits
= 5, /* initialized in riscv_init_target to ir width of DM */
147 .out_value
= ir_dbus
,
152 .out_value
= bscan_tunneled_ir_width
,
157 .out_value
= bscan_zero
,
162 struct scan_field _bscan_tunnel_nested_tap_select_dmi
[] = {
165 .out_value
= bscan_zero
,
170 .out_value
= bscan_tunneled_ir_width
,
174 .num_bits
= 0, /* initialized in riscv_init_target to ir width of DM */
175 .out_value
= ir_dbus
,
180 .out_value
= bscan_zero
,
184 struct scan_field
*bscan_tunnel_nested_tap_select_dmi
= _bscan_tunnel_nested_tap_select_dmi
;
185 uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi
);
187 struct scan_field
*bscan_tunnel_data_register_select_dmi
= _bscan_tunnel_data_register_select_dmi
;
188 uint32_t bscan_tunnel_data_register_select_dmi_num_fields
= ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi
);
195 bool read
, write
, execute
;
199 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
200 int riscv_command_timeout_sec
= DEFAULT_COMMAND_TIMEOUT_SEC
;
202 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
203 int riscv_reset_timeout_sec
= DEFAULT_RESET_TIMEOUT_SEC
;
205 bool riscv_prefer_sba
;
206 bool riscv_enable_virt2phys
= true;
207 bool riscv_ebreakm
= true;
208 bool riscv_ebreaks
= true;
209 bool riscv_ebreaku
= true;
211 bool riscv_enable_virtual
;
217 /* In addition to the ones in the standard spec, we'll also expose additional
219 * The list is either NULL, or a series of ranges (inclusive), terminated with
222 /* Same, but for custom registers. */
223 range_t
*expose_custom
;
230 virt2phys_info_t sv32
= {
235 .vpn_shift
= {12, 22},
236 .vpn_mask
= {0x3ff, 0x3ff},
237 .pte_ppn_shift
= {10, 20},
238 .pte_ppn_mask
= {0x3ff, 0xfff},
239 .pa_ppn_shift
= {12, 22},
240 .pa_ppn_mask
= {0x3ff, 0xfff},
243 virt2phys_info_t sv39
= {
248 .vpn_shift
= {12, 21, 30},
249 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff},
250 .pte_ppn_shift
= {10, 19, 28},
251 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
252 .pa_ppn_shift
= {12, 21, 30},
253 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x3ffffff},
256 virt2phys_info_t sv48
= {
261 .vpn_shift
= {12, 21, 30, 39},
262 .vpn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ff},
263 .pte_ppn_shift
= {10, 19, 28, 37},
264 .pte_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
265 .pa_ppn_shift
= {12, 21, 30, 39},
266 .pa_ppn_mask
= {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
269 static int riscv_resume_go_all_harts(struct target
*target
);
271 void select_dmi_via_bscan(struct target
*target
)
273 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
274 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
275 jtag_add_dr_scan(target
->tap
, bscan_tunnel_data_register_select_dmi_num_fields
,
276 bscan_tunnel_data_register_select_dmi
, TAP_IDLE
);
277 else /* BSCAN_TUNNEL_NESTED_TAP */
278 jtag_add_dr_scan(target
->tap
, bscan_tunnel_nested_tap_select_dmi_num_fields
,
279 bscan_tunnel_nested_tap_select_dmi
, TAP_IDLE
);
282 uint32_t dtmcontrol_scan_via_bscan(struct target
*target
, uint32_t out
)
284 /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
285 uint8_t tunneled_ir_width
[4] = {bscan_tunnel_ir_width
};
286 uint8_t tunneled_dr_width
[4] = {32};
287 uint8_t out_value
[5] = {0};
288 uint8_t in_value
[5] = {0};
290 buf_set_u32(out_value
, 0, 32, out
);
291 struct scan_field tunneled_ir
[4] = {};
292 struct scan_field tunneled_dr
[4] = {};
294 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
295 tunneled_ir
[0].num_bits
= 3;
296 tunneled_ir
[0].out_value
= bscan_zero
;
297 tunneled_ir
[0].in_value
= NULL
;
298 tunneled_ir
[1].num_bits
= bscan_tunnel_ir_width
;
299 tunneled_ir
[1].out_value
= ir_dtmcontrol
;
300 tunneled_ir
[1].in_value
= NULL
;
301 tunneled_ir
[2].num_bits
= 7;
302 tunneled_ir
[2].out_value
= tunneled_ir_width
;
303 tunneled_ir
[2].in_value
= NULL
;
304 tunneled_ir
[3].num_bits
= 1;
305 tunneled_ir
[3].out_value
= bscan_zero
;
306 tunneled_ir
[3].in_value
= NULL
;
308 tunneled_dr
[0].num_bits
= 3;
309 tunneled_dr
[0].out_value
= bscan_zero
;
310 tunneled_dr
[0].in_value
= NULL
;
311 tunneled_dr
[1].num_bits
= 32 + 1;
312 tunneled_dr
[1].out_value
= out_value
;
313 tunneled_dr
[1].in_value
= in_value
;
314 tunneled_dr
[2].num_bits
= 7;
315 tunneled_dr
[2].out_value
= tunneled_dr_width
;
316 tunneled_dr
[2].in_value
= NULL
;
317 tunneled_dr
[3].num_bits
= 1;
318 tunneled_dr
[3].out_value
= bscan_one
;
319 tunneled_dr
[3].in_value
= NULL
;
321 /* BSCAN_TUNNEL_NESTED_TAP */
322 tunneled_ir
[3].num_bits
= 3;
323 tunneled_ir
[3].out_value
= bscan_zero
;
324 tunneled_ir
[3].in_value
= NULL
;
325 tunneled_ir
[2].num_bits
= bscan_tunnel_ir_width
;
326 tunneled_ir
[2].out_value
= ir_dtmcontrol
;
327 tunneled_ir
[1].in_value
= NULL
;
328 tunneled_ir
[1].num_bits
= 7;
329 tunneled_ir
[1].out_value
= tunneled_ir_width
;
330 tunneled_ir
[2].in_value
= NULL
;
331 tunneled_ir
[0].num_bits
= 1;
332 tunneled_ir
[0].out_value
= bscan_zero
;
333 tunneled_ir
[0].in_value
= NULL
;
335 tunneled_dr
[3].num_bits
= 3;
336 tunneled_dr
[3].out_value
= bscan_zero
;
337 tunneled_dr
[3].in_value
= NULL
;
338 tunneled_dr
[2].num_bits
= 32 + 1;
339 tunneled_dr
[2].out_value
= out_value
;
340 tunneled_dr
[2].in_value
= in_value
;
341 tunneled_dr
[1].num_bits
= 7;
342 tunneled_dr
[1].out_value
= tunneled_dr_width
;
343 tunneled_dr
[1].in_value
= NULL
;
344 tunneled_dr
[0].num_bits
= 1;
345 tunneled_dr
[0].out_value
= bscan_one
;
346 tunneled_dr
[0].in_value
= NULL
;
348 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
349 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_ir
), tunneled_ir
, TAP_IDLE
);
350 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(tunneled_dr
), tunneled_dr
, TAP_IDLE
);
351 select_dmi_via_bscan(target
);
353 int retval
= jtag_execute_queue();
354 if (retval
!= ERROR_OK
) {
355 LOG_ERROR("failed jtag scan: %d", retval
);
358 /* Note the starting offset is bit 1, not bit 0. In BSCAN tunnel, there is a one-bit TCK skew between
360 uint32_t in
= buf_get_u32(in_value
, 1, 32);
361 LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out
, in
);
368 static uint32_t dtmcontrol_scan(struct target
*target
, uint32_t out
)
370 struct scan_field field
;
372 uint8_t out_value
[4] = { 0 };
374 if (bscan_tunnel_ir_width
!= 0)
375 return dtmcontrol_scan_via_bscan(target
, out
);
378 buf_set_u32(out_value
, 0, 32, out
);
380 jtag_add_ir_scan(target
->tap
, &select_dtmcontrol
, TAP_IDLE
);
383 field
.out_value
= out_value
;
384 field
.in_value
= in_value
;
385 jtag_add_dr_scan(target
->tap
, 1, &field
, TAP_IDLE
);
387 /* Always return to dbus. */
388 jtag_add_ir_scan(target
->tap
, &select_dbus
, TAP_IDLE
);
390 int retval
= jtag_execute_queue();
391 if (retval
!= ERROR_OK
) {
392 LOG_ERROR("failed jtag scan: %d", retval
);
396 uint32_t in
= buf_get_u32(field
.in_value
, 0, 32);
397 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out
, in
);
402 static struct target_type
*get_target_type(struct target
*target
)
404 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
407 LOG_ERROR("Target has not been initialized");
411 switch (info
->dtm_version
) {
413 return &riscv011_target
;
415 return &riscv013_target
;
417 LOG_ERROR("Unsupported DTM version: %d", info
->dtm_version
);
422 static int riscv_init_target(struct command_context
*cmd_ctx
,
423 struct target
*target
)
425 LOG_DEBUG("riscv_init_target()");
426 target
->arch_info
= calloc(1, sizeof(riscv_info_t
));
427 if (!target
->arch_info
)
429 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
430 riscv_info_init(target
, info
);
431 info
->cmd_ctx
= cmd_ctx
;
433 select_dtmcontrol
.num_bits
= target
->tap
->ir_length
;
434 select_dbus
.num_bits
= target
->tap
->ir_length
;
435 select_idcode
.num_bits
= target
->tap
->ir_length
;
437 if (bscan_tunnel_ir_width
!= 0) {
438 select_user4
.num_bits
= target
->tap
->ir_length
;
439 bscan_tunneled_ir_width
[0] = bscan_tunnel_ir_width
;
440 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
441 bscan_tunnel_data_register_select_dmi
[1].num_bits
= bscan_tunnel_ir_width
;
442 else /* BSCAN_TUNNEL_NESTED_TAP */
443 bscan_tunnel_nested_tap_select_dmi
[2].num_bits
= bscan_tunnel_ir_width
;
446 riscv_semihosting_init(target
);
448 target
->debug_reason
= DBG_REASON_DBGRQ
;
453 static void riscv_free_registers(struct target
*target
)
455 /* Free the shared structure use for most registers. */
456 if (target
->reg_cache
) {
457 if (target
->reg_cache
->reg_list
) {
458 free(target
->reg_cache
->reg_list
[0].arch_info
);
459 /* Free the ones we allocated separately. */
460 for (unsigned i
= GDB_REGNO_COUNT
; i
< target
->reg_cache
->num_regs
; i
++)
461 free(target
->reg_cache
->reg_list
[i
].arch_info
);
462 free(target
->reg_cache
->reg_list
);
464 free(target
->reg_cache
);
468 static void riscv_deinit_target(struct target
*target
)
470 LOG_DEBUG("riscv_deinit_target()");
471 struct target_type
*tt
= get_target_type(target
);
473 tt
->deinit_target(target
);
474 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
475 free(info
->reg_names
);
479 riscv_free_registers(target
);
481 target
->arch_info
= NULL
;
484 static void trigger_from_breakpoint(struct trigger
*trigger
,
485 const struct breakpoint
*breakpoint
)
487 trigger
->address
= breakpoint
->address
;
488 trigger
->length
= breakpoint
->length
;
489 trigger
->mask
= ~0LL;
490 trigger
->read
= false;
491 trigger
->write
= false;
492 trigger
->execute
= true;
493 /* unique_id is unique across both breakpoints and watchpoints. */
494 trigger
->unique_id
= breakpoint
->unique_id
;
497 static int maybe_add_trigger_t1(struct target
*target
, unsigned hartid
,
498 struct trigger
*trigger
, uint64_t tdata1
)
502 const uint32_t bpcontrol_x
= 1<<0;
503 const uint32_t bpcontrol_w
= 1<<1;
504 const uint32_t bpcontrol_r
= 1<<2;
505 const uint32_t bpcontrol_u
= 1<<3;
506 const uint32_t bpcontrol_s
= 1<<4;
507 const uint32_t bpcontrol_h
= 1<<5;
508 const uint32_t bpcontrol_m
= 1<<6;
509 const uint32_t bpcontrol_bpmatch
= 0xf << 7;
510 const uint32_t bpcontrol_bpaction
= 0xff << 11;
512 if (tdata1
& (bpcontrol_r
| bpcontrol_w
| bpcontrol_x
)) {
513 /* Trigger is already in use, presumably by user code. */
514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
517 tdata1
= set_field(tdata1
, bpcontrol_r
, trigger
->read
);
518 tdata1
= set_field(tdata1
, bpcontrol_w
, trigger
->write
);
519 tdata1
= set_field(tdata1
, bpcontrol_x
, trigger
->execute
);
520 tdata1
= set_field(tdata1
, bpcontrol_u
,
521 !!(r
->misa
[hartid
] & (1 << ('U' - 'A'))));
522 tdata1
= set_field(tdata1
, bpcontrol_s
,
523 !!(r
->misa
[hartid
] & (1 << ('S' - 'A'))));
524 tdata1
= set_field(tdata1
, bpcontrol_h
,
525 !!(r
->misa
[hartid
] & (1 << ('H' - 'A'))));
526 tdata1
|= bpcontrol_m
;
527 tdata1
= set_field(tdata1
, bpcontrol_bpmatch
, 0); /* exact match */
528 tdata1
= set_field(tdata1
, bpcontrol_bpaction
, 0); /* cause bp exception */
530 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
532 riscv_reg_t tdata1_rb
;
533 if (riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
,
534 GDB_REGNO_TDATA1
) != ERROR_OK
)
536 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
538 if (tdata1
!= tdata1_rb
) {
539 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
540 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
542 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
543 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
546 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
551 static int maybe_add_trigger_t2(struct target
*target
, unsigned hartid
,
552 struct trigger
*trigger
, uint64_t tdata1
)
556 /* tselect is already set */
557 if (tdata1
& (MCONTROL_EXECUTE
| MCONTROL_STORE
| MCONTROL_LOAD
)) {
558 /* Trigger is already in use, presumably by user code. */
559 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
562 /* address/data match trigger */
563 tdata1
|= MCONTROL_DMODE(riscv_xlen(target
));
564 tdata1
= set_field(tdata1
, MCONTROL_ACTION
,
565 MCONTROL_ACTION_DEBUG_MODE
);
566 tdata1
= set_field(tdata1
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
567 tdata1
|= MCONTROL_M
;
568 if (r
->misa
[hartid
] & (1 << ('H' - 'A')))
569 tdata1
|= MCONTROL_H
;
570 if (r
->misa
[hartid
] & (1 << ('S' - 'A')))
571 tdata1
|= MCONTROL_S
;
572 if (r
->misa
[hartid
] & (1 << ('U' - 'A')))
573 tdata1
|= MCONTROL_U
;
575 if (trigger
->execute
)
576 tdata1
|= MCONTROL_EXECUTE
;
578 tdata1
|= MCONTROL_LOAD
;
580 tdata1
|= MCONTROL_STORE
;
582 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, tdata1
);
585 int result
= riscv_get_register_on_hart(target
, &tdata1_rb
, hartid
, GDB_REGNO_TDATA1
);
586 if (result
!= ERROR_OK
)
588 LOG_DEBUG("tdata1=0x%" PRIx64
, tdata1_rb
);
590 if (tdata1
!= tdata1_rb
) {
591 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
592 PRIx64
" to tdata1 it contains 0x%" PRIx64
,
594 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
595 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
598 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA2
, trigger
->address
);
603 static int add_trigger(struct target
*target
, struct trigger
*trigger
)
607 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
610 /* In RTOS mode, we need to set the same trigger in the same slot on every
611 * hart, to keep up the illusion that each hart is a thread running on the
614 /* Otherwise, we just set the trigger on the one hart this target deals
617 riscv_reg_t tselect
[RISCV_MAX_HARTS
];
620 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
621 if (!riscv_hart_enabled(target
, hartid
))
625 int result
= riscv_get_register_on_hart(target
, &tselect
[hartid
],
626 hartid
, GDB_REGNO_TSELECT
);
627 if (result
!= ERROR_OK
)
630 assert(first_hart
>= 0);
633 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
634 if (r
->trigger_unique_id
[i
] != -1)
637 riscv_set_register_on_hart(target
, first_hart
, GDB_REGNO_TSELECT
, i
);
640 int result
= riscv_get_register_on_hart(target
, &tdata1
, first_hart
,
642 if (result
!= ERROR_OK
)
644 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
647 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
648 if (!riscv_hart_enabled(target
, hartid
))
650 if (hartid
> first_hart
)
651 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
654 result
= maybe_add_trigger_t1(target
, hartid
, trigger
, tdata1
);
657 result
= maybe_add_trigger_t2(target
, hartid
, trigger
, tdata1
);
660 LOG_DEBUG("trigger %d has unknown type %d", i
, type
);
664 if (result
!= ERROR_OK
)
668 if (result
!= ERROR_OK
)
671 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target
->coreid
,
672 i
, type
, trigger
->unique_id
);
673 r
->trigger_unique_id
[i
] = trigger
->unique_id
;
677 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
678 if (!riscv_hart_enabled(target
, hartid
))
680 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
,
684 if (i
>= r
->trigger_count
[first_hart
]) {
685 LOG_ERROR("Couldn't find an available hardware trigger.");
686 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
692 int riscv_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
694 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, breakpoint
->address
);
696 if (breakpoint
->type
== BKPT_SOFT
) {
697 /** @todo check RVC for size/alignment */
698 if (!(breakpoint
->length
== 4 || breakpoint
->length
== 2)) {
699 LOG_ERROR("Invalid breakpoint length %d", breakpoint
->length
);
703 if (0 != (breakpoint
->address
% 2)) {
704 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR
, breakpoint
->address
);
708 if (target_read_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
709 breakpoint
->orig_instr
) != ERROR_OK
) {
710 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR
,
711 breakpoint
->address
);
715 uint8_t buff
[4] = { 0 };
716 buf_set_u32(buff
, 0, breakpoint
->length
* CHAR_BIT
, breakpoint
->length
== 4 ? ebreak() : ebreak_c());
717 int const retval
= target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2, buff
);
719 if (retval
!= ERROR_OK
) {
720 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
721 TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
725 } else if (breakpoint
->type
== BKPT_HARD
) {
726 struct trigger trigger
;
727 trigger_from_breakpoint(&trigger
, breakpoint
);
728 int const result
= add_trigger(target
, &trigger
);
729 if (result
!= ERROR_OK
)
732 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
733 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
736 breakpoint
->set
= true;
740 static int remove_trigger(struct target
*target
, struct trigger
*trigger
)
744 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
748 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
749 if (!riscv_hart_enabled(target
, hartid
))
751 if (first_hart
< 0) {
756 assert(first_hart
>= 0);
759 for (i
= 0; i
< r
->trigger_count
[first_hart
]; i
++) {
760 if (r
->trigger_unique_id
[i
] == trigger
->unique_id
)
763 if (i
>= r
->trigger_count
[first_hart
]) {
764 LOG_ERROR("Couldn't find the hardware resources used by hardware "
768 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target
->coreid
, i
,
770 for (int hartid
= first_hart
; hartid
< riscv_count_harts(target
); ++hartid
) {
771 if (!riscv_hart_enabled(target
, hartid
))
774 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
, GDB_REGNO_TSELECT
);
775 if (result
!= ERROR_OK
)
777 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, i
);
778 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
779 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
781 r
->trigger_unique_id
[i
] = -1;
786 int riscv_remove_breakpoint(struct target
*target
,
787 struct breakpoint
*breakpoint
)
789 if (breakpoint
->type
== BKPT_SOFT
) {
790 if (target_write_memory(target
, breakpoint
->address
, 2, breakpoint
->length
/ 2,
791 breakpoint
->orig_instr
) != ERROR_OK
) {
792 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
793 "0x%" TARGET_PRIxADDR
, breakpoint
->length
, breakpoint
->address
);
797 } else if (breakpoint
->type
== BKPT_HARD
) {
798 struct trigger trigger
;
799 trigger_from_breakpoint(&trigger
, breakpoint
);
800 int result
= remove_trigger(target
, &trigger
);
801 if (result
!= ERROR_OK
)
805 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
806 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
809 breakpoint
->set
= false;
814 static void trigger_from_watchpoint(struct trigger
*trigger
,
815 const struct watchpoint
*watchpoint
)
817 trigger
->address
= watchpoint
->address
;
818 trigger
->length
= watchpoint
->length
;
819 trigger
->mask
= watchpoint
->mask
;
820 trigger
->value
= watchpoint
->value
;
821 trigger
->read
= (watchpoint
->rw
== WPT_READ
|| watchpoint
->rw
== WPT_ACCESS
);
822 trigger
->write
= (watchpoint
->rw
== WPT_WRITE
|| watchpoint
->rw
== WPT_ACCESS
);
823 trigger
->execute
= false;
824 /* unique_id is unique across both breakpoints and watchpoints. */
825 trigger
->unique_id
= watchpoint
->unique_id
;
828 int riscv_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
830 struct trigger trigger
;
831 trigger_from_watchpoint(&trigger
, watchpoint
);
833 int result
= add_trigger(target
, &trigger
);
834 if (result
!= ERROR_OK
)
836 watchpoint
->set
= true;
841 int riscv_remove_watchpoint(struct target
*target
,
842 struct watchpoint
*watchpoint
)
844 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR
, target
->coreid
, watchpoint
->address
);
846 struct trigger trigger
;
847 trigger_from_watchpoint(&trigger
, watchpoint
);
849 int result
= remove_trigger(target
, &trigger
);
850 if (result
!= ERROR_OK
)
852 watchpoint
->set
= false;
857 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
860 * The GDB server uses this information to tell GDB what data address has
861 * been hit, which enables GDB to print the hit variable along with its old
863 int riscv_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
865 struct watchpoint
*wp
= target
->watchpoints
;
867 if (riscv_rtos_enabled(target
))
868 riscv_set_current_hartid(target
, target
->rtos
->current_thread
- 1);
869 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target
));
871 /*TODO instead of disassembling the instruction that we think caused the
872 * trigger, check the hit bit of each watchpoint first. The hit bit is
873 * simpler and more reliable to check but as it is optional and relatively
874 * new, not all hardware will implement it */
876 riscv_get_register(target
, &dpc
, GDB_REGNO_DPC
);
877 const uint8_t length
= 4;
878 LOG_DEBUG("dpc is 0x%" PRIx64
, dpc
);
880 /* fetch the instruction at dpc */
881 uint8_t buffer
[length
];
882 if (target_read_buffer(target
, dpc
, length
, buffer
) != ERROR_OK
) {
883 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64
, dpc
);
887 uint32_t instruction
= 0;
889 for (int i
= 0; i
< length
; i
++) {
890 LOG_DEBUG("Next byte is %x", buffer
[i
]);
891 instruction
+= (buffer
[i
] << 8 * i
);
893 LOG_DEBUG("Full instruction is %x", instruction
);
895 /* find out which memory address is accessed by the instruction at dpc */
896 /* opcode is first 7 bits of the instruction */
897 uint8_t opcode
= instruction
& 0x7F;
900 riscv_reg_t mem_addr
;
902 if (opcode
== MATCH_LB
|| opcode
== MATCH_SB
) {
903 rs1
= (instruction
& 0xf8000) >> 15;
904 riscv_get_register(target
, &mem_addr
, rs1
);
906 if (opcode
== MATCH_SB
) {
907 LOG_DEBUG("%x is store instruction", instruction
);
908 imm
= ((instruction
& 0xf80) >> 7) | ((instruction
& 0xfe000000) >> 20);
910 LOG_DEBUG("%x is load instruction", instruction
);
911 imm
= (instruction
& 0xfff00000) >> 20;
913 /* sign extend 12-bit imm to 16-bits */
917 LOG_DEBUG("memory address=0x%" PRIx64
, mem_addr
);
919 LOG_DEBUG("%x is not a RV32I load or store", instruction
);
924 /*TODO support length/mask */
925 if (wp
->address
== mem_addr
) {
926 *hit_watchpoint
= wp
;
927 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR
, wp
->address
);
933 /* No match found - either we hit a watchpoint caused by an instruction that
934 * this function does not yet disassemble, or we hit a breakpoint.
936 * OpenOCD will behave as if this function had never been implemented i.e.
937 * report the halt to GDB with no address information. */
942 static int oldriscv_step(struct target
*target
, int current
, uint32_t address
,
943 int handle_breakpoints
)
945 struct target_type
*tt
= get_target_type(target
);
946 return tt
->step(target
, current
, address
, handle_breakpoints
);
949 static int old_or_new_riscv_step(struct target
*target
, int current
,
950 target_addr_t address
, int handle_breakpoints
)
953 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
954 if (r
->is_halted
== NULL
)
955 return oldriscv_step(target
, current
, address
, handle_breakpoints
);
957 return riscv_openocd_step(target
, current
, address
, handle_breakpoints
);
961 static int riscv_examine(struct target
*target
)
963 LOG_DEBUG("riscv_examine()");
964 if (target_was_examined(target
)) {
965 LOG_DEBUG("Target was already examined.");
969 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
971 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
972 uint32_t dtmcontrol
= dtmcontrol_scan(target
, 0);
973 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol
);
974 info
->dtm_version
= get_field(dtmcontrol
, DTMCONTROL_VERSION
);
975 LOG_DEBUG(" version=0x%x", info
->dtm_version
);
977 struct target_type
*tt
= get_target_type(target
);
981 int result
= tt
->init_target(info
->cmd_ctx
, target
);
982 if (result
!= ERROR_OK
)
985 return tt
->examine(target
);
988 static int oldriscv_poll(struct target
*target
)
990 struct target_type
*tt
= get_target_type(target
);
991 return tt
->poll(target
);
994 static int old_or_new_riscv_poll(struct target
*target
)
997 if (r
->is_halted
== NULL
)
998 return oldriscv_poll(target
);
1000 return riscv_openocd_poll(target
);
1003 int halt_prep(struct target
*target
)
1006 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1007 if (!riscv_hart_enabled(target
, i
))
1010 LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target
),
1011 target
->debug_reason
);
1012 if (riscv_set_current_hartid(target
, i
) != ERROR_OK
)
1014 if (riscv_is_halted(target
)) {
1015 LOG_DEBUG("Hart %d is already halted (reason=%d).", i
,
1016 target
->debug_reason
);
1018 if (r
->halt_prep(target
) != ERROR_OK
)
1026 int riscv_halt_go_all_harts(struct target
*target
)
1029 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1030 if (!riscv_hart_enabled(target
, i
))
1033 if (riscv_set_current_hartid(target
, i
) != ERROR_OK
)
1035 if (riscv_is_halted(target
)) {
1036 LOG_DEBUG("Hart %d is already halted.", i
);
1038 if (r
->halt_go(target
) != ERROR_OK
)
1043 riscv_invalidate_register_cache(target
);
1048 int halt_go(struct target
*target
)
1050 riscv_info_t
*r
= riscv_info(target
);
1052 if (r
->is_halted
== NULL
) {
1053 struct target_type
*tt
= get_target_type(target
);
1054 result
= tt
->halt(target
);
1056 result
= riscv_halt_go_all_harts(target
);
1058 target
->state
= TARGET_HALTED
;
1059 if (target
->debug_reason
== DBG_REASON_NOTHALTED
)
1060 target
->debug_reason
= DBG_REASON_DBGRQ
;
1065 static int halt_finish(struct target
*target
)
1067 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1070 int riscv_halt(struct target
*target
)
1074 if (r
->is_halted
== NULL
) {
1075 struct target_type
*tt
= get_target_type(target
);
1076 return tt
->halt(target
);
1079 LOG_DEBUG("[%d] halting all harts", target
->coreid
);
1081 int result
= ERROR_OK
;
1083 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1084 struct target
*t
= tlist
->target
;
1085 if (halt_prep(t
) != ERROR_OK
)
1086 result
= ERROR_FAIL
;
1089 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1090 struct target
*t
= tlist
->target
;
1091 riscv_info_t
*i
= riscv_info(t
);
1093 if (halt_go(t
) != ERROR_OK
)
1094 result
= ERROR_FAIL
;
1098 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1099 struct target
*t
= tlist
->target
;
1100 if (halt_finish(t
) != ERROR_OK
)
1105 if (halt_prep(target
) != ERROR_OK
)
1106 result
= ERROR_FAIL
;
1107 if (halt_go(target
) != ERROR_OK
)
1108 result
= ERROR_FAIL
;
1109 if (halt_finish(target
) != ERROR_OK
)
1113 if (riscv_rtos_enabled(target
)) {
1114 if (r
->rtos_hartid
!= -1) {
1115 LOG_DEBUG("halt requested on RTOS hartid %d", r
->rtos_hartid
);
1116 target
->rtos
->current_threadid
= r
->rtos_hartid
+ 1;
1117 target
->rtos
->current_thread
= r
->rtos_hartid
+ 1;
1119 LOG_DEBUG("halt requested, but no known RTOS hartid");
1125 static int riscv_assert_reset(struct target
*target
)
1127 LOG_DEBUG("[%d]", target
->coreid
);
1128 struct target_type
*tt
= get_target_type(target
);
1129 riscv_invalidate_register_cache(target
);
1130 return tt
->assert_reset(target
);
1133 static int riscv_deassert_reset(struct target
*target
)
1135 LOG_DEBUG("[%d]", target
->coreid
);
1136 struct target_type
*tt
= get_target_type(target
);
1137 return tt
->deassert_reset(target
);
1140 int riscv_resume_prep_all_harts(struct target
*target
)
1143 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
1144 if (!riscv_hart_enabled(target
, i
))
1147 LOG_DEBUG("prep hart %d", i
);
1148 if (riscv_set_current_hartid(target
, i
) != ERROR_OK
)
1150 if (riscv_is_halted(target
)) {
1151 if (r
->resume_prep(target
) != ERROR_OK
)
1154 LOG_DEBUG(" hart %d requested resume, but was already resumed", i
);
1158 LOG_DEBUG("[%d] mark as prepped", target
->coreid
);
1164 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1165 static int disable_triggers(struct target
*target
, riscv_reg_t
*state
)
1169 LOG_DEBUG("deal with triggers");
1171 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
1174 int hartid
= riscv_current_hartid(target
);
1175 if (r
->manual_hwbp_set
) {
1176 /* Look at every trigger that may have been set. */
1177 riscv_reg_t tselect
;
1178 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1180 for (unsigned t
= 0; t
< r
->trigger_count
[hartid
]; t
++) {
1181 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1184 if (riscv_get_register(target
, &tdata1
, GDB_REGNO_TDATA1
) != ERROR_OK
)
1186 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
))) {
1188 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, 0) != ERROR_OK
)
1192 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1196 /* Just go through the triggers we manage. */
1197 struct watchpoint
*watchpoint
= target
->watchpoints
;
1199 while (watchpoint
) {
1200 LOG_DEBUG("watchpoint %d: set=%d", i
, watchpoint
->set
);
1201 state
[i
] = watchpoint
->set
;
1202 if (watchpoint
->set
) {
1203 if (riscv_remove_watchpoint(target
, watchpoint
) != ERROR_OK
)
1206 watchpoint
= watchpoint
->next
;
1214 static int enable_triggers(struct target
*target
, riscv_reg_t
*state
)
1218 int hartid
= riscv_current_hartid(target
);
1220 if (r
->manual_hwbp_set
) {
1221 /* Look at every trigger that may have been set. */
1222 riscv_reg_t tselect
;
1223 if (riscv_get_register(target
, &tselect
, GDB_REGNO_TSELECT
) != ERROR_OK
)
1225 for (unsigned t
= 0; t
< r
->trigger_count
[hartid
]; t
++) {
1226 if (state
[t
] != 0) {
1227 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
1229 if (riscv_set_register(target
, GDB_REGNO_TDATA1
, state
[t
]) != ERROR_OK
)
1233 if (riscv_set_register(target
, GDB_REGNO_TSELECT
, tselect
) != ERROR_OK
)
1237 struct watchpoint
*watchpoint
= target
->watchpoints
;
1239 while (watchpoint
) {
1240 LOG_DEBUG("watchpoint %d: cleared=%" PRId64
, i
, state
[i
]);
1242 if (riscv_add_watchpoint(target
, watchpoint
) != ERROR_OK
)
1245 watchpoint
= watchpoint
->next
;
1254 * Get everything ready to resume.
1256 static int resume_prep(struct target
*target
, int current
,
1257 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1260 LOG_DEBUG("[%d]", target
->coreid
);
1263 riscv_set_register(target
, GDB_REGNO_PC
, address
);
1265 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1266 /* To be able to run off a trigger, disable all the triggers, step, and
1267 * then resume as usual. */
1268 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
1270 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
1273 if (old_or_new_riscv_step(target
, true, 0, false) != ERROR_OK
)
1276 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
1281 if (riscv_resume_prep_all_harts(target
) != ERROR_OK
)
1285 LOG_DEBUG("[%d] mark as prepped", target
->coreid
);
1292 * Resume all the harts that have been prepped, as close to instantaneous as
1295 static int resume_go(struct target
*target
, int current
,
1296 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1298 riscv_info_t
*r
= riscv_info(target
);
1300 if (r
->is_halted
== NULL
) {
1301 struct target_type
*tt
= get_target_type(target
);
1302 result
= tt
->resume(target
, current
, address
, handle_breakpoints
,
1305 result
= riscv_resume_go_all_harts(target
);
1311 static int resume_finish(struct target
*target
)
1313 register_cache_invalidate(target
->reg_cache
);
1315 target
->state
= TARGET_RUNNING
;
1316 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1317 return target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1321 * @par single_hart When true, only resume a single hart even if SMP is
1322 * configured. This is used to run algorithms on just one hart.
1325 struct target
*target
,
1327 target_addr_t address
,
1328 int handle_breakpoints
,
1329 int debug_execution
,
1332 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints
);
1333 int result
= ERROR_OK
;
1334 if (target
->smp
&& !single_hart
) {
1335 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1336 struct target
*t
= tlist
->target
;
1337 if (resume_prep(t
, current
, address
, handle_breakpoints
,
1338 debug_execution
) != ERROR_OK
)
1339 result
= ERROR_FAIL
;
1342 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1343 struct target
*t
= tlist
->target
;
1344 riscv_info_t
*i
= riscv_info(t
);
1346 if (resume_go(t
, current
, address
, handle_breakpoints
,
1347 debug_execution
) != ERROR_OK
)
1348 result
= ERROR_FAIL
;
1352 for (struct target_list
*tlist
= target
->head
; tlist
; tlist
= tlist
->next
) {
1353 struct target
*t
= tlist
->target
;
1354 if (resume_finish(t
) != ERROR_OK
)
1359 if (resume_prep(target
, current
, address
, handle_breakpoints
,
1360 debug_execution
) != ERROR_OK
)
1361 result
= ERROR_FAIL
;
1362 if (resume_go(target
, current
, address
, handle_breakpoints
,
1363 debug_execution
) != ERROR_OK
)
1364 result
= ERROR_FAIL
;
1365 if (resume_finish(target
) != ERROR_OK
)
1372 static int riscv_target_resume(struct target
*target
, int current
, target_addr_t address
,
1373 int handle_breakpoints
, int debug_execution
)
1375 return riscv_resume(target
, current
, address
, handle_breakpoints
,
1376 debug_execution
, false);
1379 static int riscv_select_current_hart(struct target
*target
)
1382 if (riscv_rtos_enabled(target
)) {
1383 if (r
->rtos_hartid
== -1)
1384 r
->rtos_hartid
= target
->rtos
->current_threadid
- 1;
1385 return riscv_set_current_hartid(target
, r
->rtos_hartid
);
1387 return riscv_set_current_hartid(target
, target
->coreid
);
1390 static int riscv_mmu(struct target
*target
, int *enabled
)
1392 if (!riscv_enable_virt2phys
) {
1397 if (riscv_rtos_enabled(target
))
1398 riscv_set_current_hartid(target
, target
->rtos
->current_thread
- 1);
1400 /* Don't use MMU in explicit or effective M (machine) mode */
1402 if (riscv_get_register(target
, &priv
, GDB_REGNO_PRIV
) != ERROR_OK
) {
1403 LOG_ERROR("Failed to read priv register.");
1407 riscv_reg_t mstatus
;
1408 if (riscv_get_register(target
, &mstatus
, GDB_REGNO_MSTATUS
) != ERROR_OK
) {
1409 LOG_ERROR("Failed to read mstatus register.");
1413 if ((get_field(mstatus
, MSTATUS_MPRV
) ? get_field(mstatus
, MSTATUS_MPP
) : priv
) == PRV_M
) {
1414 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64
").", mstatus
);
1420 if (riscv_get_register(target
, &satp
, GDB_REGNO_SATP
) != ERROR_OK
) {
1421 LOG_DEBUG("Couldn't read SATP.");
1422 /* If we can't read SATP, then there must not be an MMU. */
1427 if (get_field(satp
, RISCV_SATP_MODE(riscv_xlen(target
))) == SATP_MODE_OFF
) {
1428 LOG_DEBUG("MMU is disabled.");
1431 LOG_DEBUG("MMU is enabled.");
1438 static int riscv_address_translate(struct target
*target
,
1439 target_addr_t
virtual, target_addr_t
*physical
)
1442 riscv_reg_t satp_value
;
1445 target_addr_t table_address
;
1446 virt2phys_info_t
*info
;
1450 if (riscv_rtos_enabled(target
))
1451 riscv_set_current_hartid(target
, target
->rtos
->current_thread
- 1);
1453 int result
= riscv_get_register(target
, &satp_value
, GDB_REGNO_SATP
);
1454 if (result
!= ERROR_OK
)
1457 unsigned xlen
= riscv_xlen(target
);
1458 mode
= get_field(satp_value
, RISCV_SATP_MODE(xlen
));
1460 case SATP_MODE_SV32
:
1463 case SATP_MODE_SV39
:
1466 case SATP_MODE_SV48
:
1470 LOG_ERROR("No translation or protection." \
1471 " (satp: 0x%" PRIx64
")", satp_value
);
1474 LOG_ERROR("The translation mode is not supported." \
1475 " (satp: 0x%" PRIx64
")", satp_value
);
1478 LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR
"; mode=%s", virtual, info
->name
);
1480 /* verify bits xlen-1:va_bits-1 are all equal */
1481 target_addr_t mask
= ((target_addr_t
)1 << (xlen
- (info
->va_bits
- 1))) - 1;
1482 target_addr_t masked_msbs
= (virtual >> (info
->va_bits
- 1)) & mask
;
1483 if (masked_msbs
!= 0 && masked_msbs
!= mask
) {
1484 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR
" is not sign-extended "
1485 "for %s mode.", virtual, info
->name
);
1489 ppn_value
= get_field(satp_value
, RISCV_SATP_PPN(xlen
));
1490 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1491 i
= info
->level
- 1;
1493 uint64_t vpn
= virtual >> info
->vpn_shift
[i
];
1494 vpn
&= info
->vpn_mask
[i
];
1495 target_addr_t pte_address
= table_address
+
1496 (vpn
<< info
->pte_shift
);
1498 assert(info
->pte_shift
<= 3);
1499 int retval
= r
->read_memory(target
, pte_address
,
1500 4, (1 << info
->pte_shift
) / 4, buffer
, 4);
1501 if (retval
!= ERROR_OK
)
1504 if (info
->pte_shift
== 2)
1505 pte
= buf_get_u32(buffer
, 0, 32);
1507 pte
= buf_get_u64(buffer
, 0, 64);
1509 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR
" = 0x%" PRIx64
, i
,
1512 if (!(pte
& PTE_V
) || (!(pte
& PTE_R
) && (pte
& PTE_W
)))
1515 if ((pte
& PTE_R
) || (pte
& PTE_X
)) /* Found leaf PTE. */
1521 ppn_value
= pte
>> PTE_PPN_SHIFT
;
1522 table_address
= ppn_value
<< RISCV_PGSHIFT
;
1526 LOG_ERROR("Couldn't find the PTE.");
1530 /* Make sure to clear out the high bits that may be set. */
1531 *physical
= virtual & (((target_addr_t
)1 << info
->va_bits
) - 1);
1533 while (i
< info
->level
) {
1534 ppn_value
= pte
>> info
->pte_ppn_shift
[i
];
1535 ppn_value
&= info
->pte_ppn_mask
[i
];
1536 *physical
&= ~(((target_addr_t
)info
->pa_ppn_mask
[i
]) <<
1537 info
->pa_ppn_shift
[i
]);
1538 *physical
|= (ppn_value
<< info
->pa_ppn_shift
[i
]);
1541 LOG_DEBUG("0x%" TARGET_PRIxADDR
" -> 0x%" TARGET_PRIxADDR
, virtual,
1547 static int riscv_virt2phys(struct target
*target
, target_addr_t
virtual, target_addr_t
*physical
)
1550 if (riscv_mmu(target
, &enabled
) == ERROR_OK
) {
1554 if (riscv_address_translate(target
, virtual, physical
) == ERROR_OK
)
1561 static int riscv_read_phys_memory(struct target
*target
, target_addr_t phys_address
,
1562 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1565 if (riscv_select_current_hart(target
) != ERROR_OK
)
1567 return r
->read_memory(target
, phys_address
, size
, count
, buffer
, size
);
1570 static int riscv_read_memory(struct target
*target
, target_addr_t address
,
1571 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1574 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR
, address
);
1578 if (riscv_select_current_hart(target
) != ERROR_OK
)
1581 target_addr_t physical_addr
;
1582 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1583 address
= physical_addr
;
1586 return r
->read_memory(target
, address
, size
, count
, buffer
, size
);
1589 static int riscv_write_phys_memory(struct target
*target
, target_addr_t phys_address
,
1590 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1592 if (riscv_select_current_hart(target
) != ERROR_OK
)
1594 struct target_type
*tt
= get_target_type(target
);
1595 return tt
->write_memory(target
, phys_address
, size
, count
, buffer
);
1598 static int riscv_write_memory(struct target
*target
, target_addr_t address
,
1599 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1602 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR
, address
);
1606 if (riscv_select_current_hart(target
) != ERROR_OK
)
1609 target_addr_t physical_addr
;
1610 if (target
->type
->virt2phys(target
, address
, &physical_addr
) == ERROR_OK
)
1611 address
= physical_addr
;
1613 struct target_type
*tt
= get_target_type(target
);
1614 return tt
->write_memory(target
, address
, size
, count
, buffer
);
1617 static int riscv_get_gdb_reg_list_internal(struct target
*target
,
1618 struct reg
**reg_list
[], int *reg_list_size
,
1619 enum target_register_class reg_class
, bool read
)
1622 LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
1623 r
->rtos_hartid
, r
->current_hartid
, reg_class
, read
);
1625 if (!target
->reg_cache
) {
1626 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1630 if (riscv_select_current_hart(target
) != ERROR_OK
)
1633 switch (reg_class
) {
1634 case REG_CLASS_GENERAL
:
1635 *reg_list_size
= 33;
1638 *reg_list_size
= target
->reg_cache
->num_regs
;
1641 LOG_ERROR("Unsupported reg_class: %d", reg_class
);
1645 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
1649 for (int i
= 0; i
< *reg_list_size
; i
++) {
1650 assert(!target
->reg_cache
->reg_list
[i
].valid
||
1651 target
->reg_cache
->reg_list
[i
].size
> 0);
1652 (*reg_list
)[i
] = &target
->reg_cache
->reg_list
[i
];
1654 target
->reg_cache
->reg_list
[i
].exist
&&
1655 !target
->reg_cache
->reg_list
[i
].valid
) {
1656 if (target
->reg_cache
->reg_list
[i
].type
->get(
1657 &target
->reg_cache
->reg_list
[i
]) != ERROR_OK
)
1665 static int riscv_get_gdb_reg_list_noread(struct target
*target
,
1666 struct reg
**reg_list
[], int *reg_list_size
,
1667 enum target_register_class reg_class
)
1669 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1673 static int riscv_get_gdb_reg_list(struct target
*target
,
1674 struct reg
**reg_list
[], int *reg_list_size
,
1675 enum target_register_class reg_class
)
1677 return riscv_get_gdb_reg_list_internal(target
, reg_list
, reg_list_size
,
1681 static int riscv_arch_state(struct target
*target
)
1683 struct target_type
*tt
= get_target_type(target
);
1684 return tt
->arch_state(target
);
1687 /* Algorithm must end with a software breakpoint instruction. */
1688 static int riscv_run_algorithm(struct target
*target
, int num_mem_params
,
1689 struct mem_param
*mem_params
, int num_reg_params
,
1690 struct reg_param
*reg_params
, target_addr_t entry_point
,
1691 target_addr_t exit_point
, int timeout_ms
, void *arch_info
)
1693 riscv_info_t
*info
= (riscv_info_t
*) target
->arch_info
;
1694 int hartid
= riscv_current_hartid(target
);
1696 if (num_mem_params
> 0) {
1697 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1701 if (target
->state
!= TARGET_HALTED
) {
1702 LOG_WARNING("target not halted");
1703 return ERROR_TARGET_NOT_HALTED
;
1706 /* Save registers */
1707 struct reg
*reg_pc
= register_get_by_name(target
->reg_cache
, "pc", 1);
1708 if (!reg_pc
|| reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1710 uint64_t saved_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1711 LOG_DEBUG("saved_pc=0x%" PRIx64
, saved_pc
);
1713 uint64_t saved_regs
[32];
1714 for (int i
= 0; i
< num_reg_params
; i
++) {
1715 LOG_DEBUG("save %s", reg_params
[i
].reg_name
);
1716 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1718 LOG_ERROR("Couldn't find register named '%s'", reg_params
[i
].reg_name
);
1722 if (r
->size
!= reg_params
[i
].size
) {
1723 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1724 reg_params
[i
].reg_name
, r
->size
, reg_params
[i
].size
);
1728 if (r
->number
> GDB_REGNO_XPR31
) {
1729 LOG_ERROR("Only GPRs can be use as argument registers.");
1733 if (r
->type
->get(r
) != ERROR_OK
)
1735 saved_regs
[r
->number
] = buf_get_u64(r
->value
, 0, r
->size
);
1737 if (reg_params
[i
].direction
== PARAM_OUT
|| reg_params
[i
].direction
== PARAM_IN_OUT
) {
1738 if (r
->type
->set(r
, reg_params
[i
].value
) != ERROR_OK
)
1744 /* Disable Interrupts before attempting to run the algorithm. */
1745 uint64_t current_mstatus
;
1746 uint8_t mstatus_bytes
[8] = { 0 };
1748 LOG_DEBUG("Disabling Interrupts");
1749 struct reg
*reg_mstatus
= register_get_by_name(target
->reg_cache
,
1752 LOG_ERROR("Couldn't find mstatus!");
1756 reg_mstatus
->type
->get(reg_mstatus
);
1757 current_mstatus
= buf_get_u64(reg_mstatus
->value
, 0, reg_mstatus
->size
);
1758 uint64_t ie_mask
= MSTATUS_MIE
| MSTATUS_HIE
| MSTATUS_SIE
| MSTATUS_UIE
;
1759 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], set_field(current_mstatus
,
1762 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1765 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR
, entry_point
);
1766 if (riscv_resume(target
, 0, entry_point
, 0, 0, true) != ERROR_OK
)
1769 int64_t start
= timeval_ms();
1770 while (target
->state
!= TARGET_HALTED
) {
1771 LOG_DEBUG("poll()");
1772 int64_t now
= timeval_ms();
1773 if (now
- start
> timeout_ms
) {
1774 LOG_ERROR("Algorithm timed out after %" PRId64
" ms.", now
- start
);
1776 old_or_new_riscv_poll(target
);
1777 enum gdb_regno regnums
[] = {
1778 GDB_REGNO_RA
, GDB_REGNO_SP
, GDB_REGNO_GP
, GDB_REGNO_TP
,
1779 GDB_REGNO_T0
, GDB_REGNO_T1
, GDB_REGNO_T2
, GDB_REGNO_FP
,
1780 GDB_REGNO_S1
, GDB_REGNO_A0
, GDB_REGNO_A1
, GDB_REGNO_A2
,
1781 GDB_REGNO_A3
, GDB_REGNO_A4
, GDB_REGNO_A5
, GDB_REGNO_A6
,
1782 GDB_REGNO_A7
, GDB_REGNO_S2
, GDB_REGNO_S3
, GDB_REGNO_S4
,
1783 GDB_REGNO_S5
, GDB_REGNO_S6
, GDB_REGNO_S7
, GDB_REGNO_S8
,
1784 GDB_REGNO_S9
, GDB_REGNO_S10
, GDB_REGNO_S11
, GDB_REGNO_T3
,
1785 GDB_REGNO_T4
, GDB_REGNO_T5
, GDB_REGNO_T6
,
1787 GDB_REGNO_MSTATUS
, GDB_REGNO_MEPC
, GDB_REGNO_MCAUSE
,
1789 for (unsigned i
= 0; i
< ARRAY_SIZE(regnums
); i
++) {
1790 enum gdb_regno regno
= regnums
[i
];
1791 riscv_reg_t reg_value
;
1792 if (riscv_get_register(target
, ®_value
, regno
) != ERROR_OK
)
1794 LOG_ERROR("%s = 0x%" PRIx64
, gdb_regno_name(regno
), reg_value
);
1796 return ERROR_TARGET_TIMEOUT
;
1799 int result
= old_or_new_riscv_poll(target
);
1800 if (result
!= ERROR_OK
)
1804 /* The current hart id might have been changed in poll(). */
1805 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1808 if (reg_pc
->type
->get(reg_pc
) != ERROR_OK
)
1810 uint64_t final_pc
= buf_get_u64(reg_pc
->value
, 0, reg_pc
->size
);
1811 if (exit_point
&& final_pc
!= exit_point
) {
1812 LOG_ERROR("PC ended up at 0x%" PRIx64
" instead of 0x%"
1813 TARGET_PRIxADDR
, final_pc
, exit_point
);
1817 /* Restore Interrupts */
1818 LOG_DEBUG("Restoring Interrupts");
1819 buf_set_u64(mstatus_bytes
, 0, info
->xlen
[0], current_mstatus
);
1820 reg_mstatus
->type
->set(reg_mstatus
, mstatus_bytes
);
1822 /* Restore registers */
1823 uint8_t buf
[8] = { 0 };
1824 buf_set_u64(buf
, 0, info
->xlen
[0], saved_pc
);
1825 if (reg_pc
->type
->set(reg_pc
, buf
) != ERROR_OK
)
1828 for (int i
= 0; i
< num_reg_params
; i
++) {
1829 if (reg_params
[i
].direction
== PARAM_IN
||
1830 reg_params
[i
].direction
== PARAM_IN_OUT
) {
1831 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1832 if (r
->type
->get(r
) != ERROR_OK
) {
1833 LOG_ERROR("get(%s) failed", r
->name
);
1836 buf_cpy(r
->value
, reg_params
[i
].value
, reg_params
[i
].size
);
1838 LOG_DEBUG("restore %s", reg_params
[i
].reg_name
);
1839 struct reg
*r
= register_get_by_name(target
->reg_cache
, reg_params
[i
].reg_name
, 0);
1840 buf_set_u64(buf
, 0, info
->xlen
[0], saved_regs
[r
->number
]);
1841 if (r
->type
->set(r
, buf
) != ERROR_OK
) {
1842 LOG_ERROR("set(%s) failed", r
->name
);
1850 static int riscv_checksum_memory(struct target
*target
,
1851 target_addr_t address
, uint32_t count
,
1854 struct working_area
*crc_algorithm
;
1855 struct reg_param reg_params
[2];
1858 LOG_DEBUG("address=0x%" TARGET_PRIxADDR
"; count=0x%" PRIx32
, address
, count
);
1860 static const uint8_t riscv32_crc_code
[] = {
1861 #include "../../contrib/loaders/checksum/riscv32_crc.inc"
1863 static const uint8_t riscv64_crc_code
[] = {
1864 #include "../../contrib/loaders/checksum/riscv64_crc.inc"
1867 static const uint8_t *crc_code
;
1869 unsigned xlen
= riscv_xlen(target
);
1870 unsigned crc_code_size
;
1872 crc_code
= riscv32_crc_code
;
1873 crc_code_size
= sizeof(riscv32_crc_code
);
1875 crc_code
= riscv64_crc_code
;
1876 crc_code_size
= sizeof(riscv64_crc_code
);
1879 if (count
< crc_code_size
* 4) {
1880 /* Don't use the algorithm for relatively small buffers. It's faster
1881 * just to read the memory. target_checksum_memory() will take care of
1882 * that if we fail. */
1886 retval
= target_alloc_working_area(target
, crc_code_size
, &crc_algorithm
);
1887 if (retval
!= ERROR_OK
)
1890 if (crc_algorithm
->address
+ crc_algorithm
->size
> address
&&
1891 crc_algorithm
->address
< address
+ count
) {
1892 /* Region to checksum overlaps with the work area we've been assigned.
1893 * Bail. (Would be better to manually checksum what we read there, and
1894 * use the algorithm for the rest.) */
1895 target_free_working_area(target
, crc_algorithm
);
1899 retval
= target_write_buffer(target
, crc_algorithm
->address
, crc_code_size
,
1901 if (retval
!= ERROR_OK
) {
1902 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT
": %d",
1903 crc_algorithm
->address
, retval
);
1904 target_free_working_area(target
, crc_algorithm
);
1908 init_reg_param(®_params
[0], "a0", xlen
, PARAM_IN_OUT
);
1909 init_reg_param(®_params
[1], "a1", xlen
, PARAM_OUT
);
1910 buf_set_u64(reg_params
[0].value
, 0, xlen
, address
);
1911 buf_set_u64(reg_params
[1].value
, 0, xlen
, count
);
1913 /* 20 second timeout/megabyte */
1914 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
1916 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
1917 crc_algorithm
->address
,
1918 0, /* Leave exit point unspecified because we don't know. */
1921 if (retval
== ERROR_OK
)
1922 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
1924 LOG_ERROR("error executing RISC-V CRC algorithm");
1926 destroy_reg_param(®_params
[0]);
1927 destroy_reg_param(®_params
[1]);
1929 target_free_working_area(target
, crc_algorithm
);
1931 LOG_DEBUG("checksum=0x%" PRIx32
", result=%d", *checksum
, retval
);
1936 /*** OpenOCD Helper Functions ***/
1938 enum riscv_poll_hart
{
1940 RPH_DISCOVERED_HALTED
,
1941 RPH_DISCOVERED_RUNNING
,
1944 static enum riscv_poll_hart
riscv_poll_hart(struct target
*target
, int hartid
)
1947 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
1950 LOG_DEBUG("polling hart %d, target->state=%d", hartid
, target
->state
);
1952 /* If OpenOCD thinks we're running but this hart is halted then it's time
1953 * to raise an event. */
1954 bool halted
= riscv_is_halted(target
);
1955 if (target
->state
!= TARGET_HALTED
&& halted
) {
1956 LOG_DEBUG(" triggered a halt");
1958 return RPH_DISCOVERED_HALTED
;
1959 } else if (target
->state
!= TARGET_RUNNING
&& !halted
) {
1960 LOG_DEBUG(" triggered running");
1961 target
->state
= TARGET_RUNNING
;
1962 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1963 return RPH_DISCOVERED_RUNNING
;
1966 return RPH_NO_CHANGE
;
1969 int set_debug_reason(struct target
*target
, enum riscv_halt_reason halt_reason
)
1971 switch (halt_reason
) {
1972 case RISCV_HALT_BREAKPOINT
:
1973 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1975 case RISCV_HALT_TRIGGER
:
1976 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1978 case RISCV_HALT_INTERRUPT
:
1979 case RISCV_HALT_GROUP
:
1980 target
->debug_reason
= DBG_REASON_DBGRQ
;
1982 case RISCV_HALT_SINGLESTEP
:
1983 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1985 case RISCV_HALT_UNKNOWN
:
1986 target
->debug_reason
= DBG_REASON_UNDEFINED
;
1988 case RISCV_HALT_ERROR
:
1991 LOG_DEBUG("[%s] debug_reason=%d", target_name(target
), target
->debug_reason
);
1995 /*** OpenOCD Interface ***/
1996 int riscv_openocd_poll(struct target
*target
)
1998 LOG_DEBUG("polling all harts");
1999 int halted_hart
= -1;
2000 if (riscv_rtos_enabled(target
)) {
2001 /* Check every hart for an event. */
2002 for (int i
= 0; i
< riscv_count_harts(target
); ++i
) {
2003 enum riscv_poll_hart out
= riscv_poll_hart(target
, i
);
2006 case RPH_DISCOVERED_RUNNING
:
2008 case RPH_DISCOVERED_HALTED
:
2015 if (halted_hart
== -1) {
2016 LOG_DEBUG(" no harts just halted, target->state=%d", target
->state
);
2019 LOG_DEBUG(" hart %d halted", halted_hart
);
2021 target
->state
= TARGET_HALTED
;
2022 enum riscv_halt_reason halt_reason
= riscv_halt_reason(target
, halted_hart
);
2023 if (set_debug_reason(target
, halt_reason
) != ERROR_OK
)
2026 target
->rtos
->current_threadid
= halted_hart
+ 1;
2027 target
->rtos
->current_thread
= halted_hart
+ 1;
2028 riscv_set_rtos_hartid(target
, halted_hart
);
2030 /* If we're here then at least one hart triggered. That means we want
2031 * to go and halt _every_ hart (configured with -rtos riscv) in the
2032 * system, as that's the invariant we hold here. Some harts might have
2033 * already halted (as we're either in single-step mode or they also
2034 * triggered a breakpoint), so don't attempt to halt those harts.
2035 * riscv_halt() will do all that for us. */
2038 } else if (target
->smp
) {
2039 unsigned halts_discovered
= 0;
2040 unsigned total_targets
= 0;
2041 unsigned should_remain_halted
= 0;
2042 unsigned should_resume
= 0;
2044 for (struct target_list
*list
= target
->head
; list
!= NULL
;
2045 list
= list
->next
, i
++) {
2047 struct target
*t
= list
->target
;
2048 riscv_info_t
*r
= riscv_info(t
);
2049 enum riscv_poll_hart out
= riscv_poll_hart(t
, r
->current_hartid
);
2053 case RPH_DISCOVERED_RUNNING
:
2054 t
->state
= TARGET_RUNNING
;
2055 t
->debug_reason
= DBG_REASON_NOTHALTED
;
2057 case RPH_DISCOVERED_HALTED
:
2059 t
->state
= TARGET_HALTED
;
2060 enum riscv_halt_reason halt_reason
=
2061 riscv_halt_reason(t
, r
->current_hartid
);
2062 if (set_debug_reason(t
, halt_reason
) != ERROR_OK
)
2065 if (halt_reason
== RISCV_HALT_BREAKPOINT
) {
2067 switch (riscv_semihosting(t
, &retval
)) {
2070 /* This hart should remain halted. */
2071 should_remain_halted
++;
2074 /* This hart should be resumed, along with any other
2075 * harts that halted due to haltgroups. */
2081 } else if (halt_reason
!= RISCV_HALT_GROUP
) {
2082 should_remain_halted
++;
2091 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2092 should_remain_halted
, should_resume
);
2093 if (should_remain_halted
&& should_resume
) {
2094 LOG_WARNING("%d harts should remain halted, and %d should resume.",
2095 should_remain_halted
, should_resume
);
2097 if (should_remain_halted
) {
2098 LOG_DEBUG("halt all");
2100 } else if (should_resume
) {
2101 LOG_DEBUG("resume all");
2102 riscv_resume(target
, true, 0, 0, 0, false);
2107 enum riscv_poll_hart out
= riscv_poll_hart(target
,
2108 riscv_current_hartid(target
));
2109 if (out
== RPH_NO_CHANGE
|| out
== RPH_DISCOVERED_RUNNING
)
2111 else if (out
== RPH_ERROR
)
2114 halted_hart
= riscv_current_hartid(target
);
2115 LOG_DEBUG(" hart %d halted", halted_hart
);
2117 enum riscv_halt_reason halt_reason
= riscv_halt_reason(target
, halted_hart
);
2118 if (set_debug_reason(target
, halt_reason
) != ERROR_OK
)
2120 target
->state
= TARGET_HALTED
;
2123 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
2125 switch (riscv_semihosting(target
, &retval
)) {
2128 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2131 if (riscv_resume(target
, true, 0, 0, 0, false) != ERROR_OK
)
2138 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2144 int riscv_openocd_step(struct target
*target
, int current
,
2145 target_addr_t address
, int handle_breakpoints
)
2147 LOG_DEBUG("stepping rtos hart");
2150 riscv_set_register(target
, GDB_REGNO_PC
, address
);
2152 riscv_reg_t trigger_state
[RISCV_MAX_HWBPS
] = {0};
2153 if (disable_triggers(target
, trigger_state
) != ERROR_OK
)
2156 int out
= riscv_step_rtos_hart(target
);
2157 if (out
!= ERROR_OK
) {
2158 LOG_ERROR("unable to step rtos hart");
2162 register_cache_invalidate(target
->reg_cache
);
2164 if (enable_triggers(target
, trigger_state
) != ERROR_OK
)
2167 target
->state
= TARGET_RUNNING
;
2168 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
2169 target
->state
= TARGET_HALTED
;
2170 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2171 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
2175 /* Command Handlers */
2176 COMMAND_HANDLER(riscv_set_command_timeout_sec
)
2178 if (CMD_ARGC
!= 1) {
2179 LOG_ERROR("Command takes exactly 1 parameter");
2180 return ERROR_COMMAND_SYNTAX_ERROR
;
2182 int timeout
= atoi(CMD_ARGV
[0]);
2184 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2188 riscv_command_timeout_sec
= timeout
;
2193 COMMAND_HANDLER(riscv_set_reset_timeout_sec
)
2195 if (CMD_ARGC
!= 1) {
2196 LOG_ERROR("Command takes exactly 1 parameter");
2197 return ERROR_COMMAND_SYNTAX_ERROR
;
2199 int timeout
= atoi(CMD_ARGV
[0]);
2201 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV
[0]);
2205 riscv_reset_timeout_sec
= timeout
;
2209 COMMAND_HANDLER(riscv_test_compliance
) {
2211 struct target
*target
= get_current_target(CMD_CTX
);
2216 LOG_ERROR("Command does not take any parameters.");
2217 return ERROR_COMMAND_SYNTAX_ERROR
;
2220 if (r
->test_compliance
) {
2221 return r
->test_compliance(target
);
2223 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
2228 COMMAND_HANDLER(riscv_set_prefer_sba
)
2230 if (CMD_ARGC
!= 1) {
2231 LOG_ERROR("Command takes exactly 1 parameter");
2232 return ERROR_COMMAND_SYNTAX_ERROR
;
2234 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_prefer_sba
);
2238 COMMAND_HANDLER(riscv_set_enable_virtual
)
2240 if (CMD_ARGC
!= 1) {
2241 LOG_ERROR("Command takes exactly 1 parameter");
2242 return ERROR_COMMAND_SYNTAX_ERROR
;
2244 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virtual
);
2248 void parse_error(const char *string
, char c
, unsigned position
)
2250 char buf
[position
+2];
2251 for (unsigned i
= 0; i
< position
; i
++)
2253 buf
[position
] = '^';
2254 buf
[position
+ 1] = 0;
2256 LOG_ERROR("Parse error at character %c in:", c
);
2257 LOG_ERROR("%s", string
);
2258 LOG_ERROR("%s", buf
);
2261 int parse_ranges(range_t
**ranges
, const char **argv
)
2263 for (unsigned pass
= 0; pass
< 2; pass
++) {
2266 bool parse_low
= true;
2268 for (unsigned i
= 0; i
== 0 || argv
[0][i
-1]; i
++) {
2269 char c
= argv
[0][i
];
2271 /* Ignore whitespace. */
2279 } else if (c
== '-') {
2281 } else if (c
== ',' || c
== 0) {
2283 (*ranges
)[range
].low
= low
;
2284 (*ranges
)[range
].high
= low
;
2289 parse_error(argv
[0], c
, i
);
2290 return ERROR_COMMAND_SYNTAX_ERROR
;
2297 } else if (c
== ',' || c
== 0) {
2300 (*ranges
)[range
].low
= low
;
2301 (*ranges
)[range
].high
= high
;
2307 parse_error(argv
[0], c
, i
);
2308 return ERROR_COMMAND_SYNTAX_ERROR
;
2315 *ranges
= calloc(range
+ 2, sizeof(range_t
));
2319 (*ranges
)[range
].low
= 1;
2320 (*ranges
)[range
].high
= 0;
2327 COMMAND_HANDLER(riscv_set_expose_csrs
)
2329 if (CMD_ARGC
!= 1) {
2330 LOG_ERROR("Command takes exactly 1 parameter");
2331 return ERROR_COMMAND_SYNTAX_ERROR
;
2334 return parse_ranges(&expose_csr
, CMD_ARGV
);
2337 COMMAND_HANDLER(riscv_set_expose_custom
)
2339 if (CMD_ARGC
!= 1) {
2340 LOG_ERROR("Command takes exactly 1 parameter");
2341 return ERROR_COMMAND_SYNTAX_ERROR
;
2344 return parse_ranges(&expose_custom
, CMD_ARGV
);
2347 COMMAND_HANDLER(riscv_authdata_read
)
2349 if (CMD_ARGC
!= 0) {
2350 LOG_ERROR("Command takes no parameters");
2351 return ERROR_COMMAND_SYNTAX_ERROR
;
2354 struct target
*target
= get_current_target(CMD_CTX
);
2356 LOG_ERROR("target is NULL!");
2362 LOG_ERROR("riscv_info is NULL!");
2366 if (r
->authdata_read
) {
2368 if (r
->authdata_read(target
, &value
) != ERROR_OK
)
2370 command_print_sameline(CMD
, "0x%08" PRIx32
, value
);
2373 LOG_ERROR("authdata_read is not implemented for this target.");
2378 COMMAND_HANDLER(riscv_authdata_write
)
2380 if (CMD_ARGC
!= 1) {
2381 LOG_ERROR("Command takes exactly 1 argument");
2382 return ERROR_COMMAND_SYNTAX_ERROR
;
2385 struct target
*target
= get_current_target(CMD_CTX
);
2389 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], value
);
2391 if (r
->authdata_write
) {
2392 return r
->authdata_write(target
, value
);
2394 LOG_ERROR("authdata_write is not implemented for this target.");
2399 COMMAND_HANDLER(riscv_dmi_read
)
2401 if (CMD_ARGC
!= 1) {
2402 LOG_ERROR("Command takes 1 parameter");
2403 return ERROR_COMMAND_SYNTAX_ERROR
;
2406 struct target
*target
= get_current_target(CMD_CTX
);
2408 LOG_ERROR("target is NULL!");
2414 LOG_ERROR("riscv_info is NULL!");
2419 uint32_t address
, value
;
2420 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2421 if (r
->dmi_read(target
, &value
, address
) != ERROR_OK
)
2423 command_print(CMD
, "0x%" PRIx32
, value
);
2426 LOG_ERROR("dmi_read is not implemented for this target.");
2432 COMMAND_HANDLER(riscv_dmi_write
)
2434 if (CMD_ARGC
!= 2) {
2435 LOG_ERROR("Command takes exactly 2 arguments");
2436 return ERROR_COMMAND_SYNTAX_ERROR
;
2439 struct target
*target
= get_current_target(CMD_CTX
);
2442 uint32_t address
, value
;
2443 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
2444 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2447 return r
->dmi_write(target
, address
, value
);
2449 LOG_ERROR("dmi_write is not implemented for this target.");
2454 COMMAND_HANDLER(riscv_test_sba_config_reg
)
2456 if (CMD_ARGC
!= 4) {
2457 LOG_ERROR("Command takes exactly 4 arguments");
2458 return ERROR_COMMAND_SYNTAX_ERROR
;
2461 struct target
*target
= get_current_target(CMD_CTX
);
2464 target_addr_t legal_address
;
2466 target_addr_t illegal_address
;
2467 bool run_sbbusyerror_test
;
2469 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[0], legal_address
);
2470 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], num_words
);
2471 COMMAND_PARSE_NUMBER(target_addr
, CMD_ARGV
[2], illegal_address
);
2472 COMMAND_PARSE_ON_OFF(CMD_ARGV
[3], run_sbbusyerror_test
);
2474 if (r
->test_sba_config_reg
) {
2475 return r
->test_sba_config_reg(target
, legal_address
, num_words
,
2476 illegal_address
, run_sbbusyerror_test
);
2478 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2483 COMMAND_HANDLER(riscv_reset_delays
)
2488 LOG_ERROR("Command takes at most one argument");
2489 return ERROR_COMMAND_SYNTAX_ERROR
;
2493 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], wait
);
2495 struct target
*target
= get_current_target(CMD_CTX
);
2497 r
->reset_delays_wait
= wait
;
2501 COMMAND_HANDLER(riscv_set_ir
)
2503 if (CMD_ARGC
!= 2) {
2504 LOG_ERROR("Command takes exactly 2 arguments");
2505 return ERROR_COMMAND_SYNTAX_ERROR
;
2509 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
2511 if (!strcmp(CMD_ARGV
[0], "idcode"))
2512 buf_set_u32(ir_idcode
, 0, 32, value
);
2513 else if (!strcmp(CMD_ARGV
[0], "dtmcs"))
2514 buf_set_u32(ir_dtmcontrol
, 0, 32, value
);
2515 else if (!strcmp(CMD_ARGV
[0], "dmi"))
2516 buf_set_u32(ir_dbus
, 0, 32, value
);
2523 COMMAND_HANDLER(riscv_resume_order
)
2526 LOG_ERROR("Command takes at most one argument");
2527 return ERROR_COMMAND_SYNTAX_ERROR
;
2530 if (!strcmp(CMD_ARGV
[0], "normal")) {
2531 resume_order
= RO_NORMAL
;
2532 } else if (!strcmp(CMD_ARGV
[0], "reversed")) {
2533 resume_order
= RO_REVERSED
;
2535 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV
[0]);
2542 COMMAND_HANDLER(riscv_use_bscan_tunnel
)
2545 int tunnel_type
= BSCAN_TUNNEL_NESTED_TAP
;
2548 LOG_ERROR("Command takes at most two arguments");
2549 return ERROR_COMMAND_SYNTAX_ERROR
;
2550 } else if (CMD_ARGC
== 1) {
2551 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2552 } else if (CMD_ARGC
== 2) {
2553 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], irwidth
);
2554 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[1], tunnel_type
);
2556 if (tunnel_type
== BSCAN_TUNNEL_NESTED_TAP
)
2557 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2558 else if (tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
)
2559 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2561 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2563 bscan_tunnel_type
= tunnel_type
;
2564 bscan_tunnel_ir_width
= irwidth
;
2568 COMMAND_HANDLER(riscv_set_enable_virt2phys
)
2570 if (CMD_ARGC
!= 1) {
2571 LOG_ERROR("Command takes exactly 1 parameter");
2572 return ERROR_COMMAND_SYNTAX_ERROR
;
2574 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_enable_virt2phys
);
2578 COMMAND_HANDLER(riscv_set_ebreakm
)
2580 if (CMD_ARGC
!= 1) {
2581 LOG_ERROR("Command takes exactly 1 parameter");
2582 return ERROR_COMMAND_SYNTAX_ERROR
;
2584 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreakm
);
2588 COMMAND_HANDLER(riscv_set_ebreaks
)
2590 if (CMD_ARGC
!= 1) {
2591 LOG_ERROR("Command takes exactly 1 parameter");
2592 return ERROR_COMMAND_SYNTAX_ERROR
;
2594 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaks
);
2598 COMMAND_HANDLER(riscv_set_ebreaku
)
2600 if (CMD_ARGC
!= 1) {
2601 LOG_ERROR("Command takes exactly 1 parameter");
2602 return ERROR_COMMAND_SYNTAX_ERROR
;
2604 COMMAND_PARSE_ON_OFF(CMD_ARGV
[0], riscv_ebreaku
);
2608 static const struct command_registration riscv_exec_command_handlers
[] = {
2610 .name
= "test_compliance",
2611 .handler
= riscv_test_compliance
,
2613 .mode
= COMMAND_EXEC
,
2614 .help
= "Runs a basic compliance test suite against the RISC-V Debug Spec."
2617 .name
= "set_command_timeout_sec",
2618 .handler
= riscv_set_command_timeout_sec
,
2619 .mode
= COMMAND_ANY
,
2621 .help
= "Set the wall-clock timeout (in seconds) for individual commands"
2624 .name
= "set_reset_timeout_sec",
2625 .handler
= riscv_set_reset_timeout_sec
,
2626 .mode
= COMMAND_ANY
,
2628 .help
= "Set the wall-clock timeout (in seconds) after reset is deasserted"
2631 .name
= "set_prefer_sba",
2632 .handler
= riscv_set_prefer_sba
,
2633 .mode
= COMMAND_ANY
,
2635 .help
= "When on, prefer to use System Bus Access to access memory. "
2636 "When off (default), prefer to use the Program Buffer to access memory."
2639 .name
= "set_enable_virtual",
2640 .handler
= riscv_set_enable_virtual
,
2641 .mode
= COMMAND_ANY
,
2643 .help
= "When on, memory accesses are performed on physical or virtual "
2644 "memory depending on the current system configuration. "
2645 "When off (default), all memory accessses are performed on physical memory."
2648 .name
= "expose_csrs",
2649 .handler
= riscv_set_expose_csrs
,
2650 .mode
= COMMAND_ANY
,
2651 .usage
= "n0[-m0][,n1[-m1]]...",
2652 .help
= "Configure a list of inclusive ranges for CSRs to expose in "
2653 "addition to the standard ones. This must be executed before "
2657 .name
= "expose_custom",
2658 .handler
= riscv_set_expose_custom
,
2659 .mode
= COMMAND_ANY
,
2660 .usage
= "n0[-m0][,n1[-m1]]...",
2661 .help
= "Configure a list of inclusive ranges for custom registers to "
2662 "expose. custom0 is accessed as abstract register number 0xc000, "
2663 "etc. This must be executed before `init`."
2666 .name
= "authdata_read",
2667 .handler
= riscv_authdata_read
,
2669 .mode
= COMMAND_ANY
,
2670 .help
= "Return the 32-bit value read from authdata."
2673 .name
= "authdata_write",
2674 .handler
= riscv_authdata_write
,
2675 .mode
= COMMAND_ANY
,
2677 .help
= "Write the 32-bit value to authdata."
2681 .handler
= riscv_dmi_read
,
2682 .mode
= COMMAND_ANY
,
2684 .help
= "Perform a 32-bit DMI read at address, returning the value."
2687 .name
= "dmi_write",
2688 .handler
= riscv_dmi_write
,
2689 .mode
= COMMAND_ANY
,
2690 .usage
= "address value",
2691 .help
= "Perform a 32-bit DMI write of value at address."
2694 .name
= "test_sba_config_reg",
2695 .handler
= riscv_test_sba_config_reg
,
2696 .mode
= COMMAND_ANY
,
2697 .usage
= "legal_address num_words "
2698 "illegal_address run_sbbusyerror_test[on/off]",
2699 .help
= "Perform a series of tests on the SBCS register. "
2700 "Inputs are a legal, 128-byte aligned address and a number of words to "
2701 "read/write starting at that address (i.e., address range [legal address, "
2702 "legal_address+word_size*num_words) must be legally readable/writable), "
2703 "an illegal, 128-byte aligned address for error flag/handling cases, "
2704 "and whether sbbusyerror test should be run."
2707 .name
= "reset_delays",
2708 .handler
= riscv_reset_delays
,
2709 .mode
= COMMAND_ANY
,
2711 .help
= "OpenOCD learns how many Run-Test/Idle cycles are required "
2712 "between scans to avoid encountering the target being busy. This "
2713 "command resets those learned values after `wait` scans. It's only "
2714 "useful for testing OpenOCD itself."
2717 .name
= "resume_order",
2718 .handler
= riscv_resume_order
,
2719 .mode
= COMMAND_ANY
,
2720 .usage
= "normal|reversed",
2721 .help
= "Choose the order that harts are resumed in when `hasel` is not "
2722 "supported. Normal order is from lowest hart index to highest. "
2723 "Reversed order is from highest hart index to lowest."
2727 .handler
= riscv_set_ir
,
2728 .mode
= COMMAND_ANY
,
2729 .usage
= "[idcode|dtmcs|dmi] value",
2730 .help
= "Set IR value for specified JTAG register."
2733 .name
= "use_bscan_tunnel",
2734 .handler
= riscv_use_bscan_tunnel
,
2735 .mode
= COMMAND_ANY
,
2736 .usage
= "value [type]",
2737 .help
= "Enable or disable use of a BSCAN tunnel to reach DM. Supply "
2738 "the width of the DM transport TAP's instruction register to "
2739 "enable. Supply a value of 0 to disable. Pass A second argument "
2740 "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
2744 .name
= "set_enable_virt2phys",
2745 .handler
= riscv_set_enable_virt2phys
,
2746 .mode
= COMMAND_ANY
,
2748 .help
= "When on (default), enable translation from virtual address to "
2752 .name
= "set_ebreakm",
2753 .handler
= riscv_set_ebreakm
,
2754 .mode
= COMMAND_ANY
,
2756 .help
= "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
2757 "don't trap to OpenOCD. Defaults to on."
2760 .name
= "set_ebreaks",
2761 .handler
= riscv_set_ebreaks
,
2762 .mode
= COMMAND_ANY
,
2764 .help
= "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
2765 "don't trap to OpenOCD. Defaults to on."
2768 .name
= "set_ebreaku",
2769 .handler
= riscv_set_ebreaku
,
2770 .mode
= COMMAND_ANY
,
2772 .help
= "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
2773 "don't trap to OpenOCD. Defaults to on."
2775 COMMAND_REGISTRATION_DONE
2779 * To be noted that RISC-V targets use the same semihosting commands as
2782 * The main reason is compatibility with existing tools. For example the
2783 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
2784 * configure semihosting, which generate commands like `arm semihosting
2786 * A secondary reason is the fact that the protocol used is exactly the
2787 * one specified by ARM. If RISC-V will ever define its own semihosting
2788 * protocol, then a command like `riscv semihosting enable` will make
2789 * sense, but for now all semihosting commands are prefixed with `arm`.
2791 extern const struct command_registration semihosting_common_handlers
[];
2793 const struct command_registration riscv_command_handlers
[] = {
2796 .mode
= COMMAND_ANY
,
2797 .help
= "RISC-V Command Group",
2799 .chain
= riscv_exec_command_handlers
2803 .mode
= COMMAND_ANY
,
2804 .help
= "ARM Command Group",
2806 .chain
= semihosting_common_handlers
2808 COMMAND_REGISTRATION_DONE
2811 static unsigned riscv_xlen_nonconst(struct target
*target
)
2813 return riscv_xlen(target
);
2816 struct target_type riscv_target
= {
2819 .init_target
= riscv_init_target
,
2820 .deinit_target
= riscv_deinit_target
,
2821 .examine
= riscv_examine
,
2823 /* poll current target status */
2824 .poll
= old_or_new_riscv_poll
,
2827 .resume
= riscv_target_resume
,
2828 .step
= old_or_new_riscv_step
,
2830 .assert_reset
= riscv_assert_reset
,
2831 .deassert_reset
= riscv_deassert_reset
,
2833 .read_memory
= riscv_read_memory
,
2834 .write_memory
= riscv_write_memory
,
2835 .read_phys_memory
= riscv_read_phys_memory
,
2836 .write_phys_memory
= riscv_write_phys_memory
,
2838 .checksum_memory
= riscv_checksum_memory
,
2841 .virt2phys
= riscv_virt2phys
,
2843 .get_gdb_reg_list
= riscv_get_gdb_reg_list
,
2844 .get_gdb_reg_list_noread
= riscv_get_gdb_reg_list_noread
,
2846 .add_breakpoint
= riscv_add_breakpoint
,
2847 .remove_breakpoint
= riscv_remove_breakpoint
,
2849 .add_watchpoint
= riscv_add_watchpoint
,
2850 .remove_watchpoint
= riscv_remove_watchpoint
,
2851 .hit_watchpoint
= riscv_hit_watchpoint
,
2853 .arch_state
= riscv_arch_state
,
2855 .run_algorithm
= riscv_run_algorithm
,
2857 .commands
= riscv_command_handlers
,
2859 .address_bits
= riscv_xlen_nonconst
,
2862 /*** RISC-V Interface ***/
2864 void riscv_info_init(struct target
*target
, riscv_info_t
*r
)
2866 memset(r
, 0, sizeof(*r
));
2868 r
->registers_initialized
= false;
2869 r
->current_hartid
= target
->coreid
;
2871 memset(r
->trigger_unique_id
, 0xff, sizeof(r
->trigger_unique_id
));
2873 for (size_t h
= 0; h
< RISCV_MAX_HARTS
; ++h
)
2877 static int riscv_resume_go_all_harts(struct target
*target
)
2881 /* Dummy variables to make mingw32-gcc happy. */
2885 switch (resume_order
) {
2888 last
= riscv_count_harts(target
) - 1;
2892 first
= riscv_count_harts(target
) - 1;
2900 for (int i
= first
; i
!= last
+ step
; i
+= step
) {
2901 if (!riscv_hart_enabled(target
, i
))
2904 LOG_DEBUG("resuming hart %d", i
);
2905 if (riscv_set_current_hartid(target
, i
) != ERROR_OK
)
2907 if (riscv_is_halted(target
)) {
2908 if (r
->resume_go(target
) != ERROR_OK
)
2911 LOG_DEBUG(" hart %d requested resume, but was already resumed", i
);
2915 riscv_invalidate_register_cache(target
);
2919 int riscv_step_rtos_hart(struct target
*target
)
2922 int hartid
= r
->current_hartid
;
2923 if (riscv_rtos_enabled(target
)) {
2924 hartid
= r
->rtos_hartid
;
2926 LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2930 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
2932 LOG_DEBUG("stepping hart %d", hartid
);
2934 if (!riscv_is_halted(target
)) {
2935 LOG_ERROR("Hart isn't halted before single step!");
2938 riscv_invalidate_register_cache(target
);
2940 if (r
->step_current_hart(target
) != ERROR_OK
)
2942 riscv_invalidate_register_cache(target
);
2944 if (!riscv_is_halted(target
)) {
2945 LOG_ERROR("Hart was not halted after single step!");
2951 bool riscv_supports_extension(struct target
*target
, int hartid
, char letter
)
2955 if (letter
>= 'a' && letter
<= 'z')
2957 else if (letter
>= 'A' && letter
<= 'Z')
2961 return r
->misa
[hartid
] & (1 << num
);
2964 unsigned riscv_xlen(const struct target
*target
)
2966 return riscv_xlen_of_hart(target
, riscv_current_hartid(target
));
2969 int riscv_xlen_of_hart(const struct target
*target
, int hartid
)
2972 assert(r
->xlen
[hartid
] != -1);
2973 return r
->xlen
[hartid
];
2976 bool riscv_rtos_enabled(const struct target
*target
)
2981 int riscv_set_current_hartid(struct target
*target
, int hartid
)
2984 if (!r
->select_current_hart
)
2987 int previous_hartid
= riscv_current_hartid(target
);
2988 r
->current_hartid
= hartid
;
2989 assert(riscv_hart_enabled(target
, hartid
));
2990 LOG_DEBUG("setting hartid to %d, was %d", hartid
, previous_hartid
);
2991 if (r
->select_current_hart(target
) != ERROR_OK
)
2994 /* This might get called during init, in which case we shouldn't be
2995 * setting up the register cache. */
2996 if (target_was_examined(target
) && riscv_rtos_enabled(target
))
2997 riscv_invalidate_register_cache(target
);
3002 void riscv_invalidate_register_cache(struct target
*target
)
3006 LOG_DEBUG("[%d]", target
->coreid
);
3007 register_cache_invalidate(target
->reg_cache
);
3008 for (size_t i
= 0; i
< target
->reg_cache
->num_regs
; ++i
) {
3009 struct reg
*reg
= &target
->reg_cache
->reg_list
[i
];
3013 r
->registers_initialized
= true;
3016 int riscv_current_hartid(const struct target
*target
)
3019 return r
->current_hartid
;
3022 void riscv_set_all_rtos_harts(struct target
*target
)
3025 r
->rtos_hartid
= -1;
3028 void riscv_set_rtos_hartid(struct target
*target
, int hartid
)
3030 LOG_DEBUG("setting RTOS hartid %d", hartid
);
3032 r
->rtos_hartid
= hartid
;
3035 int riscv_count_harts(struct target
*target
)
3040 if (r
== NULL
|| r
->hart_count
== NULL
)
3042 return r
->hart_count(target
);
3045 bool riscv_has_register(struct target
*target
, int hartid
, int regid
)
3052 * return true iff we are guaranteed that the register will contain exactly
3053 * the value we just wrote when it's read.
3054 * If write is false:
3055 * return true iff we are guaranteed that the register will read the same
3056 * value in the future as the value we just read.
3058 static bool gdb_regno_cacheable(enum gdb_regno regno
, bool write
)
3060 /* GPRs, FPRs, vector registers are just normal data stores. */
3061 if (regno
<= GDB_REGNO_XPR31
||
3062 (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
) ||
3063 (regno
>= GDB_REGNO_V0
&& regno
<= GDB_REGNO_V31
))
3066 /* Most CSRs won't change value on us, but we can't assume it about rbitrary
3072 case GDB_REGNO_VSTART
:
3073 case GDB_REGNO_VXSAT
:
3074 case GDB_REGNO_VXRM
:
3075 case GDB_REGNO_VLENB
:
3077 case GDB_REGNO_VTYPE
:
3078 case GDB_REGNO_MISA
:
3079 case GDB_REGNO_DCSR
:
3080 case GDB_REGNO_DSCRATCH0
:
3081 case GDB_REGNO_MSTATUS
:
3082 case GDB_REGNO_MEPC
:
3083 case GDB_REGNO_MCAUSE
:
3084 case GDB_REGNO_SATP
:
3086 * WARL registers might not contain the value we just wrote, but
3087 * these ones won't spontaneously change their value either. *
3091 case GDB_REGNO_TSELECT
: /* I think this should be above, but then it doesn't work. */
3092 case GDB_REGNO_TDATA1
: /* Changes value when tselect is changed. */
3093 case GDB_REGNO_TDATA2
: /* Changse value when tselect is changed. */
3100 * This function is called when the debug user wants to change the value of a
3101 * register. The new value may be cached, and may not be written until the hart
3103 int riscv_set_register(struct target
*target
, enum gdb_regno r
, riscv_reg_t v
)
3105 return riscv_set_register_on_hart(target
, riscv_current_hartid(target
), r
, v
);
3108 int riscv_set_register_on_hart(struct target
*target
, int hartid
,
3109 enum gdb_regno regid
, uint64_t value
)
3112 LOG_DEBUG("{%d} %s <- %" PRIx64
, hartid
, gdb_regno_name(regid
), value
);
3113 assert(r
->set_register
);
3115 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3116 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&& value
== 0 &&
3117 riscv_supports_extension(target
, hartid
, 'E'))
3120 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3121 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3123 int result
= r
->set_register(target
, hartid
, regid
, value
);
3124 if (result
== ERROR_OK
)
3125 reg
->valid
= gdb_regno_cacheable(regid
, true);
3128 LOG_DEBUG("[%s]{%d} wrote 0x%" PRIx64
" to %s valid=%d",
3129 target_name(target
), hartid
, value
, reg
->name
, reg
->valid
);
3133 int riscv_get_register(struct target
*target
, riscv_reg_t
*value
,
3136 return riscv_get_register_on_hart(target
, value
,
3137 riscv_current_hartid(target
), r
);
3140 int riscv_get_register_on_hart(struct target
*target
, riscv_reg_t
*value
,
3141 int hartid
, enum gdb_regno regid
)
3145 struct reg
*reg
= &target
->reg_cache
->reg_list
[regid
];
3147 LOG_DEBUG("[%s]{%d} %s does not exist.",
3148 target_name(target
), hartid
, gdb_regno_name(regid
));
3152 if (reg
&& reg
->valid
&& hartid
== riscv_current_hartid(target
)) {
3153 *value
= buf_get_u64(reg
->value
, 0, reg
->size
);
3154 LOG_DEBUG("{%d} %s: %" PRIx64
" (cached)", hartid
,
3155 gdb_regno_name(regid
), *value
);
3159 /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3160 if (regid
> GDB_REGNO_XPR15
&& regid
<= GDB_REGNO_XPR31
&&
3161 riscv_supports_extension(target
, hartid
, 'E')) {
3166 int result
= r
->get_register(target
, value
, hartid
, regid
);
3168 if (result
== ERROR_OK
)
3169 reg
->valid
= gdb_regno_cacheable(regid
, false);
3171 LOG_DEBUG("{%d} %s: %" PRIx64
, hartid
, gdb_regno_name(regid
), *value
);
3175 bool riscv_is_halted(struct target
*target
)
3178 assert(r
->is_halted
);
3179 return r
->is_halted(target
);
3182 enum riscv_halt_reason
riscv_halt_reason(struct target
*target
, int hartid
)
3185 if (riscv_set_current_hartid(target
, hartid
) != ERROR_OK
)
3186 return RISCV_HALT_ERROR
;
3187 if (!riscv_is_halted(target
)) {
3188 LOG_ERROR("Hart is not halted!");
3189 return RISCV_HALT_UNKNOWN
;
3191 return r
->halt_reason(target
);
3194 size_t riscv_debug_buffer_size(struct target
*target
)
3197 return r
->debug_buffer_size
[riscv_current_hartid(target
)];
3200 int riscv_write_debug_buffer(struct target
*target
, int index
, riscv_insn_t insn
)
3203 r
->write_debug_buffer(target
, index
, insn
);
3207 riscv_insn_t
riscv_read_debug_buffer(struct target
*target
, int index
)
3210 return r
->read_debug_buffer(target
, index
);
3213 int riscv_execute_debug_buffer(struct target
*target
)
3216 return r
->execute_debug_buffer(target
);
3219 void riscv_fill_dmi_write_u64(struct target
*target
, char *buf
, int a
, uint64_t d
)
3222 r
->fill_dmi_write_u64(target
, buf
, a
, d
);
3225 void riscv_fill_dmi_read_u64(struct target
*target
, char *buf
, int a
)
3228 r
->fill_dmi_read_u64(target
, buf
, a
);
3231 void riscv_fill_dmi_nop_u64(struct target
*target
, char *buf
)
3234 r
->fill_dmi_nop_u64(target
, buf
);
3237 int riscv_dmi_write_u64_bits(struct target
*target
)
3240 return r
->dmi_write_u64_bits(target
);
3243 bool riscv_hart_enabled(struct target
*target
, int hartid
)
3245 /* FIXME: Add a hart mask to the RTOS. */
3246 if (riscv_rtos_enabled(target
))
3247 return hartid
< riscv_count_harts(target
);
3249 return hartid
== target
->coreid
;
3253 * Count triggers, and initialize trigger_count for each hart.
3254 * trigger_count is initialized even if this function fails to discover
3256 * Disable any hardware triggers that have dmode set. We can't have set them
3257 * ourselves. Maybe they're left over from some killed debug session.
3259 int riscv_enumerate_triggers(struct target
*target
)
3263 if (r
->triggers_enumerated
)
3266 r
->triggers_enumerated
= true; /* At the very least we tried. */
3268 for (int hartid
= 0; hartid
< riscv_count_harts(target
); ++hartid
) {
3269 if (!riscv_hart_enabled(target
, hartid
))
3272 riscv_reg_t tselect
;
3273 int result
= riscv_get_register_on_hart(target
, &tselect
, hartid
,
3275 if (result
!= ERROR_OK
)
3278 for (unsigned t
= 0; t
< RISCV_MAX_TRIGGERS
; ++t
) {
3279 r
->trigger_count
[hartid
] = t
;
3281 /* If we can't write tselect, then this hart does not support triggers. */
3282 if (riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, t
) != ERROR_OK
)
3284 uint64_t tselect_rb
;
3285 result
= riscv_get_register_on_hart(target
, &tselect_rb
, hartid
,
3287 if (result
!= ERROR_OK
)
3289 /* Mask off the top bit, which is used as tdrmode in old
3290 * implementations. */
3291 tselect_rb
&= ~(1ULL << (riscv_xlen(target
)-1));
3292 if (tselect_rb
!= t
)
3295 result
= riscv_get_register_on_hart(target
, &tdata1
, hartid
,
3297 if (result
!= ERROR_OK
)
3300 int type
= get_field(tdata1
, MCONTROL_TYPE(riscv_xlen(target
)));
3305 /* On these older cores we don't support software using
3307 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
3310 if (tdata1
& MCONTROL_DMODE(riscv_xlen(target
)))
3311 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TDATA1
, 0);
3316 riscv_set_register_on_hart(target
, hartid
, GDB_REGNO_TSELECT
, tselect
);
3318 LOG_INFO("[%d] Found %d triggers", hartid
, r
->trigger_count
[hartid
]);
3324 const char *gdb_regno_name(enum gdb_regno regno
)
3326 static char buf
[32];
3329 case GDB_REGNO_ZERO
:
3395 case GDB_REGNO_FPR0
:
3397 case GDB_REGNO_FPR31
:
3399 case GDB_REGNO_CSR0
:
3401 case GDB_REGNO_TSELECT
:
3403 case GDB_REGNO_TDATA1
:
3405 case GDB_REGNO_TDATA2
:
3407 case GDB_REGNO_MISA
:
3411 case GDB_REGNO_DCSR
:
3413 case GDB_REGNO_DSCRATCH0
:
3415 case GDB_REGNO_MSTATUS
:
3417 case GDB_REGNO_MEPC
:
3419 case GDB_REGNO_MCAUSE
:
3421 case GDB_REGNO_PRIV
:
3423 case GDB_REGNO_SATP
:
3425 case GDB_REGNO_VTYPE
:
3494 if (regno
<= GDB_REGNO_XPR31
)
3495 sprintf(buf
, "x%d", regno
- GDB_REGNO_ZERO
);
3496 else if (regno
>= GDB_REGNO_CSR0
&& regno
<= GDB_REGNO_CSR4095
)
3497 sprintf(buf
, "csr%d", regno
- GDB_REGNO_CSR0
);
3498 else if (regno
>= GDB_REGNO_FPR0
&& regno
<= GDB_REGNO_FPR31
)
3499 sprintf(buf
, "f%d", regno
- GDB_REGNO_FPR0
);
3501 sprintf(buf
, "gdb_regno_%d", regno
);
3506 static int register_get(struct reg
*reg
)
3508 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3509 struct target
*target
= reg_info
->target
;
3512 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3513 if (!r
->get_register_buf
) {
3514 LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3515 gdb_regno_name(reg
->number
));
3519 if (r
->get_register_buf(target
, reg
->value
, reg
->number
) != ERROR_OK
)
3523 int result
= riscv_get_register(target
, &value
, reg
->number
);
3524 if (result
!= ERROR_OK
)
3526 buf_set_u64(reg
->value
, 0, reg
->size
, value
);
3528 reg
->valid
= gdb_regno_cacheable(reg
->number
, false);
3529 char *str
= buf_to_hex_str(reg
->value
, reg
->size
);
3530 LOG_DEBUG("[%d]{%d} read 0x%s from %s (valid=%d)", target
->coreid
,
3531 riscv_current_hartid(target
), str
, reg
->name
, reg
->valid
);
3536 static int register_set(struct reg
*reg
, uint8_t *buf
)
3538 riscv_reg_info_t
*reg_info
= reg
->arch_info
;
3539 struct target
*target
= reg_info
->target
;
3542 char *str
= buf_to_hex_str(buf
, reg
->size
);
3543 LOG_DEBUG("[%d]{%d} write 0x%s to %s (valid=%d)", target
->coreid
,
3544 riscv_current_hartid(target
), str
, reg
->name
, reg
->valid
);
3547 memcpy(reg
->value
, buf
, DIV_ROUND_UP(reg
->size
, 8));
3548 reg
->valid
= gdb_regno_cacheable(reg
->number
, true);
3550 if (reg
->number
== GDB_REGNO_TDATA1
||
3551 reg
->number
== GDB_REGNO_TDATA2
) {
3552 r
->manual_hwbp_set
= true;
3553 /* When enumerating triggers, we clear any triggers with DMODE set,
3554 * assuming they were left over from a previous debug session. So make
3555 * sure that is done before a user might be setting their own triggers.
3557 if (riscv_enumerate_triggers(target
) != ERROR_OK
)
3561 if (reg
->number
>= GDB_REGNO_V0
&& reg
->number
<= GDB_REGNO_V31
) {
3562 if (!r
->set_register_buf
) {
3563 LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3564 gdb_regno_name(reg
->number
));
3568 if (r
->set_register_buf(target
, reg
->number
, reg
->value
) != ERROR_OK
)
3571 uint64_t value
= buf_get_u64(buf
, 0, reg
->size
);
3572 if (riscv_set_register(target
, reg
->number
, value
) != ERROR_OK
)
3579 static struct reg_arch_type riscv_reg_arch_type
= {
3580 .get
= register_get
,
3589 static int cmp_csr_info(const void *p1
, const void *p2
)
3591 return (int) (((struct csr_info
*)p1
)->number
) - (int) (((struct csr_info
*)p2
)->number
);
3594 int riscv_init_registers(struct target
*target
)
3598 riscv_free_registers(target
);
3600 target
->reg_cache
= calloc(1, sizeof(*target
->reg_cache
));
3601 if (!target
->reg_cache
)
3603 target
->reg_cache
->name
= "RISC-V Registers";
3604 target
->reg_cache
->num_regs
= GDB_REGNO_COUNT
;
3606 if (expose_custom
) {
3607 for (unsigned i
= 0; expose_custom
[i
].low
<= expose_custom
[i
].high
; i
++) {
3608 for (unsigned number
= expose_custom
[i
].low
;
3609 number
<= expose_custom
[i
].high
;
3611 target
->reg_cache
->num_regs
++;
3615 LOG_DEBUG("create register cache for %d registers",
3616 target
->reg_cache
->num_regs
);
3618 target
->reg_cache
->reg_list
=
3619 calloc(target
->reg_cache
->num_regs
, sizeof(struct reg
));
3620 if (!target
->reg_cache
->reg_list
)
3623 const unsigned int max_reg_name_len
= 12;
3624 free(info
->reg_names
);
3626 calloc(target
->reg_cache
->num_regs
, max_reg_name_len
);
3627 if (!info
->reg_names
)
3629 char *reg_name
= info
->reg_names
;
3631 int hartid
= riscv_current_hartid(target
);
3633 static struct reg_feature feature_cpu
= {
3634 .name
= "org.gnu.gdb.riscv.cpu"
3636 static struct reg_feature feature_fpu
= {
3637 .name
= "org.gnu.gdb.riscv.fpu"
3639 static struct reg_feature feature_csr
= {
3640 .name
= "org.gnu.gdb.riscv.csr"
3642 static struct reg_feature feature_vector
= {
3643 .name
= "org.gnu.gdb.riscv.vector"
3645 static struct reg_feature feature_virtual
= {
3646 .name
= "org.gnu.gdb.riscv.virtual"
3648 static struct reg_feature feature_custom
= {
3649 .name
= "org.gnu.gdb.riscv.custom"
3652 /* These types are built into gdb. */
3653 static struct reg_data_type type_ieee_single
= { .type
= REG_TYPE_IEEE_SINGLE
, .id
= "ieee_single" };
3654 static struct reg_data_type type_ieee_double
= { .type
= REG_TYPE_IEEE_DOUBLE
, .id
= "ieee_double" };
3655 static struct reg_data_type_union_field single_double_fields
[] = {
3656 {"float", &type_ieee_single
, single_double_fields
+ 1},
3657 {"double", &type_ieee_double
, NULL
},
3659 static struct reg_data_type_union single_double_union
= {
3660 .fields
= single_double_fields
3662 static struct reg_data_type type_ieee_single_double
= {
3663 .type
= REG_TYPE_ARCH_DEFINED
,
3665 .type_class
= REG_TYPE_CLASS_UNION
,
3666 .reg_type_union
= &single_double_union
3668 static struct reg_data_type type_uint8
= { .type
= REG_TYPE_UINT8
, .id
= "uint8" };
3669 static struct reg_data_type type_uint16
= { .type
= REG_TYPE_UINT16
, .id
= "uint16" };
3670 static struct reg_data_type type_uint32
= { .type
= REG_TYPE_UINT32
, .id
= "uint32" };
3671 static struct reg_data_type type_uint64
= { .type
= REG_TYPE_UINT64
, .id
= "uint64" };
3672 static struct reg_data_type type_uint128
= { .type
= REG_TYPE_UINT128
, .id
= "uint128" };
3674 /* This is roughly the XML we want:
3675 * <vector id="bytes" type="uint8" count="16"/>
3676 * <vector id="shorts" type="uint16" count="8"/>
3677 * <vector id="words" type="uint32" count="4"/>
3678 * <vector id="longs" type="uint64" count="2"/>
3679 * <vector id="quads" type="uint128" count="1"/>
3680 * <union id="riscv_vector_type">
3681 * <field name="b" type="bytes"/>
3682 * <field name="s" type="shorts"/>
3683 * <field name="w" type="words"/>
3684 * <field name="l" type="longs"/>
3685 * <field name="q" type="quads"/>
3689 info
->vector_uint8
.type
= &type_uint8
;
3690 info
->vector_uint8
.count
= info
->vlenb
[hartid
];
3691 info
->type_uint8_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3692 info
->type_uint8_vector
.id
= "bytes";
3693 info
->type_uint8_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3694 info
->type_uint8_vector
.reg_type_vector
= &info
->vector_uint8
;
3696 info
->vector_uint16
.type
= &type_uint16
;
3697 info
->vector_uint16
.count
= info
->vlenb
[hartid
] / 2;
3698 info
->type_uint16_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3699 info
->type_uint16_vector
.id
= "shorts";
3700 info
->type_uint16_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3701 info
->type_uint16_vector
.reg_type_vector
= &info
->vector_uint16
;
3703 info
->vector_uint32
.type
= &type_uint32
;
3704 info
->vector_uint32
.count
= info
->vlenb
[hartid
] / 4;
3705 info
->type_uint32_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3706 info
->type_uint32_vector
.id
= "words";
3707 info
->type_uint32_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3708 info
->type_uint32_vector
.reg_type_vector
= &info
->vector_uint32
;
3710 info
->vector_uint64
.type
= &type_uint64
;
3711 info
->vector_uint64
.count
= info
->vlenb
[hartid
] / 8;
3712 info
->type_uint64_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3713 info
->type_uint64_vector
.id
= "longs";
3714 info
->type_uint64_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3715 info
->type_uint64_vector
.reg_type_vector
= &info
->vector_uint64
;
3717 info
->vector_uint128
.type
= &type_uint128
;
3718 info
->vector_uint128
.count
= info
->vlenb
[hartid
] / 16;
3719 info
->type_uint128_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3720 info
->type_uint128_vector
.id
= "quads";
3721 info
->type_uint128_vector
.type_class
= REG_TYPE_CLASS_VECTOR
;
3722 info
->type_uint128_vector
.reg_type_vector
= &info
->vector_uint128
;
3724 info
->vector_fields
[0].name
= "b";
3725 info
->vector_fields
[0].type
= &info
->type_uint8_vector
;
3726 if (info
->vlenb
[hartid
] >= 2) {
3727 info
->vector_fields
[0].next
= info
->vector_fields
+ 1;
3728 info
->vector_fields
[1].name
= "s";
3729 info
->vector_fields
[1].type
= &info
->type_uint16_vector
;
3731 info
->vector_fields
[0].next
= NULL
;
3733 if (info
->vlenb
[hartid
] >= 4) {
3734 info
->vector_fields
[1].next
= info
->vector_fields
+ 2;
3735 info
->vector_fields
[2].name
= "w";
3736 info
->vector_fields
[2].type
= &info
->type_uint32_vector
;
3738 info
->vector_fields
[1].next
= NULL
;
3740 if (info
->vlenb
[hartid
] >= 8) {
3741 info
->vector_fields
[2].next
= info
->vector_fields
+ 3;
3742 info
->vector_fields
[3].name
= "l";
3743 info
->vector_fields
[3].type
= &info
->type_uint64_vector
;
3745 info
->vector_fields
[2].next
= NULL
;
3747 if (info
->vlenb
[hartid
] >= 16) {
3748 info
->vector_fields
[3].next
= info
->vector_fields
+ 4;
3749 info
->vector_fields
[4].name
= "q";
3750 info
->vector_fields
[4].type
= &info
->type_uint128_vector
;
3752 info
->vector_fields
[3].next
= NULL
;
3754 info
->vector_fields
[4].next
= NULL
;
3756 info
->vector_union
.fields
= info
->vector_fields
;
3758 info
->type_vector
.type
= REG_TYPE_ARCH_DEFINED
;
3759 info
->type_vector
.id
= "riscv_vector";
3760 info
->type_vector
.type_class
= REG_TYPE_CLASS_UNION
;
3761 info
->type_vector
.reg_type_union
= &info
->vector_union
;
3763 struct csr_info csr_info
[] = {
3764 #define DECLARE_CSR(name, number) { number, #name },
3765 #include "encoding.h"
3768 /* encoding.h does not contain the registers in sorted order. */
3769 qsort(csr_info
, ARRAY_SIZE(csr_info
), sizeof(*csr_info
), cmp_csr_info
);
3770 unsigned csr_info_index
= 0;
3772 unsigned custom_range_index
= 0;
3773 int custom_within_range
= 0;
3775 riscv_reg_info_t
*shared_reg_info
= calloc(1, sizeof(riscv_reg_info_t
));
3776 if (!shared_reg_info
)
3778 shared_reg_info
->target
= target
;
3780 /* When gdb requests register N, gdb_get_register_packet() assumes that this
3781 * is register at index N in reg_list. So if there are certain registers
3782 * that don't exist, we need to leave holes in the list (or renumber, but
3783 * it would be nice not to have yet another set of numbers to translate
3785 for (uint32_t number
= 0; number
< target
->reg_cache
->num_regs
; number
++) {
3786 struct reg
*r
= &target
->reg_cache
->reg_list
[number
];
3790 r
->type
= &riscv_reg_arch_type
;
3791 r
->arch_info
= shared_reg_info
;
3793 r
->size
= riscv_xlen(target
);
3794 /* r->size is set in riscv_invalidate_register_cache, maybe because the
3795 * target is in theory allowed to change XLEN on us. But I expect a lot
3796 * of other things to break in that case as well. */
3797 if (number
<= GDB_REGNO_XPR31
) {
3798 r
->exist
= number
<= GDB_REGNO_XPR15
||
3799 !riscv_supports_extension(target
, hartid
, 'E');
3800 /* TODO: For now we fake that all GPRs exist because otherwise gdb
3803 r
->caller_save
= true;
3805 case GDB_REGNO_ZERO
:
3902 r
->group
= "general";
3903 r
->feature
= &feature_cpu
;
3904 } else if (number
== GDB_REGNO_PC
) {
3905 r
->caller_save
= true;
3906 sprintf(reg_name
, "pc");
3907 r
->group
= "general";
3908 r
->feature
= &feature_cpu
;
3909 } else if (number
>= GDB_REGNO_FPR0
&& number
<= GDB_REGNO_FPR31
) {
3910 r
->caller_save
= true;
3911 if (riscv_supports_extension(target
, hartid
, 'D')) {
3913 if (riscv_supports_extension(target
, hartid
, 'F'))
3914 r
->reg_data_type
= &type_ieee_single_double
;
3916 r
->reg_data_type
= &type_ieee_double
;
3917 } else if (riscv_supports_extension(target
, hartid
, 'F')) {
3918 r
->reg_data_type
= &type_ieee_single
;
4002 case GDB_REGNO_FS10
:
4005 case GDB_REGNO_FS11
:
4014 case GDB_REGNO_FT10
:
4017 case GDB_REGNO_FT11
:
4022 r
->feature
= &feature_fpu
;
4023 } else if (number
>= GDB_REGNO_CSR0
&& number
<= GDB_REGNO_CSR4095
) {
4025 r
->feature
= &feature_csr
;
4026 unsigned csr_number
= number
- GDB_REGNO_CSR0
;
4028 while (csr_info
[csr_info_index
].number
< csr_number
&&
4029 csr_info_index
< ARRAY_SIZE(csr_info
) - 1) {
4032 if (csr_info
[csr_info_index
].number
== csr_number
) {
4033 r
->name
= csr_info
[csr_info_index
].name
;
4035 sprintf(reg_name
, "csr%d", csr_number
);
4036 /* Assume unnamed registers don't exist, unless we have some
4037 * configuration that tells us otherwise. That's important
4038 * because eg. Eclipse crashes if a target has too many
4039 * registers, and apparently has no way of only showing a
4040 * subset of registers in any case. */
4044 switch (csr_number
) {
4048 r
->exist
= riscv_supports_extension(target
, hartid
, 'F');
4050 r
->feature
= &feature_fpu
;
4056 case CSR_SCOUNTEREN
:
4062 r
->exist
= riscv_supports_extension(target
, hartid
, 'S');
4066 /* "In systems with only M-mode, or with both M-mode and
4067 * U-mode but without U-mode trap support, the medeleg and
4068 * mideleg registers should not exist." */
4069 r
->exist
= riscv_supports_extension(target
, hartid
, 'S') ||
4070 riscv_supports_extension(target
, hartid
, 'N');
4078 case CSR_HPMCOUNTER3H
:
4079 case CSR_HPMCOUNTER4H
:
4080 case CSR_HPMCOUNTER5H
:
4081 case CSR_HPMCOUNTER6H
:
4082 case CSR_HPMCOUNTER7H
:
4083 case CSR_HPMCOUNTER8H
:
4084 case CSR_HPMCOUNTER9H
:
4085 case CSR_HPMCOUNTER10H
:
4086 case CSR_HPMCOUNTER11H
:
4087 case CSR_HPMCOUNTER12H
:
4088 case CSR_HPMCOUNTER13H
:
4089 case CSR_HPMCOUNTER14H
:
4090 case CSR_HPMCOUNTER15H
:
4091 case CSR_HPMCOUNTER16H
:
4092 case CSR_HPMCOUNTER17H
:
4093 case CSR_HPMCOUNTER18H
:
4094 case CSR_HPMCOUNTER19H
:
4095 case CSR_HPMCOUNTER20H
:
4096 case CSR_HPMCOUNTER21H
:
4097 case CSR_HPMCOUNTER22H
:
4098 case CSR_HPMCOUNTER23H
:
4099 case CSR_HPMCOUNTER24H
:
4100 case CSR_HPMCOUNTER25H
:
4101 case CSR_HPMCOUNTER26H
:
4102 case CSR_HPMCOUNTER27H
:
4103 case CSR_HPMCOUNTER28H
:
4104 case CSR_HPMCOUNTER29H
:
4105 case CSR_HPMCOUNTER30H
:
4106 case CSR_HPMCOUNTER31H
:
4109 case CSR_MHPMCOUNTER3H
:
4110 case CSR_MHPMCOUNTER4H
:
4111 case CSR_MHPMCOUNTER5H
:
4112 case CSR_MHPMCOUNTER6H
:
4113 case CSR_MHPMCOUNTER7H
:
4114 case CSR_MHPMCOUNTER8H
:
4115 case CSR_MHPMCOUNTER9H
:
4116 case CSR_MHPMCOUNTER10H
:
4117 case CSR_MHPMCOUNTER11H
:
4118 case CSR_MHPMCOUNTER12H
:
4119 case CSR_MHPMCOUNTER13H
:
4120 case CSR_MHPMCOUNTER14H
:
4121 case CSR_MHPMCOUNTER15H
:
4122 case CSR_MHPMCOUNTER16H
:
4123 case CSR_MHPMCOUNTER17H
:
4124 case CSR_MHPMCOUNTER18H
:
4125 case CSR_MHPMCOUNTER19H
:
4126 case CSR_MHPMCOUNTER20H
:
4127 case CSR_MHPMCOUNTER21H
:
4128 case CSR_MHPMCOUNTER22H
:
4129 case CSR_MHPMCOUNTER23H
:
4130 case CSR_MHPMCOUNTER24H
:
4131 case CSR_MHPMCOUNTER25H
:
4132 case CSR_MHPMCOUNTER26H
:
4133 case CSR_MHPMCOUNTER27H
:
4134 case CSR_MHPMCOUNTER28H
:
4135 case CSR_MHPMCOUNTER29H
:
4136 case CSR_MHPMCOUNTER30H
:
4137 case CSR_MHPMCOUNTER31H
:
4138 r
->exist
= riscv_xlen(target
) == 32;
4147 r
->exist
= riscv_supports_extension(target
, hartid
, 'V');
4151 if (!r
->exist
&& expose_csr
) {
4152 for (unsigned i
= 0; expose_csr
[i
].low
<= expose_csr
[i
].high
; i
++) {
4153 if (csr_number
>= expose_csr
[i
].low
&& csr_number
<= expose_csr
[i
].high
) {
4154 LOG_INFO("Exposing additional CSR %d", csr_number
);
4161 } else if (number
== GDB_REGNO_PRIV
) {
4162 sprintf(reg_name
, "priv");
4163 r
->group
= "general";
4164 r
->feature
= &feature_virtual
;
4167 } else if (number
>= GDB_REGNO_V0
&& number
<= GDB_REGNO_V31
) {
4168 r
->caller_save
= false;
4169 r
->exist
= riscv_supports_extension(target
, hartid
, 'V') && info
->vlenb
[hartid
];
4170 r
->size
= info
->vlenb
[hartid
] * 8;
4171 sprintf(reg_name
, "v%d", number
- GDB_REGNO_V0
);
4172 r
->group
= "vector";
4173 r
->feature
= &feature_vector
;
4174 r
->reg_data_type
= &info
->type_vector
;
4176 } else if (number
>= GDB_REGNO_COUNT
) {
4177 /* Custom registers. */
4178 assert(expose_custom
);
4180 range_t
*range
= &expose_custom
[custom_range_index
];
4181 assert(range
->low
<= range
->high
);
4182 unsigned custom_number
= range
->low
+ custom_within_range
;
4184 r
->group
= "custom";
4185 r
->feature
= &feature_custom
;
4186 r
->arch_info
= calloc(1, sizeof(riscv_reg_info_t
));
4189 ((riscv_reg_info_t
*) r
->arch_info
)->target
= target
;
4190 ((riscv_reg_info_t
*) r
->arch_info
)->custom_number
= custom_number
;
4191 sprintf(reg_name
, "custom%d", custom_number
);
4193 custom_within_range
++;
4194 if (custom_within_range
> range
->high
- range
->low
) {
4195 custom_within_range
= 0;
4196 custom_range_index
++;
4202 reg_name
+= strlen(reg_name
) + 1;
4203 assert(reg_name
< info
->reg_names
+ target
->reg_cache
->num_regs
*
4205 r
->value
= info
->reg_cache_values
[number
];
4212 void riscv_add_bscan_tunneled_scan(struct target
*target
, struct scan_field
*field
,
4213 riscv_bscan_tunneled_scan_context_t
*ctxt
)
4215 jtag_add_ir_scan(target
->tap
, &select_user4
, TAP_IDLE
);
4217 memset(ctxt
->tunneled_dr
, 0, sizeof(ctxt
->tunneled_dr
));
4218 if (bscan_tunnel_type
== BSCAN_TUNNEL_DATA_REGISTER
) {
4219 ctxt
->tunneled_dr
[3].num_bits
= 1;
4220 ctxt
->tunneled_dr
[3].out_value
= bscan_one
;
4221 ctxt
->tunneled_dr
[2].num_bits
= 7;
4222 ctxt
->tunneled_dr_width
= field
->num_bits
;
4223 ctxt
->tunneled_dr
[2].out_value
= &ctxt
->tunneled_dr_width
;
4224 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4225 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4227 ctxt
->tunneled_dr
[1].num_bits
= field
->num_bits
+ 1;
4228 ctxt
->tunneled_dr
[1].out_value
= field
->out_value
;
4229 ctxt
->tunneled_dr
[1].in_value
= field
->in_value
;
4231 ctxt
->tunneled_dr
[0].num_bits
= 3;
4232 ctxt
->tunneled_dr
[0].out_value
= bscan_zero
;
4234 /* BSCAN_TUNNEL_NESTED_TAP */
4235 ctxt
->tunneled_dr
[0].num_bits
= 1;
4236 ctxt
->tunneled_dr
[0].out_value
= bscan_one
;
4237 ctxt
->tunneled_dr
[1].num_bits
= 7;
4238 ctxt
->tunneled_dr_width
= field
->num_bits
;
4239 ctxt
->tunneled_dr
[1].out_value
= &ctxt
->tunneled_dr_width
;
4240 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4241 scanning num_bits + 1, and then will right shift the input field after executing the queues */
4242 ctxt
->tunneled_dr
[2].num_bits
= field
->num_bits
+ 1;
4243 ctxt
->tunneled_dr
[2].out_value
= field
->out_value
;
4244 ctxt
->tunneled_dr
[2].in_value
= field
->in_value
;
4245 ctxt
->tunneled_dr
[3].num_bits
= 3;
4246 ctxt
->tunneled_dr
[3].out_value
= bscan_zero
;
4248 jtag_add_dr_scan(target
->tap
, ARRAY_SIZE(ctxt
->tunneled_dr
), ctxt
->tunneled_dr
, TAP_IDLE
);