src/target/riscv/riscv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef RISCV_H
   4 #define RISCV_H
   5
   6 struct riscv_program;
   7
   8 #include <stdint.h>
   9 #include "opcodes.h"
  10 #include "gdb_regs.h"
  11 #include "jtag/jtag.h"
  12 #include "target/register.h"
  13 #include <helper/command.h>
  14
  15 /* The register cache is statically allocated. */
  16 #define RISCV_MAX_HARTS 1024
  17 #define RISCV_MAX_REGISTERS 5000
  18 #define RISCV_MAX_TRIGGERS 32
  19 #define RISCV_MAX_HWBPS 16
  20
  21 #define DEFAULT_COMMAND_TIMEOUT_SEC             2
  22 #define DEFAULT_RESET_TIMEOUT_SEC               30
  23
  24 #define RISCV_SATP_MODE(xlen)  ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
  25 #define RISCV_SATP_PPN(xlen)  ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
  26 #define RISCV_PGSHIFT 12
  27
  28 # define PG_MAX_LEVEL 4
  29
  30 #define RISCV_NUM_MEM_ACCESS_METHODS  3
  31
  32 extern struct target_type riscv011_target;
  33 extern struct target_type riscv013_target;
  34
  35 /*
  36  * Definitions shared by code supporting all RISC-V versions.
  37  */
  38 typedef uint64_t riscv_reg_t;
  39 typedef uint32_t riscv_insn_t;
  40 typedef uint64_t riscv_addr_t;
  41
  42 enum riscv_mem_access_method {
  43         RISCV_MEM_ACCESS_UNSPECIFIED,
  44         RISCV_MEM_ACCESS_PROGBUF,
  45         RISCV_MEM_ACCESS_SYSBUS,
  46         RISCV_MEM_ACCESS_ABSTRACT
  47 };
  48
  49 enum riscv_halt_reason {
  50         RISCV_HALT_INTERRUPT,
  51         RISCV_HALT_BREAKPOINT,
  52         RISCV_HALT_SINGLESTEP,
  53         RISCV_HALT_TRIGGER,
  54         RISCV_HALT_UNKNOWN,
  55         RISCV_HALT_GROUP,
  56         RISCV_HALT_ERROR
  57 };
  58
  59 typedef struct {
  60         struct target *target;
  61         unsigned custom_number;
  62 } riscv_reg_info_t;
  63
  64 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE       0x80
  65 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER        0x81
  66 struct riscv_sample_buf {
  67         uint8_t *buf;
  68         unsigned int used;
  69         unsigned int size;
  70 };
  71
  72 typedef struct {
  73         bool enabled;
  74         struct {
  75                 bool enabled;
  76                 target_addr_t address;
  77                 uint32_t size_bytes;
  78         } bucket[16];
  79 } riscv_sample_config_t;
  80
  81 typedef struct {
  82         struct list_head list;
  83         uint16_t low, high;
  84         char *name;
  85 } range_list_t;
  86
  87 typedef struct {
  88         unsigned dtm_version;
  89
  90         struct command_context *cmd_ctx;
  91         void *version_specific;
  92
  93         /* The hart that is currently being debugged.  Note that this is
  94          * different than the hartid that the RTOS is expected to use.  This
  95          * one will change all the time, it's more of a global argument to
  96          * every function than an actual */
  97         int current_hartid;
  98
  99         /* OpenOCD's register cache points into here. This is not per-hart because
 100          * we just invalidate the entire cache when we change which hart is
 101          * selected. Use an array of 8 uint8_t per register. */
 102         uint8_t reg_cache_values[RISCV_MAX_REGISTERS][8];
 103
 104         /* Single buffer that contains all register names, instead of calling
 105          * malloc for each register. Needs to be freed when reg_list is freed. */
 106         char *reg_names;
 107
 108         /* It's possible that each core has a different supported ISA set. */
 109         int xlen;
 110         riscv_reg_t misa;
 111         /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
 112         unsigned int vlenb;
 113
 114         /* The number of triggers per hart. */
 115         unsigned int trigger_count;
 116
 117         /* For each physical trigger, contains -1 if the hwbp is available, or the
 118          * unique_id of the breakpoint/watchpoint that is using it.
 119          * Note that in RTOS mode the triggers are the same across all harts the
 120          * target controls, while otherwise only a single hart is controlled. */
 121         int trigger_unique_id[RISCV_MAX_HWBPS];
 122
 123         /* The number of entries in the debug buffer. */
 124         int debug_buffer_size;
 125
 126         /* This avoids invalidating the register cache too often. */
 127         bool registers_initialized;
 128
 129         /* This hart contains an implicit ebreak at the end of the program buffer. */
 130         bool impebreak;
 131
 132         bool triggers_enumerated;
 133
 134         /* Decremented every scan, and when it reaches 0 we clear the learned
 135          * delays, causing them to be relearned. Used for testing. */
 136         int reset_delays_wait;
 137
 138         /* This target has been prepped and is ready to step/resume. */
 139         bool prepped;
 140         /* This target was selected using hasel. */
 141         bool selected;
 142
 143         /* Helper functions that target the various RISC-V debug spec
 144          * implementations. */
 145         int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
 146         int (*set_register)(struct target *target, int regid, uint64_t value);
 147         int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
 148         int (*set_register_buf)(struct target *target, int regno,
 149                         const uint8_t *buf);
 150         int (*select_current_hart)(struct target *target);
 151         bool (*is_halted)(struct target *target);
 152         /* Resume this target, as well as every other prepped target that can be
 153          * resumed near-simultaneously. Clear the prepped flag on any target that
 154          * was resumed. */
 155         int (*resume_go)(struct target *target);
 156         int (*step_current_hart)(struct target *target);
 157         int (*on_halt)(struct target *target);
 158         /* Get this target as ready as possible to resume, without actually
 159          * resuming. */
 160         int (*resume_prep)(struct target *target);
 161         int (*halt_prep)(struct target *target);
 162         int (*halt_go)(struct target *target);
 163         int (*on_step)(struct target *target);
 164         enum riscv_halt_reason (*halt_reason)(struct target *target);
 165         int (*write_debug_buffer)(struct target *target, unsigned index,
 166                         riscv_insn_t d);
 167         riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
 168         int (*execute_debug_buffer)(struct target *target);
 169         int (*dmi_write_u64_bits)(struct target *target);
 170         void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
 171         void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
 172         void (*fill_dmi_nop_u64)(struct target *target, char *buf);
 173
 174         int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
 175         int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
 176
 177         int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
 178         int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
 179
 180         int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
 181                         uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
 182
 183         int (*sample_memory)(struct target *target,
 184                                                  struct riscv_sample_buf *buf,
 185                                                  riscv_sample_config_t *config,
 186                                                  int64_t until_ms);
 187
 188         int (*read_memory)(struct target *target, target_addr_t address,
 189                         uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
 190
 191         /* How many harts are attached to the DM that this target is attached to? */
 192         int (*hart_count)(struct target *target);
 193         unsigned (*data_bits)(struct target *target);
 194
 195         COMMAND_HELPER((*print_info), struct target *target);
 196
 197         /* Storage for vector register types. */
 198         struct reg_data_type_vector vector_uint8;
 199         struct reg_data_type_vector vector_uint16;
 200         struct reg_data_type_vector vector_uint32;
 201         struct reg_data_type_vector vector_uint64;
 202         struct reg_data_type_vector vector_uint128;
 203         struct reg_data_type type_uint8_vector;
 204         struct reg_data_type type_uint16_vector;
 205         struct reg_data_type type_uint32_vector;
 206         struct reg_data_type type_uint64_vector;
 207         struct reg_data_type type_uint128_vector;
 208         struct reg_data_type_union_field vector_fields[5];
 209         struct reg_data_type_union vector_union;
 210         struct reg_data_type type_vector;
 211
 212         /* Set when trigger registers are changed by the user. This indicates we eed
 213          * to beware that we may hit a trigger that we didn't realize had been set. */
 214         bool manual_hwbp_set;
 215
 216         /* Memory access methods to use, ordered by priority, highest to lowest. */
 217         int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
 218
 219         /* Different memory regions may need different methods but single configuration is applied
 220          * for all. Following flags are used to warn only once about failing memory access method. */
 221         bool mem_access_progbuf_warn;
 222         bool mem_access_sysbus_warn;
 223         bool mem_access_abstract_warn;
 224
 225         /* In addition to the ones in the standard spec, we'll also expose additional
 226          * CSRs in this list. */
 227         struct list_head expose_csr;
 228         /* Same, but for custom registers.
 229          * Custom registers are for non-standard extensions and use abstract register numbers
 230          * from range 0xc000 ... 0xffff. */
 231         struct list_head expose_custom;
 232
 233         riscv_sample_config_t sample_config;
 234         struct riscv_sample_buf sample_buf;
 235 } riscv_info_t;
 236
 237 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
 238                            unsigned int value);
 239
 240 typedef struct {
 241         uint8_t tunneled_dr_width;
 242         struct scan_field tunneled_dr[4];
 243 } riscv_bscan_tunneled_scan_context_t;
 244
 245 typedef struct {
 246         const char *name;
 247         int level;
 248         unsigned va_bits;
 249         unsigned pte_shift;
 250         unsigned vpn_shift[PG_MAX_LEVEL];
 251         unsigned vpn_mask[PG_MAX_LEVEL];
 252         unsigned pte_ppn_shift[PG_MAX_LEVEL];
 253         unsigned pte_ppn_mask[PG_MAX_LEVEL];
 254         unsigned pa_ppn_shift[PG_MAX_LEVEL];
 255         unsigned pa_ppn_mask[PG_MAX_LEVEL];
 256 } virt2phys_info_t;
 257
 258 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 259 extern int riscv_command_timeout_sec;
 260
 261 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 262 extern int riscv_reset_timeout_sec;
 263
 264 extern bool riscv_enable_virtual;
 265 extern bool riscv_ebreakm;
 266 extern bool riscv_ebreaks;
 267 extern bool riscv_ebreaku;
 268
 269 /* Everything needs the RISC-V specific info structure, so here's a nice macro
 270  * that provides that. */
 271 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
 272 static inline riscv_info_t *riscv_info(const struct target *target)
 273 {
 274         assert(target->arch_info);
 275         return target->arch_info;
 276 }
 277 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
 278
 279 extern uint8_t ir_dtmcontrol[4];
 280 extern struct scan_field select_dtmcontrol;
 281 extern uint8_t ir_dbus[4];
 282 extern struct scan_field select_dbus;
 283 extern uint8_t ir_idcode[4];
 284 extern struct scan_field select_idcode;
 285
 286 extern struct scan_field select_user4;
 287 extern struct scan_field *bscan_tunneled_select_dmi;
 288 extern uint32_t bscan_tunneled_select_dmi_num_fields;
 289 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
 290 extern int bscan_tunnel_ir_width;
 291 extern bscan_tunnel_type_t bscan_tunnel_type;
 292
 293 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
 294 void select_dmi_via_bscan(struct target *target);
 295
 296 /*** OpenOCD Interface */
 297 int riscv_openocd_poll(struct target *target);
 298
 299 int riscv_halt(struct target *target);
 300
 301 int riscv_resume(
 302         struct target *target,
 303         int current,
 304         target_addr_t address,
 305         int handle_breakpoints,
 306         int debug_execution,
 307         bool single_hart
 308 );
 309
 310 int riscv_openocd_step(
 311         struct target *target,
 312         int current,
 313         target_addr_t address,
 314         int handle_breakpoints
 315 );
 316
 317 int riscv_openocd_assert_reset(struct target *target);
 318 int riscv_openocd_deassert_reset(struct target *target);
 319
 320 /*** RISC-V Interface ***/
 321
 322 /* Initializes the shared RISC-V structure. */
 323 void riscv_info_init(struct target *target, riscv_info_t *r);
 324
 325 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
 326  * then the only hart. */
 327 int riscv_step_rtos_hart(struct target *target);
 328
 329 bool riscv_supports_extension(struct target *target, char letter);
 330
 331 /* Returns XLEN for the given (or current) hart. */
 332 unsigned riscv_xlen(const struct target *target);
 333 int riscv_xlen_of_hart(const struct target *target);
 334
 335 /* Sets the current hart, which is the hart that will actually be used when
 336  * issuing debug commands. */
 337 int riscv_set_current_hartid(struct target *target, int hartid);
 338 int riscv_select_current_hart(struct target *target);
 339 int riscv_current_hartid(const struct target *target);
 340
 341 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
 342  * without requiring multiple targets.  */
 343
 344 /* Lists the number of harts in the system, which are assumed to be
 345  * consecutive and start with mhartid=0. */
 346 int riscv_count_harts(struct target *target);
 347
 348 /** Set register, updating the cache. */
 349 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
 350 /** Get register, from the cache if it's in there. */
 351 int riscv_get_register(struct target *target, riscv_reg_t *value,
 352                 enum gdb_regno r);
 353
 354 /* Checks the state of the current hart -- "is_halted" checks the actual
 355  * on-device register. */
 356 bool riscv_is_halted(struct target *target);
 357 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
 358
 359 /* These helper functions let the generic program interface get target-specific
 360  * information. */
 361 size_t riscv_debug_buffer_size(struct target *target);
 362
 363 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
 364 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
 365 int riscv_execute_debug_buffer(struct target *target);
 366
 367 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
 368 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
 369 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
 370 int riscv_dmi_write_u64_bits(struct target *target);
 371
 372 /* Invalidates the register cache. */
 373 void riscv_invalidate_register_cache(struct target *target);
 374
 375 int riscv_enumerate_triggers(struct target *target);
 376
 377 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 378 int riscv_remove_breakpoint(struct target *target,
 379                 struct breakpoint *breakpoint);
 380 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 381 int riscv_remove_watchpoint(struct target *target,
 382                 struct watchpoint *watchpoint);
 383 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
 384
 385 int riscv_init_registers(struct target *target);
 386
 387 void riscv_semihosting_init(struct target *target);
 388 typedef enum {
 389         SEMI_NONE,              /* Not halted for a semihosting call. */
 390         SEMI_HANDLED,   /* Call handled, and target was resumed. */
 391         SEMI_WAITING,   /* Call handled, target is halted waiting until we can resume. */
 392         SEMI_ERROR              /* Something went wrong. */
 393 } semihosting_result_t;
 394 semihosting_result_t riscv_semihosting(struct target *target, int *retval);
 395
 396 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
 397                 riscv_bscan_tunneled_scan_context_t *ctxt);
 398
 399 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 400 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 401
 402 #endif