src/target/riscv/riscv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef RISCV_H
   4 #define RISCV_H
   5
   6 struct riscv_program;
   7
   8 #include <stdint.h>
   9 #include "opcodes.h"
  10 #include "gdb_regs.h"
  11 #include "jtag/jtag.h"
  12 #include "target/register.h"
  13
  14 /* The register cache is statically allocated. */
  15 #define RISCV_MAX_HARTS 1024
  16 #define RISCV_MAX_REGISTERS 5000
  17 #define RISCV_MAX_TRIGGERS 32
  18 #define RISCV_MAX_HWBPS 16
  19
  20 #define DEFAULT_COMMAND_TIMEOUT_SEC             2
  21 #define DEFAULT_RESET_TIMEOUT_SEC               30
  22
  23 #define RISCV_SATP_MODE(xlen)  ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
  24 #define RISCV_SATP_PPN(xlen)  ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
  25 #define RISCV_PGSHIFT 12
  26
  27 # define PG_MAX_LEVEL 4
  28
  29 extern struct target_type riscv011_target;
  30 extern struct target_type riscv013_target;
  31
  32 /*
  33  * Definitions shared by code supporting all RISC-V versions.
  34  */
  35 typedef uint64_t riscv_reg_t;
  36 typedef uint32_t riscv_insn_t;
  37 typedef uint64_t riscv_addr_t;
  38
  39 enum riscv_halt_reason {
  40         RISCV_HALT_INTERRUPT,
  41         RISCV_HALT_BREAKPOINT,
  42         RISCV_HALT_SINGLESTEP,
  43         RISCV_HALT_TRIGGER,
  44         RISCV_HALT_UNKNOWN,
  45         RISCV_HALT_GROUP,
  46         RISCV_HALT_ERROR
  47 };
  48
  49 typedef struct {
  50         struct target *target;
  51         unsigned custom_number;
  52 } riscv_reg_info_t;
  53
  54 typedef struct {
  55         unsigned dtm_version;
  56
  57         struct command_context *cmd_ctx;
  58         void *version_specific;
  59
  60         /* The hart that the RTOS thinks is currently being debugged. */
  61         int rtos_hartid;
  62
  63         /* The hart that is currently being debugged.  Note that this is
  64          * different than the hartid that the RTOS is expected to use.  This
  65          * one will change all the time, it's more of a global argument to
  66          * every function than an actual */
  67         int current_hartid;
  68
  69         /* OpenOCD's register cache points into here. This is not per-hart because
  70          * we just invalidate the entire cache when we change which hart is
  71          * selected. Use an array of 8 uint8_t per register. */
  72         uint8_t reg_cache_values[RISCV_MAX_REGISTERS][8];
  73
  74         /* Single buffer that contains all register names, instead of calling
  75          * malloc for each register. Needs to be freed when reg_list is freed. */
  76         char *reg_names;
  77
  78         /* It's possible that each core has a different supported ISA set. */
  79         int xlen[RISCV_MAX_HARTS];
  80         riscv_reg_t misa[RISCV_MAX_HARTS];
  81         /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
  82         unsigned vlenb[RISCV_MAX_HARTS];
  83
  84         /* The number of triggers per hart. */
  85         unsigned trigger_count[RISCV_MAX_HARTS];
  86
  87         /* For each physical trigger, contains -1 if the hwbp is available, or the
  88          * unique_id of the breakpoint/watchpoint that is using it.
  89          * Note that in RTOS mode the triggers are the same across all harts the
  90          * target controls, while otherwise only a single hart is controlled. */
  91         int trigger_unique_id[RISCV_MAX_HWBPS];
  92
  93         /* The number of entries in the debug buffer. */
  94         int debug_buffer_size[RISCV_MAX_HARTS];
  95
  96         /* This avoids invalidating the register cache too often. */
  97         bool registers_initialized;
  98
  99         /* This hart contains an implicit ebreak at the end of the program buffer. */
 100         bool impebreak;
 101
 102         bool triggers_enumerated;
 103
 104         /* Decremented every scan, and when it reaches 0 we clear the learned
 105          * delays, causing them to be relearned. Used for testing. */
 106         int reset_delays_wait;
 107
 108         /* This target has been prepped and is ready to step/resume. */
 109         bool prepped;
 110         /* This target was selected using hasel. */
 111         bool selected;
 112
 113         /* Helper functions that target the various RISC-V debug spec
 114          * implementations. */
 115         int (*get_register)(struct target *target,
 116                 riscv_reg_t *value, int hid, int rid);
 117         int (*set_register)(struct target *target, int hartid, int regid,
 118                         uint64_t value);
 119         int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
 120         int (*set_register_buf)(struct target *target, int regno,
 121                         const uint8_t *buf);
 122         int (*select_current_hart)(struct target *target);
 123         bool (*is_halted)(struct target *target);
 124         /* Resume this target, as well as every other prepped target that can be
 125          * resumed near-simultaneously. Clear the prepped flag on any target that
 126          * was resumed. */
 127         int (*resume_go)(struct target *target);
 128         int (*step_current_hart)(struct target *target);
 129         int (*on_halt)(struct target *target);
 130         /* Get this target as ready as possible to resume, without actually
 131          * resuming. */
 132         int (*resume_prep)(struct target *target);
 133         int (*halt_prep)(struct target *target);
 134         int (*halt_go)(struct target *target);
 135         int (*on_step)(struct target *target);
 136         enum riscv_halt_reason (*halt_reason)(struct target *target);
 137         int (*write_debug_buffer)(struct target *target, unsigned index,
 138                         riscv_insn_t d);
 139         riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
 140         int (*execute_debug_buffer)(struct target *target);
 141         int (*dmi_write_u64_bits)(struct target *target);
 142         void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
 143         void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
 144         void (*fill_dmi_nop_u64)(struct target *target, char *buf);
 145
 146         int (*authdata_read)(struct target *target, uint32_t *value);
 147         int (*authdata_write)(struct target *target, uint32_t value);
 148
 149         int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
 150         int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
 151
 152         int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
 153                         uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
 154
 155         int (*test_compliance)(struct target *target);
 156
 157         int (*read_memory)(struct target *target, target_addr_t address,
 158                         uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
 159
 160         /* How many harts are attached to the DM that this target is attached to? */
 161         int (*hart_count)(struct target *target);
 162         unsigned (*data_bits)(struct target *target);
 163
 164         /* Storage for vector register types. */
 165         struct reg_data_type_vector vector_uint8;
 166         struct reg_data_type_vector vector_uint16;
 167         struct reg_data_type_vector vector_uint32;
 168         struct reg_data_type_vector vector_uint64;
 169         struct reg_data_type_vector vector_uint128;
 170         struct reg_data_type type_uint8_vector;
 171         struct reg_data_type type_uint16_vector;
 172         struct reg_data_type type_uint32_vector;
 173         struct reg_data_type type_uint64_vector;
 174         struct reg_data_type type_uint128_vector;
 175         struct reg_data_type_union_field vector_fields[5];
 176         struct reg_data_type_union vector_union;
 177         struct reg_data_type type_vector;
 178
 179         /* Set when trigger registers are changed by the user. This indicates we eed
 180          * to beware that we may hit a trigger that we didn't realize had been set. */
 181         bool manual_hwbp_set;
 182 } riscv_info_t;
 183
 184 typedef struct {
 185         uint8_t tunneled_dr_width;
 186         struct scan_field tunneled_dr[4];
 187 } riscv_bscan_tunneled_scan_context_t;
 188
 189 typedef struct {
 190         const char *name;
 191         int level;
 192         unsigned va_bits;
 193         unsigned pte_shift;
 194         unsigned vpn_shift[PG_MAX_LEVEL];
 195         unsigned vpn_mask[PG_MAX_LEVEL];
 196         unsigned pte_ppn_shift[PG_MAX_LEVEL];
 197         unsigned pte_ppn_mask[PG_MAX_LEVEL];
 198         unsigned pa_ppn_shift[PG_MAX_LEVEL];
 199         unsigned pa_ppn_mask[PG_MAX_LEVEL];
 200 } virt2phys_info_t;
 201
 202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 203 extern int riscv_command_timeout_sec;
 204
 205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 206 extern int riscv_reset_timeout_sec;
 207
 208 extern bool riscv_prefer_sba;
 209
 210 extern bool riscv_enable_virtual;
 211 extern bool riscv_ebreakm;
 212 extern bool riscv_ebreaks;
 213 extern bool riscv_ebreaku;
 214
 215 /* Everything needs the RISC-V specific info structure, so here's a nice macro
 216  * that provides that. */
 217 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
 218 static inline riscv_info_t *riscv_info(const struct target *target)
 219 { return target->arch_info; }
 220 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
 221
 222 extern uint8_t ir_dtmcontrol[4];
 223 extern struct scan_field select_dtmcontrol;
 224 extern uint8_t ir_dbus[4];
 225 extern struct scan_field select_dbus;
 226 extern uint8_t ir_idcode[4];
 227 extern struct scan_field select_idcode;
 228
 229 extern struct scan_field select_user4;
 230 extern struct scan_field *bscan_tunneled_select_dmi;
 231 extern uint32_t bscan_tunneled_select_dmi_num_fields;
 232 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
 233 extern int bscan_tunnel_ir_width;
 234 extern bscan_tunnel_type_t bscan_tunnel_type;
 235
 236 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
 237 void select_dmi_via_bscan(struct target *target);
 238
 239 /*** OpenOCD Interface */
 240 int riscv_openocd_poll(struct target *target);
 241
 242 int riscv_halt(struct target *target);
 243
 244 int riscv_resume(
 245         struct target *target,
 246         int current,
 247         target_addr_t address,
 248         int handle_breakpoints,
 249         int debug_execution,
 250         bool single_hart
 251 );
 252
 253 int riscv_openocd_step(
 254         struct target *target,
 255         int current,
 256         target_addr_t address,
 257         int handle_breakpoints
 258 );
 259
 260 int riscv_openocd_assert_reset(struct target *target);
 261 int riscv_openocd_deassert_reset(struct target *target);
 262
 263 /*** RISC-V Interface ***/
 264
 265 /* Initializes the shared RISC-V structure. */
 266 void riscv_info_init(struct target *target, riscv_info_t *r);
 267
 268 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
 269  * then the only hart. */
 270 int riscv_step_rtos_hart(struct target *target);
 271
 272 bool riscv_supports_extension(struct target *target, int hartid, char letter);
 273
 274 /* Returns XLEN for the given (or current) hart. */
 275 unsigned riscv_xlen(const struct target *target);
 276 int riscv_xlen_of_hart(const struct target *target, int hartid);
 277
 278 bool riscv_rtos_enabled(const struct target *target);
 279
 280 /* Sets the current hart, which is the hart that will actually be used when
 281  * issuing debug commands. */
 282 int riscv_set_current_hartid(struct target *target, int hartid);
 283 int riscv_current_hartid(const struct target *target);
 284
 285 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
 286  * without requiring multiple targets.  */
 287
 288 /* When using the RTOS to debug, this selects the hart that is currently being
 289  * debugged.  This doesn't propagate to the hardware. */
 290 void riscv_set_all_rtos_harts(struct target *target);
 291 void riscv_set_rtos_hartid(struct target *target, int hartid);
 292
 293 /* Lists the number of harts in the system, which are assumed to be
 294  * consecutive and start with mhartid=0. */
 295 int riscv_count_harts(struct target *target);
 296
 297 /* Returns TRUE if the target has the given register on the given hart.  */
 298 bool riscv_has_register(struct target *target, int hartid, int regid);
 299
 300 /** Set register, updating the cache. */
 301 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
 302 /** Set register, updating the cache. */
 303 int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
 304 /** Get register, from the cache if it's in there. */
 305 int riscv_get_register(struct target *target, riscv_reg_t *value,
 306                 enum gdb_regno r);
 307 /** Get register, from the cache if it's in there. */
 308 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
 309                 int hartid, enum gdb_regno regid);
 310
 311 /* Checks the state of the current hart -- "is_halted" checks the actual
 312  * on-device register. */
 313 bool riscv_is_halted(struct target *target);
 314 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
 315
 316 /* These helper functions let the generic program interface get target-specific
 317  * information. */
 318 size_t riscv_debug_buffer_size(struct target *target);
 319
 320 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
 321 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
 322 int riscv_execute_debug_buffer(struct target *target);
 323
 324 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
 325 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
 326 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
 327 int riscv_dmi_write_u64_bits(struct target *target);
 328
 329 /* Invalidates the register cache. */
 330 void riscv_invalidate_register_cache(struct target *target);
 331
 332 /* Returns TRUE when a hart is enabled in this target. */
 333 bool riscv_hart_enabled(struct target *target, int hartid);
 334
 335 int riscv_enumerate_triggers(struct target *target);
 336
 337 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 338 int riscv_remove_breakpoint(struct target *target,
 339                 struct breakpoint *breakpoint);
 340 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 341 int riscv_remove_watchpoint(struct target *target,
 342                 struct watchpoint *watchpoint);
 343 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
 344
 345 int riscv_init_registers(struct target *target);
 346
 347 void riscv_semihosting_init(struct target *target);
 348 typedef enum {
 349         SEMI_NONE,              /* Not halted for a semihosting call. */
 350         SEMI_HANDLED,   /* Call handled, and target was resumed. */
 351         SEMI_WAITING,   /* Call handled, target is halted waiting until we can resume. */
 352         SEMI_ERROR              /* Something went wrong. */
 353 } semihosting_result_t;
 354 semihosting_result_t riscv_semihosting(struct target *target, int *retval);
 355
 356 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
 357                 riscv_bscan_tunneled_scan_context_t *ctxt);
 358
 359 #endif